== Series Details ==
Series: drm/i915: Add lmem fault handler (rev2)
URL : https://patchwork.freedesktop.org/series/70485/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7535 -> Patchwork_15685
Summary
---
**FAILURE**
Now that we changed execbuf submission slightly to allow us to do all
pinning in one place, we can now simply add ww versions on top of
struct_mutex. All we have to do is a separate path for -EDEADLK
handling, which needs to unpin all gem bo's before dropping the lock,
then starting over.
This fin
== Series Details ==
Series: drm/i915: Add DPCD quirk for AUO PSR2 panel
URL : https://patchwork.freedesktop.org/series/70702/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7534_full -> Patchwork_15676_full
Summary
---
== Series Details ==
Series: drm/i915/display: remove duplicated assignment to pointer crtc_state
(rev2)
URL : https://patchwork.freedesktop.org/series/70695/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7535 -> Patchwork_15686
===
Quoting Chris Wilson (2019-12-07 19:01:03)
> The cmdparser rejection debug is not for driver development, but for the
> user, for which we use a plain DRM_DEBUG().
>
> Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Regards, Joonas
___
Intel
On Tue, 10 Dec 2019, Stephen Rothwell wrote:
> Hi all,
>
> [Just adding Dave Airlie to the cc list]
>
> On Tue, 10 Dec 2019 09:39:57 +1100 Stephen Rothwell
> wrote:
>>
>> After merging the drm-intel tree, today's linux-next build (x86_64
>> allmodconfig) failed like this:
FYI, I've now backmerg
== Series Details ==
Series: drm/i915: Improve execbuf debug (rev3)
URL : https://patchwork.freedesktop.org/series/70625/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7534_full -> Patchwork_15677_full
Summary
---
**
Quoting Abdiel Janulgue (2019-12-11 05:59:07)
> Fault handler to handle missing pages for lmem objects.
>
> v2: Handle ENXIO in fault error, account for offset in region start
> for fake lmem (Matt).
> Add selftest (Chris).
>
> Signed-off-by: Abdiel Janulgue
> Signed-off-by: Matthew Auld
Quoting Chris Wilson (2019-12-07 19:01:05)
> We need to flush the destination buffer, even on error, to maintain
> consistent cache state. Thereby removing the jump on error past the
> clear, and reducing the loop-escape mechanism to a mere break.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Joo
Quoting Chris Wilson (2019-12-07 19:01:04)
> Declutter the calling interface by reducing the parameters to the
> i915_vma and associated offsets.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Regards, Joonas
___
Intel-gfx mailing list
Quoting Chris Wilson (2019-12-07 19:01:06)
> As the caller no longer uses the i915_vma result, stop returning it and
> just return the error code instead.
>
> Signed-off-by: Chris Wilson
> @@ -2002,8 +2007,6 @@ static struct i915_vma *eb_parse(struct i915_execbuffer
> *eb)
>
Messages displayed on SKIPs introduced by commit 92caadb4e551
("tests/prime_vgem: Skip basic-read/write subtests if not supported")
don't inform clearly enough that those SKIPs are expected behavior.
Fix it.
Signed-off-by: Janusz Krzysztofik
Cc: Ewelina Musial
---
tests/prime_vgem.c | 9 ++-
Quoting Chris Wilson (2019-12-07 19:01:07)
> The movntqda requires 16-byte alignment for the source pointer. Avoid
> falling back to clflush if the source pointer is misaligned by doing the
> doing a small uncached memcpy to fixup the alignments.
>
> Signed-off-by: Chris Wilson
> @@ -1150,19 +
On Thu, 05 Dec 2019, Anshuamn Gupta wrote:
> On 2019-12-05 at 18:05:13 +0530, Animesh Manna wrote:
>> As the current usage is restricted to first DSB instance per pipe, so
>> existing code could not catch the issue to calculate the mmio offset
>> of different DSB instance per pipe. Corrected the o
On Fri, 15 Nov 2019, Chris Wilson wrote:
> Quoting Jani Nikula (2019-11-15 11:04:28)
>> On Fri, 15 Nov 2019, Chris Wilson wrote:
>> > Quoting Jani Nikula (2019-11-15 10:18:40)
>> >> Get rid of the module specific static variable.
>> >>
>> >> Signed-off-by: Jani Nikula
>> >> ---
>> >> drivers/g
The cmdparser rejection debug is not for driver development, but for the
user, for which we use a plain DRM_DEBUG().
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 55 +-
1 file changed, 27 insertions(+), 28 deletion
Declutter the calling interface by reducing the parameters to the
i915_vma and associated offsets.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 33 +-
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 21
drivers/gpu/drm/i
As the caller no longer uses the i915_vma result, stop returning it and
just return the error code instead.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 39 +--
1 file changed, 18 insertions(+), 21 deletions(-)
dif
We need to flush the destination buffer, even on error, to maintain
consistent cache state. Thereby removing the jump on error past the
clear, and reducing the loop-escape mechanism to a mere break.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_cmd_parse
The movntqda requires 16-byte alignment for the source pointer. Avoid
falling back to clflush if the source pointer is misaligned by doing the
doing a small uncached memcpy to fixup the alignments.
v2: Turn the unaligned copy into a genuine helper
Signed-off-by: Chris Wilson
Reviewed-by: Joonas
Commit 4d89adc7b56f ("drm/i915/display/dsi: Add support to pipe D")
added pipe D support for DSI, but failed to update the state readout.
Fixes: 4d89adc7b56f ("drm/i915/display/dsi: Add support to pipe D")
Cc: Lucas De Marchi
Cc: José Roberto de Souza
Cc: Vandita Kulkarni
Signed-off-by: Jani Ni
On Tue, 10 Dec 2019, Miguel Ojeda wrote:
> On Mon, Dec 9, 2019 at 3:04 PM Jani Nikula wrote:
>>
>> On Tue, 03 Dec 2019, Jani Nikula wrote:
>> > Now that the fbops member of struct fb_info is const, we can start
>> > making the ops const as well.
>> >
>> > Cc: Miguel Ojeda Sandonis
>> > Cc: Robi
Quoting Chris Wilson (2019-12-07 19:01:08)
> The gen7 cmdparser is primarily a promotion-based system to allow access
> to additional registers beyond the HW validation, and allows fallback to
> normal execution of the user batch buffer if valid and requires
> chaining. In the next patch, we will d
== Series Details ==
Series: Simplify GuC communication handling
URL : https://patchwork.freedesktop.org/series/70717/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7534_full -> Patchwork_15681_full
Summary
---
**FAI
Quoting Joonas Lahtinen (2019-12-11 11:27:17)
> Quoting Chris Wilson (2019-12-07 19:01:08)
> > The gen7 cmdparser is primarily a promotion-based system to allow access
> > to additional registers beyond the HW validation, and allows fallback to
> > normal execution of the user batch buffer if valid
Quoting Patchwork (2019-12-11 11:33:35)
> Possible regressions
>
> * igt@gem_exec_parallel@rcs0-contexts:
> - shard-iclb: [PASS][1] -> [CRASH][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7534/shard-iclb4/igt@gem_exec_paral...@rcs0-contexts.html
>[2]:
== Series Details ==
Series: drm/i915: timeline semaphore support
URL : https://patchwork.freedesktop.org/series/70728/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7534_full -> Patchwork_15683_full
Summary
---
**FA
There is no need to pass explicit gt since we already have
a trick to get parent gt from uc_fw, we only need to use it.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +-
drivers/gp
There is no need to pass explicit i915/gt/ggtt params since we
already have a debug trick to get parent gt from uc_fw, and thus
access i915/gt/ggtt implicitly, we only need to make this trick
available on non-debug builds.
Michal Wajdeczko (3):
drm/i915/uc: Drop explicit i915 param in some uc_fw
There is no need to pass explicit ggtt since we already have
a trick to get parent gt from uc_fw, we only need to use it.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff
There is no need to pass explicit i915 since we already have
a debug trick to get parent gt from uc_fw, we only need to
make this trick available on non-debug builds.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c| 5 ++---
drivers/gpu/
On Tue, 10 Dec 2019 22:09:15 +0100, Daniele Ceraolo Spurio
wrote:
The only difference from the GuC POV between guc_communication_stop and
guc_communication_disable is that the former can be called after GuC
has been reset. Instead of having two separate paths, we can just skip
the call into G
+ Daniel/Maarten for the dma_resv
Quoting Chris Wilson (2019-12-07 19:01:09)
> Execute the cmdparser asynchronously as part of the submission pipeline.
> Using our dma-fences, we can schedule execution after an asynchronous
> piece of work, so we move the cmdparser out from under the struct_mutex
== Series Details ==
Series: drm/i915/execbuf: Add support for parallel execbuf submission. (rev3)
URL : https://patchwork.freedesktop.org/series/70680/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7540 -> Patchwork_15687
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: Fix cmdparser drm.debug
URL : https://patchwork.freedesktop.org/series/70751/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
932afa9f6249 drm/i915: Fix cmdparser drm.debug
d6fc56037549 drm/i915: Remove redundan
As we use the active state to keep the vma alive while we are reading
its contents during GPU error capture, we need to mark the
context->state vma as active during execution if we want to include it
in the error state.
Reported-by: Lionel Landwerlin
Fixes: b1e3177bd1d8 ("drm/i915: Coordinate i91
As we use the active state to keep the vma alive while we are reading
its contents during GPU error capture, we need to mark the
ring->vma as active during execution if we want to include the rinbuffer
in the error state.
Reported-by: Lionel Landwerlin
Fixes: b1e3177bd1d8 ("drm/i915: Coordinate i
On Tue, 10 Dec 2019 22:09:16 +0100, Daniele Ceraolo Spurio
wrote:
The GuC supports having multiple CT buffer pairs and we designed our
implementation with that in mind. However, the different channels are not
processed in parallel within the GuC, so there is very little advantage
in having mu
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: Fix cmdparser drm.debug
URL : https://patchwork.freedesktop.org/series/70751/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7540 -> Patchwork_15688
Summar
On Tue, 10 Dec 2019 22:09:17 +0100, Daniele Ceraolo Spurio
wrote:
Since we started using CT buffers on all gens, the function pointers can
only be set to either the _nop() or the _ct() functions. Since the
_nop() case applies to when the CT are disabled, we can just handle that
case in the _c
From: Ville Syrjälä
The linetime watermarks really have very little in common with the
plane watermarks. It looks to be cleaner to simply track them in
the crtc_state and program them from the normal modeset/fastset
paths.
The only dark cloud comes from the fact that the register is
still suppos
On Tue, 10 Dec 2019 22:09:18 +0100, Daniele Ceraolo Spurio
wrote:
The Gen11+ and the legacy function differ in the register and value
written to interrupt the GuC. However, while on older gen the value
matches a bit on the register, on Gen11+ the value is a SW defined
payload that is sent to
== Series Details ==
Series: drm/i915/display: remove duplicated assignment to pointer crtc_state
(rev2)
URL : https://patchwork.freedesktop.org/series/70695/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7535_full -> Patchwork_15686_full
=
== Series Details ==
Series: drm/i915/dsi: fix pipe D readout for DSI transcoders
URL : https://patchwork.freedesktop.org/series/70752/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7540 -> Patchwork_15689
Summary
---
Use the dev_name(i915) to identify the requests for debugging, so we can
tell different device timelines apart.
Signed-off-by: Chris Wilson
Cc: Venkata Sandeep Dhanalakota
---
drivers/gpu/drm/i915/i915_request.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
Quoting Jani Nikula (2019-12-11 12:36:10)
> On Fri, 15 Nov 2019, Chris Wilson wrote:
> > Quoting Jani Nikula (2019-11-15 11:04:28)
> >> On Fri, 15 Nov 2019, Chris Wilson wrote:
> >> > Quoting Jani Nikula (2019-11-15 10:18:40)
> >> >> Get rid of the module specific static variable.
> >> >>
> >> >
Quoting Abdiel Janulgue (2019-12-11 05:59:07)
> Fault handler to handle missing pages for lmem objects.
>
> v2: Handle ENXIO in fault error, account for offset in region start
> for fake lmem (Matt).
> Add selftest (Chris).
>
> Signed-off-by: Abdiel Janulgue
> Signed-off-by: Matthew Auld
On 19/12/11 03:02, Chris Wilson wrote:
> Use the dev_name(i915) to identify the requests for debugging, so we can
> tell different device timelines apart.
>
> Signed-off-by: Chris Wilson
> Cc: Venkata Sandeep Dhanalakota
> ---
> drivers/gpu/drm/i915/i915_request.c | 2 +-
> 1 file changed, 1 in
Quoting Venkata Sandeep Dhanalakota (2019-12-11 15:59:09)
> On 19/12/11 03:02, Chris Wilson wrote:
> > Use the dev_name(i915) to identify the requests for debugging, so we can
> > tell different device timelines apart.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Venkata Sandeep Dhanalakota
> > -
We do not require to register the sysctl paths per instance,
so making registration global.
Cc: Sudeep Dutt
Cc: Rodrigo Vivi
Cc: Daniel Vetter
Cc: Chris Wilson
Cc: Jani Nikula
Signed-off-by: Venkata Sandeep Dhanalakota
---
drivers/gpu/drm/i915/i915_perf.c | 10 --
drivers/gpu/
Make each instance to report the hang only once.
Cc: Sudeep Dutt
Cc: Rodrigo Vivi
Cc: Daniel Vetter
Cc: Chris Wilson
Cc: Jani Nikula
Signed-off-by: Venkata Sandeep Dhanalakota
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gpu_error.c | 3 +--
2 files changed, 3
On 19/12/11 04:07, Chris Wilson wrote:
> Quoting Venkata Sandeep Dhanalakota (2019-12-11 15:59:09)
> > On 19/12/11 03:02, Chris Wilson wrote:
> > > Use the dev_name(i915) to identify the requests for debugging, so we can
> > > tell different device timelines apart.
> > >
> > > Signed-off-by: Chris
On 11/12/2019 18:07, Venkata Sandeep Dhanalakota wrote:
We do not require to register the sysctl paths per instance,
so making registration global.
Cc: Sudeep Dutt
Cc: Rodrigo Vivi
Cc: Daniel Vetter
Cc: Chris Wilson
Cc: Jani Nikula
Signed-off-by: Venkata Sandeep Dhanalakota
Not sure wha
Quoting Venkata Sandeep Dhanalakota (2019-12-11 16:07:24)
> Make each instance to report the hang only once.
>
> Cc: Sudeep Dutt
> Cc: Rodrigo Vivi
> Cc: Daniel Vetter
> Cc: Chris Wilson
> Cc: Jani Nikula
> Signed-off-by: Venkata Sandeep Dhanalakota
I still don't think so, since the we only
Quoting Chris Wilson (2019-12-11 16:17:23)
> Quoting Venkata Sandeep Dhanalakota (2019-12-11 16:07:24)
> > Make each instance to report the hang only once.
> >
> > Cc: Sudeep Dutt
> > Cc: Rodrigo Vivi
> > Cc: Daniel Vetter
> > Cc: Chris Wilson
> > Cc: Jani Nikula
> > Signed-off-by: Venkata Sa
On Tue, Dec 10, 2019 at 02:23:49PM +, Colin King wrote:
> From: Colin Ian King
>
> A prior check and return when pointer fb is null makes
> subsequent null checks on fb redundant. Remove the redundant
> null checks.
>
> Addresses-Coverity: ("Logically dead code")
> Signed-off-by: Colin Ian
This should bring the fi-icl-dsi host on CI back online. It's using the
wrong registers for DSC.
Unfortunately intel_dsc_power_domain() remains broken for DSI, for all
generations. The rabbit hole goes deeper; POWER_DOMAIN_TRANSCODER() is
also broken for DSI transcoders, beyond DSC and beyond the
On Tue, Dec 10, 2019 at 02:45:35PM +, Colin King wrote:
> From: Colin Ian King
>
> Pointer crtc_state is being assigned twice, one of these is redundant
> and can be removed.
>
> Addresses-Coverity: ("Evaluation order violation")
> Signed-off-by: Colin Ian King
> ---
> drivers/gpu/drm/i915
ICL eDP and DSI transcoders have a DSC engine separate from the
pipe. Abstract the register selection and fix it for ICL.
Add a warning for pipe A DSC on ICL; it does not exist.
Cc: Manasi Navare
Cc: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 5
The check for cpu_transcoder != TRANSCODER_A is more magic than
necessary, and potentially misleading. Before TGL, DSC is supported on
pipe A if, and only if, it's used with eDP or DSI transcoders. No
functional changes.
Cc: Manasi Navare
Cc: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
dri
Quoting Michal Wajdeczko (2019-12-11 12:45:48)
> There is no need to pass explicit gt since we already have
> a trick to get parent gt from uc_fw, we only need to use it.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Daniele Ceraolo Spurio
Reviewed-by: Chris Wilson
-Chris
__
Quoting Michal Wajdeczko (2019-12-11 12:45:47)
> There is no need to pass explicit i915 since we already have
> a debug trick to get parent gt from uc_fw, we only need to
> make this trick available on non-debug builds.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Daniele Ceraolo Spurio
Reviewed-by
Quoting Michal Wajdeczko (2019-12-11 12:45:49)
> There is no need to pass explicit ggtt since we already have
> a trick to get parent gt from uc_fw, we only need to use it.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Daniele Ceraolo Spurio
Reviewed-by: Chris Wilson
-Chris
On 11/12/2019 16:07, Venkata Sandeep Dhanalakota wrote:
We do not require to register the sysctl paths per instance,
so making registration global.
Cc: Sudeep Dutt
Cc: Rodrigo Vivi
Cc: Daniel Vetter
Cc: Chris Wilson
Cc: Jani Nikula
Signed-off-by: Venkata Sandeep Dhanalakota
---
drivers
On 11/12/2019 16:31, Tvrtko Ursulin wrote:
On 11/12/2019 16:07, Venkata Sandeep Dhanalakota wrote:
We do not require to register the sysctl paths per instance,
so making registration global.
Cc: Sudeep Dutt
Cc: Rodrigo Vivi
Cc: Daniel Vetter
Cc: Chris Wilson
Cc: Jani Nikula
Signed-off-by:
Validate that the cmdparser works with whatever offset we use for our
batches.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_parse.c | 55 +++--
1 file changed, 46 insertions(+), 9 deletions(-)
diff --git a/tests/i915/gem_exec_parse.c b/tests/i915/gem_exec_
On 12/5/19 11:14 PM, Lucas De Marchi wrote:
Pass the correct variable as argument.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/
On 19/12/11 04:39, Tvrtko Ursulin wrote:
>
> On 11/12/2019 16:31, Tvrtko Ursulin wrote:
> > On 11/12/2019 16:07, Venkata Sandeep Dhanalakota wrote:
> > > We do not require to register the sysctl paths per instance,
> > > so making registration global.
> > >
> > > Cc: Sudeep Dutt
> > > Cc: Rodrig
On 11/12/2019 17:13, Venkata Sandeep Dhanalakota wrote:
On 19/12/11 04:39, Tvrtko Ursulin wrote:
On 11/12/2019 16:31, Tvrtko Ursulin wrote:
On 11/12/2019 16:07, Venkata Sandeep Dhanalakota wrote:
We do not require to register the sysctl paths per instance,
so making registration global.
Cc:
Hi Lee,
On 10-12-2019 09:51, Lee Jones wrote:
On Tue, 19 Nov 2019, Hans de Goede wrote:
At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
different PWM controllers for controlling the LCD's backlight brightness.
Either the one integrated into the PMIC or the one integrate
Hi,
On 11-12-2019 01:24, Linus Walleij wrote:
On Mon, Dec 2, 2019 at 4:49 PM Hans de Goede wrote:
There is only one problem, currently is is not possible to
unregister a mapping added with pinctrl_register_mappings
and the i915 driver is typically a module which can be unloaded
and I believe
On 12/11/19 5:43 AM, Michal Wajdeczko wrote:
On Tue, 10 Dec 2019 22:09:16 +0100, Daniele Ceraolo Spurio
wrote:
The GuC supports having multiple CT buffer pairs and we designed our
implementation with that in mind. However, the different channels are not
processed in parallel within the GuC
On Wed, 2019-12-11 at 13:08 +0200, Jani Nikula wrote:
> Commit 4d89adc7b56f ("drm/i915/display/dsi: Add support to pipe D")
> added pipe D support for DSI, but failed to update the state readout.
>
Reviewed-by: José Roberto de Souza
> Fixes: 4d89adc7b56f ("drm/i915/display/dsi: Add support to p
On 12/11/19 6:04 AM, Michal Wajdeczko wrote:
On Tue, 10 Dec 2019 22:09:17 +0100, Daniele Ceraolo Spurio
wrote:
Since we started using CT buffers on all gens, the function pointers can
only be set to either the _nop() or the _ct() functions. Since the
_nop() case applies to when the CT are
== Series Details ==
Series: Drop some explicit params in uc_fw functions
URL : https://patchwork.freedesktop.org/series/70758/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7543 -> Patchwork_15690
Summary
---
**SUCC
From: Ville Syrjälä
Let's get rid of the redundant intel_ prefix on our variables.
Reviewed-by: José Roberto de Souza
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 32 ++--
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/driver
intel_connector_needs_modeset() will be used outside of
intel_display.c in a future patch so it would only be necessary to
remove the state and add the prototype to the header file.
But while at it, I simplified the arguments and changed to intel
types and moved it to a better place intel_atomic.c
Check if fastset is allowed by external dependencies like other pipes
and transcoders.
Right now it only forces a fullmodeset when the MST master transcoder
did not changed but the pipe of the master transcoder needs a
fullmodeset so all slaves also needs to do a fullmodeset.
But it will probably
On TGL the blending of all the streams have moved from DDI to
transcoder, so now every transcoder working over the same MST port must
send its stream to a master transcoder and master will send to DDI
respecting the time slots.
So here adding all the CRTCs that shares the same MST stream if
needed
The disable sequence after wait for transcoder off was not correctly
implemented.
The MST disable sequence is basically the same for HSW, SKL, ICL and
TGL, with just minor changes for TGL.
So here calling a new MST function to do the MST sequences, most of
the steps just moved from the post disabl
From: Ville Syrjälä
Annoyingly __drm_atomic_helper_crtc_reset() does two
totally separate things:
a) reset the state to defaults values
b) assign the crtc->state pointer
I just want a) without the b) so let's split out part
a) into __drm_atomic_helper_crtc_state_reset(). And
of course we'll do t
From: Ville Syrjälä
We already have alloc/free helpers for planes, add the same for
crtcs. The main benefit is we get to move all the annoying state
initialization out of the main crtc_init() flow.
Reviewed-by: José Roberto de Souza
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/displa
This function is only called from port sync and it is identical to
what will be executed again in intel_update_crtc() over port sync
pipes.
If it is really necessary it at least deserves a better name and a
comment, leaving it to people working on port sync.
Cc: Ville Syrjälä
Cc: Maarten Lankhors
Due to DDB overlaps the pipe enabling sequence is not always crescent.
As the previous patch selects the smallest pipe/transcoder in the MST
stream to be master and it needs to be enabled first this changes
were needed to guarantee that.
So first lets enable all pipes that did not needed a fullmod
From: Ville Syrjälä
For the sake of symmetry with the crtc stuff let's add
a helper to reset the plane state to sane default values.
For the moment this only gets caller from the plane init.
Reviewed-by: José Roberto de Souza
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel
From: Ville Syrjälä
We have a few places where we want to reset a crtc state to its
default values. Let's add a helper for that. We'll need the new
__drm_atomic_helper_crtc_state_reset() helper for this to allow
us to just reset the state itself without clobbering the
crtc->state pointer.
And wh
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: Fix cmdparser drm.debug (rev2)
URL : https://patchwork.freedesktop.org/series/70751/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e2943a8b9e49 drm/i915: Fix cmdparser drm.debug
da0dfb8ec55a drm/i915: Remove r
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: Fix cmdparser drm.debug (rev2)
URL : https://patchwork.freedesktop.org/series/70751/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7543 -> Patchwork_15692
== Series Details ==
Series: drm/i915: Some cleanup near the SKL wm/ddb area (rev4)
URL : https://patchwork.freedesktop.org/series/67930/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7543 -> Patchwork_15693
Summary
---
On 12/5/19 11:14 PM, Lucas De Marchi wrote:
Instead of "ungated" use the same name for the variable as the bitfield,
making it clearer what's the intent of the checks.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8 +++-
1 file changed, 3 insertions(+),
On 12/5/19 11:14 PM, Lucas De Marchi wrote:
This allows us to isolate reading and writing to the
ICL_DPCLKA_CFGCR0 during the sanitize phase.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 57 +---
1 file changed, 32 insertions(+), 25 dele
Ahead of splitting out the code specific to execlists submission to its
own file, we can re-organize the code within the intel_lrc file to make
that separation clearer. To achieve this, a number of functions have
been split/renamed using the "logical_ring" and "lr_context" naming,
respectively for
Having the virtual engine handling in its own file will make it easier
call it from or modify for the GuC implementation without leaking the
changes in the context management or execlists submission paths.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Matthew Bro
From: Matthew Brost
The upcoming GuC submission code will need to use the structure, so
split it to its own file.
Signed-off-by: Matthew Brost
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Cc: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 103
This has some fixes in the transcoder port sync teardown sequence which
ensures now that the hotplug/unplug is handled gracefully
Manasi Navare (3):
drm/i915/dp: Make sure all tiled connectors get added to the state
with full modeset
drm/i915/dp: Make port sync mode assignments only if all
The new GuC submission code will get rid of the execlists emulation and
move towards being a more independent submission flow. However, given
that the HW underneath is still the same, the generic engine HW setup
and context handling can be shared between the GuC and execlists
submission paths. Curr
While clearing the Ports ync mode enable and master select bits
we need to make sure that we perform a RMW for disable else
it sets the other bits casuing unwanted sideeffects.
Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5
Cc: Ville Syrjälä
Cc: Jani Nikula
Fixes: 51528afe7c5e ("drm
In case of tiled displays, all the tiles are linke dto each other
for transcoder port sync. So in intel_atomic_check() we need to make
sure that we add all the tiles to the modeset and if one of the
tiles needs a full modeset then mark all other tiles for a full modeset.
Suggested-by: Ville Syrjäl
Add an extra check before making master slave assignments for tiled
displays to make sure we make these assignments only if all tiled
connectors are present. If not then initialize the state to defaults
so it does a normal non tiled modeset without transcoder port sync.
Bugzilla: https://gitlab.fr
== Series Details ==
Series: drm/i915: Use the i915_device name for identifying our request fences
URL : https://patchwork.freedesktop.org/series/70761/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
856e7af5a09b drm/i915: Use the i915_device name for identifying our request
fe
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