On 12/5/19 11:14 PM, Lucas De Marchi wrote:
This allows us to isolate reading and writing to the
ICL_DPCLKA_CFGCR0 during the sanitize phase.

Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
---
  drivers/gpu/drm/i915/display/intel_ddi.c | 57 +++++++++++++-----------
  1 file changed, 32 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index ebcc7302706b..3433b0bf4f44 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3003,11 +3003,40 @@ static void icl_unmap_plls_to_ports(struct 
intel_encoder *encoder)
        mutex_unlock(&dev_priv->dpll_lock);
  }
+static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
+                                     u32 port_mask, bool ddi_clk_needed)
+{
+       enum port port;
+       u32 val;
+
+       val = I915_READ(ICL_DPCLKA_CFGCR0);
+       for_each_port_masked(port, port_mask) {
+               enum phy phy = intel_port_to_phy(dev_priv, port);
+
+               bool ddi_clk_ungated = !(val &
+                                        icl_dpclka_cfgcr0_clk_off(dev_priv,
+                                                                  phy));
+
+               if (ddi_clk_needed == ddi_clk_ungated)
+                       continue;
+
+               /*
+                * Punt on the case now where clock is gated, but it would
+                * be needed by the port. Something else is really broken then.
+                */
+               if (WARN_ON(ddi_clk_needed))
+                       continue;
+
+               DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, 
gate it\n",
+                        phy_name(port));
+               val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
+               I915_WRITE(ICL_DPCLKA_CFGCR0, val);
+       }
+}
+
  void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
  {
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-       u32 val;
-       enum port port;
        u32 port_mask;
        bool ddi_clk_needed;
@@ -3056,29 +3085,7 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
                ddi_clk_needed = false;
        }
- val = I915_READ(ICL_DPCLKA_CFGCR0);
-       for_each_port_masked(port, port_mask) {
-               enum phy phy = intel_port_to_phy(dev_priv, port);
-
-               bool ddi_clk_ungated = !(val &
-                                        icl_dpclka_cfgcr0_clk_off(dev_priv,
-                                                                  phy));
-
-               if (ddi_clk_needed == ddi_clk_ungated)
-                       continue;
-
-               /*
-                * Punt on the case now where clock is gated, but it would
-                * be needed by the port. Something else is really broken then.
-                */
-               if (WARN_ON(ddi_clk_needed))
-                       continue;
-
-               DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, 
gate it\n",
-                        phy_name(port));
-               val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
-               I915_WRITE(ICL_DPCLKA_CFGCR0, val);
-       }
+       icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
  }
static void intel_ddi_clk_select(struct intel_encoder *encoder,


No change to functionality.

Reviewed-by: Clint Taylor

-Clint


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