Re: [Intel-gfx] [PATCH v9 04/10] drm/i915/dsb: Indexed register write function for DSB.

2019-09-23 Thread Jani Nikula
On Fri, 20 Sep 2019, Animesh Manna wrote: > On 9/20/2019 5:48 PM, Jani Nikula wrote: >> On Fri, 20 Sep 2019, Animesh Manna wrote: >>> DSB can program large set of data through indexed register write >>> (opcode 0x9) in one shot. DSB feature can be used for bulk register >>> programming e.g. gamma

[Intel-gfx] [PATCH i-g-t] i915/gem_ppgtt: Check for blitter support

2019-09-23 Thread Chris Wilson
Another type of bcs user, hidden away. Signed-off-by: Chris Wilson Cc: Mika Kuoppala --- tests/i915/gem_ppgtt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/i915/gem_ppgtt.c b/tests/i915/gem_ppgtt.c index 0d40a7b78..89cdc4dbc 100644 --- a/tests/i915/gem_ppgtt.c +++ b/tests/i915/gem

Re: [Intel-gfx] [PATCH v9 02/10] drm/i915/dsb: DSB context creation.

2019-09-23 Thread Jani Nikula
On Fri, 20 Sep 2019, Animesh Manna wrote: > This patch adds a function, which will internally get the gem buffer > for DSB engine. The GEM buffer is from global GTT, and is mapped into > CPU domain, contains the data + opcode to be feed to DSB engine. > > v1: Initial version. > > v2: > - removed s

Re: [Intel-gfx] [v4][PATCH 0/3] adding gamma state checker for icl+ platforms

2019-09-23 Thread Jani Nikula
On Sun, 22 Sep 2019, Swati Sharma wrote: > In this patch series, added state checker to validate gamma lut values > for icelake+ platforms. It's extension of the > patch series https://patchwork.freedesktop.org/patch/328246/?series=58039 > which enabled the basic infrastructure and state checker f

[Intel-gfx] [PATCH i-g-t] i915/gem_eio: Include non-context based tests for older kms testing

2019-09-23 Thread Chris Wilson
As not every machine can use contexts, include a non-context reset stress test to run in parallel to enabling/disabling pipes. Signed-off-by: Chris Wilson --- tests/i915/gem_eio.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio

Re: [Intel-gfx] [PATCH i-g-t] i915/gem_ppgtt: Check for blitter support

2019-09-23 Thread Mika Kuoppala
Chris Wilson writes: > Another type of bcs user, hidden away. > > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala Reviewed-by: Mika Kuoppala > --- > tests/i915/gem_ppgtt.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/tests/i915/gem_ppgtt.c b/tests/i915/gem_ppgtt.c > index 0d40a7

Re: [Intel-gfx] [PATCH] drm/i915: save AUD_FREQ_CNTRL state at audio domain suspend

2019-09-23 Thread Jani Nikula
On Fri, 20 Sep 2019, Kai Vehmanen wrote: > When audio power domain is suspended, the display driver must > save state of AUD_FREQ_CNTRL on Tiger Lake and Ice Lake > systems. The initial value of the register is set by BIOS and > is read by driver during the audio component init sequence. > > Cc: J

Re: [Intel-gfx] [PATCH 1/5] drm/i915/execlists: Refactor -EIO markup of hung requests

2019-09-23 Thread Mika Kuoppala
Chris Wilson writes: > Pull setting -EIO on the hung requests into its own utility function. > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 32 +++-- > 1 file changed, 17 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/

[Intel-gfx] [PATCH] drm/i915/execlists: Relax assertion for a pinned context image on reset

2019-09-23 Thread Chris Wilson
A gpu hang can occur at any time, given a sufficiently angry gpu. An example is when it forgets to perform a context-switch at the end of a request, leaving us with a hanging GPU on a completed request. Here, we may retire the request, only leaving its context alive via the active barrier. When we

Re: [Intel-gfx] [PATCH 1/5] drm/i915/execlists: Refactor -EIO markup of hung requests

2019-09-23 Thread Chris Wilson
Quoting Mika Kuoppala (2019-09-23 08:47:18) > Chris Wilson writes: > > > Pull setting -EIO on the hung requests into its own utility function. > > > > Signed-off-by: Chris Wilson > > --- > > drivers/gpu/drm/i915/gt/intel_lrc.c | 32 +++-- > > 1 file changed, 17 insertion

Re: [Intel-gfx] [PATCH v2 1/6] drm/i915: add i915_driver_modeset_remove()

2019-09-23 Thread Jani Nikula
On Fri, 20 Sep 2019, Jani Nikula wrote: > For completeness, add counterpart to i915_driver_modeset_probe() and > remove the asymmetry in the probe/remove parts. No functional changes. > > Reviewed-by: Chris Wilson > Signed-off-by: Jani Nikula Pushed the series, thanks for the review. Now to fig

Re: [Intel-gfx] [PATCH 12/21] drm/i915: Mark up address spaces that may need to allocate

2019-09-23 Thread Tvrtko Ursulin
On 20/09/2019 17:35, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-09-20 17:22:42) On 02/09/2019 05:02, Chris Wilson wrote: Since we cannot allocate underneath the vm->mutex (it is used in the direct-reclaim paths), we need to shift the allocations off into a mutexless worker with fence re

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v3,1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync

2019-09-23 Thread Patchwork
== Series Details == Series: series starting with [v3,1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync URL : https://patchwork.freedesktop.org/series/67043/ State : success == Summary == CI Bug Log - changes from CI_DRM_6935_full -> Patchwork_14

Re: [Intel-gfx] [PATCH v9 04/10] drm/i915/dsb: Indexed register write function for DSB.

2019-09-23 Thread Animesh Manna
On 9/23/2019 1:05 PM, Jani Nikula wrote: On Fri, 20 Sep 2019, Animesh Manna wrote: On 9/20/2019 5:48 PM, Jani Nikula wrote: On Fri, 20 Sep 2019, Animesh Manna wrote: DSB can program large set of data through indexed register write (opcode 0x9) in one shot. DSB feature can be used for bulk

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftests: Verify the LRC register layout between init and HW (rev3)

2019-09-23 Thread Patchwork
== Series Details == Series: series starting with [1/2] drm/i915/selftests: Verify the LRC register layout between init and HW (rev3) URL : https://patchwork.freedesktop.org/series/67018/ State : warning == Summary == $ dim checkpatch origin/drm-tip 09bbb2f5aa68 drm/i915/selftests: Verify the

[Intel-gfx] [PATCH i-g-t] i915/gem_render_copy: Add hang detector

2019-09-23 Thread Chris Wilson
Die early if the GPU hangs during our basic render copy testing, and clean up rather than waiting for multiple different failing batches before detecting our failure. Signed-off-by: Chris Wilson --- tests/i915/gem_render_copy.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/i915/ge

Re: [Intel-gfx] [PATCH 1/5] drm/i915/execlists: Refactor -EIO markup of hung requests

2019-09-23 Thread Tvrtko Ursulin
On 21/09/2019 10:55, Chris Wilson wrote: Pull setting -EIO on the hung requests into its own utility function. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_lrc.c | 32 +++-- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/

Re: [Intel-gfx] [PATCH 1/5] drm/i915/execlists: Refactor -EIO markup of hung requests

2019-09-23 Thread Chris Wilson
Quoting Tvrtko Ursulin (2019-09-23 10:27:01) > > On 21/09/2019 10:55, Chris Wilson wrote: > > Pull setting -EIO on the hung requests into its own utility function. > > > > Signed-off-by: Chris Wilson > > --- > > drivers/gpu/drm/i915/gt/intel_lrc.c | 32 +++-- > > 1 fil

intel-gfx@lists.freedesktop.org

2019-09-23 Thread Chris Wilson
Since amalgamating the queued and active lists in commit 422d7df4f090 ("drm/i915: Replace engine->timeline with a plain list"), performing a i915_request_submit() will remove the request from the execlists priority queue. References: 422d7df4f090 ("drm/i915: Replace engine->timeline with a plain

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: Verify the LRC register layout between init and HW (rev3)

2019-09-23 Thread Patchwork
== Series Details == Series: series starting with [1/2] drm/i915/selftests: Verify the LRC register layout between init and HW (rev3) URL : https://patchwork.freedesktop.org/series/67018/ State : success == Summary == CI Bug Log - changes from CI_DRM_6939 -> Patchwork_14491 ==

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Only enqueue already completed requests

2019-09-23 Thread Tvrtko Ursulin
On 21/09/2019 10:55, Chris Wilson wrote: If we are asked to submit a completed request, just move it onto the active-list without modifying it's payload. If we try to emit the modified payload of a completed request, we risk racing with the ring->head update during retirement which may advance t

intel-gfx@lists.freedesktop.org

2019-09-23 Thread Tvrtko Ursulin
On 23/09/2019 10:40, Chris Wilson wrote: Since amalgamating the queued and active lists in commit 422d7df4f090 ("drm/i915: Replace engine->timeline with a plain list"), performing a i915_request_submit() will remove the request from the execlists priority queue. References: 422d7df4f090 ("drm/i

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Relax assertion for a pinned context image on reset

2019-09-23 Thread Mika Kuoppala
Chris Wilson writes: > A gpu hang can occur at any time, given a sufficiently angry gpu. An > example is when it forgets to perform a context-switch at the end of a > request, leaving us with a hanging GPU on a completed request. Here, we > may retire the request, only leaving its context alive v

Re: [Intel-gfx] [PATCH 1/5] drm/i915/execlists: Refactor -EIO markup of hung requests

2019-09-23 Thread Tvrtko Ursulin
On 23/09/2019 10:35, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-09-23 10:27:01) On 21/09/2019 10:55, Chris Wilson wrote: Pull setting -EIO on the hung requests into its own utility function. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_lrc.c | 32 +++---

[Intel-gfx] [PATCH v2] drm/i915: Create dumb buffer from LMEM

2019-09-23 Thread Ramalingam C
When LMEM is supported, dumb buffer preferred to be created from LMEM. This is developed on top of v3 LMEM series https://patchwork.freedesktop.org/series/56683/. v2: Parameters are reshuffled. [Chris] Signed-off-by: Ramalingam C cc: Matthew Auld --- drivers/gpu/drm/i915/i915_gem.c | 17 +++

Re: [Intel-gfx] [PATCH] drm/i915: Create dumb buffer from LMEM

2019-09-23 Thread Ramalingam C
On 2019-09-19 at 21:05:09 +0100, Chris Wilson wrote: > Quoting Ramalingam C (2019-09-19 19:04:33) > > When LMEM is supported, dumb buffer preferred to be created from LMEM. > > > > This is developed on top of v3 LMEM series > > https://patchwork.freedesktop.org/series/56683/. > > > > Signed-off-b

[Intel-gfx] [PATCH] drm/i915: Allow gen11 to use over 32k long strides

2019-09-23 Thread Juha-Pekka Heikkila
The stride in bytes must not exceed the size of 8K pixels. Linear 64 bpp pixel format maximum stride in tiles is 1024 which would mean gen11 support 64k long stride. Signed-off-by: Juha-Pekka Heikkila --- drivers/gpu/drm/i915/display/intel_sprite.c | 30 +++-- 1 file chan

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Only enqueue already completed requests

2019-09-23 Thread Chris Wilson
Quoting Tvrtko Ursulin (2019-09-23 10:51:48) > > On 21/09/2019 10:55, Chris Wilson wrote: > > If we are asked to submit a completed request, just move it onto the > > active-list without modifying it's payload. If we try to emit the > > modified payload of a completed request, we risk racing with

[Intel-gfx] [RFC v3 5/9] drm/i915: Extract framebufer CCS offset checks into a function

2019-09-23 Thread Dhinakaran Pandiyan
intel_fill_fb_info() has grown quite large and wrapping the offset checks into a separate function makes the loop a bit easier to follow. Cc: Ville Syrjälä Cc: Matt Roper Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/display/intel_display.c | 69 1 file chang

[Intel-gfx] [RFC v3 4/9] drm/i915/tgl: Gen-12 render decompression

2019-09-23 Thread Dhinakaran Pandiyan
Gen-12 display decompression operates on Y-tiled compressed main surface. The CCS is linear and has 4 bits of metadata for each main surface cache line pair, a size ratio of 1:256. Gen-12 display decompression is incompatible with buffers compressed by earlier GPUs, so make use of a new modifier to

[Intel-gfx] [RFC v3 3/9] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment

2019-09-23 Thread Dhinakaran Pandiyan
Easier to read if all the alignment changes are in one place and contained within a function. Cc: Ville Syrjälä Cc: Matt Roper Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/display/intel_display.c | 31 ++-- 1 file changed, 16 insertions(+), 15 deletions(-) diff

[Intel-gfx] [RFC v3 1/9] drm/framebuffer: Format modifier for Intel Gen-12 render compression

2019-09-23 Thread Dhinakaran Pandiyan
Gen-12 has a new compression format, add a new modifier to indicate that. Cc: Ville Syrjälä Cc: Matt Roper Cc: Nanley G Chery Cc: Jason Ekstrand Signed-off-by: Dhinakaran Pandiyan Signed-off-by: Lucas De Marchi --- include/uapi/drm/drm_fourcc.h | 11 +++ 1 file changed, 11 insertion

[Intel-gfx] [RFC v3 6/9] drm/framebuffer: Format modifier for Intel Gen-12 media compression

2019-09-23 Thread Dhinakaran Pandiyan
Gen-12 display can decompress surfaces compressed by the media engine, add a new modifier as the driver needs to know the surface was compressed by the media or render engine. Cc: Nanley G Chery Cc: Matt Roper Cc: Ville Syrjälä Signed-off-by: Dhinakaran Pandiyan Signed-off-by: Lucas De Marchi

[Intel-gfx] [RFC v3 2/9] drm/i915: Use intel_tile_height() instead of re-implementing

2019-09-23 Thread Dhinakaran Pandiyan
intel_tile_dims() computes tile height using size and width, when there is already a function to do just that - intel_tile_height() Cc: Ville Syrjälä Cc: Matt Roper Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 del

[Intel-gfx] [RFC v3 8/9] drm/fb: Extend format_info member arrays to handle four planes

2019-09-23 Thread Dhinakaran Pandiyan
addfb() uAPI has supported four planes for a while now, make format_info compatible with that. Cc: Ville Syrjälä Cc: Matt Roper Signed-off-by: Dhinakaran Pandiyan --- include/drm/drm_fourcc.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/drm/drm_fourcc.h b

[Intel-gfx] [RFC v3 0/9] Gen12 E2E compression

2019-09-23 Thread Dhinakaran Pandiyan
Patches in this series are at two levels of completion. The render decompression patches 1, 2, 3 and 4 address feedback provided for https://patchwork.freedesktop.org/series/66367/ Media decompression patches 5, 6, 7, 8 and 9 are a complete rewrite to handle planar formats and have not been tested

[Intel-gfx] [RFC v3 9/9] Gen-12 display can decompress surfaces compressed by the media engine.

2019-09-23 Thread Dhinakaran Pandiyan
Detect the modifier corresponding to media compression to enable display decompression for YUV and xRGB packed formats. A new modifier is added so that the driver can distinguish between media and render compressed buffers. Unlike render decompression, plane 6 and plane 7 do not support media deco

[Intel-gfx] [RFC v3 7/9] drm/i915: Skip rotated offset adjustment for unsupported modifiers

2019-09-23 Thread Dhinakaran Pandiyan
During framebuffer creation, we pre-compute offsets for 90/270 plane rotation. However, only Y and Yf modifiers support 90/270 rotation. So, skip the calculations for other modifiers. Cc: Matt Roper Cc: Ville Syrjälä Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/display/intel_dis

[Intel-gfx] [PATCH v2] drm/i915: Only enqueue already completed requests

2019-09-23 Thread Chris Wilson
If we are asked to submit a completed request, just move it onto the active-list without modifying it's payload. If we try to emit the modified payload of a completed request, we risk racing with the ring->head update during retirement which may advance the head past our breadcrumb and so we genera

Re: [Intel-gfx] [PATCH] drm/i915: Allow set context SSEU on platforms after gen 11

2019-09-23 Thread Tvrtko Ursulin
Replying with some more information for benefit of archives. On 20/09/2019 22:29, Chris Wilson wrote: Quoting Summers, Stuart (2019-09-20 22:09:46) On Thu, 2019-09-19 at 08:00 +0100, Tvrtko Ursulin wrote: On 18/09/2019 18:31, Stuart Summers wrote: Bugzilla: https://bugs.freedesktop.org/show_b

intel-gfx@lists.freedesktop.org

2019-09-23 Thread Patchwork
== Series Details == Series: drm/i915/execlists: Drop redundant list_del_init(&rq->sched.link) URL : https://patchwork.freedesktop.org/series/67076/ State : warning == Summary == $ dim checkpatch origin/drm-tip ad411b1a5bca drm/i915/execlists: Drop redundant list_del_init(&rq->sched.link) -:12

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/23] drm/i915/dp: Fix dsc bpp calculations, v2.

2019-09-23 Thread Maarten Lankhorst
Op 21-09-2019 om 17:22 schreef Patchwork: > == Series Details == > > Series: series starting with [01/23] drm/i915/dp: Fix dsc bpp calculations, > v2. > URL : https://patchwork.freedesktop.org/series/66998/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_6928_full -> Pat

Re: [Intel-gfx] [PATCH v2] drm/i915: Only enqueue already completed requests

2019-09-23 Thread Tvrtko Ursulin
On 23/09/2019 11:32, Chris Wilson wrote: If we are asked to submit a completed request, just move it onto the active-list without modifying it's payload. If we try to emit the modified payload of a completed request, we risk racing with the ring->head update during retirement which may advance t

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Relax assertion for a pinned context image on reset

2019-09-23 Thread Patchwork
== Series Details == Series: drm/i915/execlists: Relax assertion for a pinned context image on reset URL : https://patchwork.freedesktop.org/series/67069/ State : success == Summary == CI Bug Log - changes from CI_DRM_6939 -> Patchwork_14492

Re: [Intel-gfx] [PATCH v2] drm/i915: Only enqueue already completed requests

2019-09-23 Thread Chris Wilson
Quoting Tvrtko Ursulin (2019-09-23 11:44:01) > > On 23/09/2019 11:32, Chris Wilson wrote: > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c > > b/drivers/gpu/drm/i915/gt/intel_lrc.c > > index 0a4812ebd184..8c1ea5c315ac 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > > +++ b/drivers/gpu/

[Intel-gfx] [CI 4/4] drm/i915/execlists: Refactor -EIO markup of hung requests

2019-09-23 Thread Chris Wilson
Pull setting -EIO on the hung requests into its own utility function. Having allowed ourselves to short-circuit submission of completed requests, we can now do the mark_eio() prior to submission and avoid some redundant operations. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin --- dri

intel-gfx@lists.freedesktop.org

2019-09-23 Thread Chris Wilson
Since amalgamating the queued and active lists in commit 422d7df4f090 ("drm/i915: Replace engine->timeline with a plain list"), performing a i915_request_submit() will remove the request from the execlists priority queue. References: 422d7df4f090 ("drm/i915: Replace engine->timeline with a plain

[Intel-gfx] [CI 1/4] drm/i915/execlists: Relax assertion for a pinned context image on reset

2019-09-23 Thread Chris Wilson
A gpu hang can occur at any time, given a sufficiently angry gpu. An example is when it forgets to perform a context-switch at the end of a request, leaving us with a hanging GPU on a completed request. Here, we may retire the request, only leaving its context alive via the active barrier. When we

[Intel-gfx] [CI 3/4] drm/i915: Only enqueue already completed requests

2019-09-23 Thread Chris Wilson
If we are asked to submit a completed request, just move it onto the active-list without modifying it's payload. If we try to emit the modified payload of a completed request, we risk racing with the ring->head update during retirement which may advance the head past our breadcrumb and so we genera

intel-gfx@lists.freedesktop.org

2019-09-23 Thread Patchwork
== Series Details == Series: drm/i915/execlists: Drop redundant list_del_init(&rq->sched.link) URL : https://patchwork.freedesktop.org/series/67076/ State : success == Summary == CI Bug Log - changes from CI_DRM_6939 -> Patchwork_14493 Summ

Re: [Intel-gfx] i915 firmware updates (CMl- GuC,HuC; TGL-DMC,ICL-DMC, HuC Updates-SKL,BXT,KBL,GLK,ICL)

2019-09-23 Thread Josh Boyer
On Fri, Sep 13, 2019 at 6:30 PM Srivatsa, Anusha wrote: > > Hi, > Kyle, Josh,Ben > > Ignore the previous PR and kindly consider this one. It has another new > update and is the latest one- > > The following changes since commit 6c6918ad8ae0dfb2cb591484eba525409980c16f: > > linux-firmware: Updat

Re: [Intel-gfx] [PATCH v2] drm: Add high-precision time to vblank trace event

2019-09-23 Thread Daniel Vetter
On Sat, Sep 21, 2019 at 10:33 AM Heinrich Fink wrote: > > On Tue, 3 Sep 2019 at 11:53, Daniel Vetter wrote: > > > > On Tue, Sep 03, 2019 at 11:19:19AM +0200, Heinrich Fink wrote: > > > On Tue, 3 Sep 2019 at 09:46, Daniel Vetter wrote: > > > > > > > > On Mon, Sep 02, 2019 at 04:24:12PM +0200, Hei

Re: [Intel-gfx] [RFC PATCH V2 0/6] mdev based hardware virtio offloading support

2019-09-23 Thread Michael S. Tsirkin
On Fri, Sep 20, 2019 at 04:20:44PM +0800, Jason Wang wrote: > Hi all: > > There are hardware that can do virtio datapath offloading while having > its own control path. This path tries to implement a mdev based > unified API to support using kernel virtio driver to drive those > devices. This is d

Re: [Intel-gfx] FW: [PATCH 1/5] drm/i915: Allow i915 to manage the vma offset nodes instead of drm core

2019-09-23 Thread Daniel Vetter
On Thu, Sep 19, 2019 at 3:05 PM Daniel Vetter wrote: > > On Wed, Sep 11, 2019 at 2:19 PM Chris Wilson wrote: > > Quoting Balestrieri, Francesco (2019-09-11 13:03:25) > > > On 04/09/2019, 13.33, "Intel-gfx on behalf of Daniel Vetter" > > > > > > wrote: > > > > > > On Mon, Aug 26, 2019 at 2

[Intel-gfx] [PATCH] drm/i915/tgl: Fix doc not corresponding to code

2019-09-23 Thread Anna Karas
Replace PPLs names used in documentation to that used in the code. Cc: Vandita Kulkarni Fixes: commit d0570414f3d1 ("drm/i915/tgl: Add new pll ids") Signed-off-by: Anna Karas --- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[Intel-gfx] [PATCH 03/36] drm/i915: use bpp instead of cpp for drm_format_info

2019-09-23 Thread Sandy Huang
cpp[BytePerPlane] can't describe the 10bit data format correctly, So we use bpp[BitPerPlane] to instead cpp. Signed-off-by: Sandy Huang --- drivers/gpu/drm/i915/display/intel_atomic_plane.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 28 +++ drivers/gpu/drm/i

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Fix doc not corresponding to code

2019-09-23 Thread Chris Wilson
Quoting Anna Karas (2019-09-23 13:44:35) > Replace PPLs names used in documentation to that used in the code. > > Cc: Vandita Kulkarni > Fixes: commit d0570414f3d1 ("drm/i915/tgl: Add new pll ids") > Signed-off-by: Anna Karas Reviewed-by: Chris Wilson -Chris

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Fix doc not corresponding to code

2019-09-23 Thread Chris Wilson
Aside: can you please resend your earlier patches without the disclaimer? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915/dp: Fix dsc bpp calculations, v3.

2019-09-23 Thread Maarten Lankhorst
There was a integer wraparound when mode_clock became too high, and we didn't correct for the FEC overhead factor when dividing, with the calculations breaking at HBR3. As a result our calculated bpp was way too high, and the link width limitation never came into effect. Print out the resulting b

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Create dumb buffer from LMEM (rev2)

2019-09-23 Thread Patchwork
== Series Details == Series: drm/i915: Create dumb buffer from LMEM (rev2) URL : https://patchwork.freedesktop.org/series/66950/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h A

[Intel-gfx] [PATCH] drm/i915: Describe structure member in documentation

2019-09-23 Thread Anna Karas
Add description of wakeref member of intel_shared_dpll structure to documentation. Cc: Lucas De Marchi Cc: Vivek Kasireddy Signed-off-by: Anna Karas --- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dpl

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Allow gen11 to use over 32k long strides

2019-09-23 Thread Patchwork
== Series Details == Series: drm/i915: Allow gen11 to use over 32k long strides URL : https://patchwork.freedesktop.org/series/67077/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3d2dacc3cf82 drm/i915: Allow gen11 to use over 32k long strides -:33: CHECK:SPACING: spaces prefer

Re: [Intel-gfx] [PATCH] drm/i915/dp: Fix dsc bpp calculations, v3.

2019-09-23 Thread Ville Syrjälä
On Mon, Sep 23, 2019 at 02:52:52PM +0200, Maarten Lankhorst wrote: > There was a integer wraparound when mode_clock became too high, > and we didn't correct for the FEC overhead factor when dividing, > with the calculations breaking at HBR3. > > As a result our calculated bpp was way too high, and

[Intel-gfx] [PATCH 0/6] mdev based hardware virtio offloading support

2019-09-23 Thread Jason Wang
Hi all: There are hardware that can do virtio datapath offloading while having its own control path. This path tries to implement a mdev based unified API to support using kernel virtio driver to drive those devices. This is done by introducing a new mdev transport for virtio (virtio_mdev) and reg

[Intel-gfx] [PATCH 1/6] mdev: class id support

2019-09-23 Thread Jason Wang
Mdev bus only supports vfio driver right now, so it doesn't implement match method. But in the future, we may add drivers other than vfio, one example is virtio-mdev[1] driver. This means we need to add device class id support in bus match method to pair the mdev device and mdev driver correctly.

[Intel-gfx] [PATCH 2/6] mdev: introduce device specific ops

2019-09-23 Thread Jason Wang
Currently, except for the create and remove. The rest of mdev_parent_ops is designed for vfio-mdev driver only and may not help for kernel mdev driver. Follow the class id support by previous patch, this patch introduces device specific ops pointer inside parent ops which points to device specific

[Intel-gfx] [PATCH 3/6] mdev: introduce virtio device and its device ops

2019-09-23 Thread Jason Wang
This patch implements basic support for mdev driver that supports virtio transport for kernel virtio driver. Signed-off-by: Jason Wang --- drivers/vfio/mdev/mdev_core.c | 7 ++ include/linux/mdev.h | 4 + include/linux/virtio_mdev.h | 144 ++ 3 file

[Intel-gfx] [PATCH 4/6] virtio: introduce a mdev based transport

2019-09-23 Thread Jason Wang
This patch introduces a new mdev transport for virtio. This is used to use kernel virtio driver to drive the mediated device that is capable of populating virtqueue directly. A new virtio-mdev driver will be registered to the mdev bus, when a new virtio-mdev device is probed, it will register the

[Intel-gfx] [PATCH 6/6] docs: sample driver to demonstrate how to implement virtio-mdev framework

2019-09-23 Thread Jason Wang
This sample driver creates mdev device that simulate virtio net device over virtio mdev transport. The device is implemented through vringh and workqueue. A device specific dma ops is to make sure HVA is used directly as the IOVA. This should be sufficient for kernel virtio driver to work. Only 'v

[Intel-gfx] [PATCH 5/6] vringh: fix copy direction of vringh_iov_push_kern()

2019-09-23 Thread Jason Wang
We want to copy from iov to buf, so the direction was wrong. Signed-off-by: Jason Wang --- drivers/vhost/vringh.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/vhost/vringh.c b/drivers/vhost/vringh.c index 08ad0d1f0476..a0a2d74967ef 100644 --- a/drivers/vhost

[Intel-gfx] [PATCH] drm/i915: Delete references to non-existing file

2019-09-23 Thread Anna Karas
Delete references to non-existing i915_gem_batch_pool.c file. Cc: Jani Nikula Cc: Chris Wilson Fixes: commit 8675a608a6fe ("drm/i915: Kill the undead i915_gem_batch_pool.c") Signed-off-by: Anna Karas --- Documentation/gpu/i915.rst | 9 - 1 file changed, 9 deletions(-) diff --git a/Doc

Re: [Intel-gfx] [PATCH 02/23] HAX drm/i915: Disable FEC entirely for now

2019-09-23 Thread Maarten Lankhorst
Op 20-09-2019 om 13:42 schreef Maarten Lankhorst: > I get a permanent FIFO underrun when enabling FEC with big joiner, > so for now disable it. > > It seems that even at 1024x768 resolution without bigjoiner we don't > get a working configuration. Flag is set but vblank timing shows that > vblanks

Re: [Intel-gfx] [PATCH] drm/i915: Delete references to non-existing file

2019-09-23 Thread Chris Wilson
Quoting Anna Karas (2019-09-23 14:06:08) > Delete references to non-existing i915_gem_batch_pool.c file. > > Cc: Jani Nikula > Cc: Chris Wilson > Fixes: commit 8675a608a6fe > ("drm/i915: Kill the undead i915_gem_batch_pool.c") This fixes is wrong. 8675a608a6fe is not a commit, but a blob. Hmm.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Allow gen11 to use over 32k long strides

2019-09-23 Thread Patchwork
== Series Details == Series: drm/i915: Allow gen11 to use over 32k long strides URL : https://patchwork.freedesktop.org/series/67077/ State : success == Summary == CI Bug Log - changes from CI_DRM_6939 -> Patchwork_14495 Summary ---

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Fixup preempt-to-busy vs resubmission of a virtual request

2019-09-23 Thread Tvrtko Ursulin
On 21/09/2019 10:55, Chris Wilson wrote: As preempt-to-busy leaves the request on the HW as the resubmission is processed, that request may complete in the background and even cause a second virtual request to enter queue. This second virtual request breaks our "single request in the virtual pip

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Fixup preempt-to-busy vs resubmission of a virtual request

2019-09-23 Thread Chris Wilson
Quoting Tvrtko Ursulin (2019-09-23 14:32:23) > > On 21/09/2019 10:55, Chris Wilson wrote: > > As preempt-to-busy leaves the request on the HW as the resubmission is > > processed, that request may complete in the background and even cause a > > second virtual request to enter queue. This second vi

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Fixup preempt-to-busy vs reset of a virtual request

2019-09-23 Thread Tvrtko Ursulin
On 21/09/2019 10:55, Chris Wilson wrote: Due to the nature of preempt-to-busy the execlists active tracking and the schedule queue may become temporarily desync'ed (between resubmission to HW and its ack from HW). This means that we may have unwound a request and passed it back to the virtual en

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Fixup preempt-to-busy vs resubmission of a virtual request

2019-09-23 Thread Chris Wilson
Quoting Chris Wilson (2019-09-23 14:39:20) > Quoting Tvrtko Ursulin (2019-09-23 14:32:23) > > > > On 21/09/2019 10:55, Chris Wilson wrote: > > > + if (i915_request_completed(rq)) { > > > + __i915_request_submit(rq); > > > + ve->request = NULL; > > > + } else { > > >

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Prevent bonded requests from overtaking each other on preemption

2019-09-23 Thread Tvrtko Ursulin
On 21/09/2019 10:55, Chris Wilson wrote: Force bonded requests to run on distinct engines so that they cannot be shuffled onto the same engine where timeslicing will reverse the order. A bonded request will often wait on a semaphore signaled by its master, creating an implicit dependency -- if w

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/selftests: Verify the LRC register layout between init and HW (rev3)

2019-09-23 Thread Patchwork
== Series Details == Series: series starting with [1/2] drm/i915/selftests: Verify the LRC register layout between init and HW (rev3) URL : https://patchwork.freedesktop.org/series/67018/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6939_full -> Patchwork_14491_full

Re: [Intel-gfx] [PATCH v2 00/21] drm/dp: Various helper improvements and cleanups

2019-09-23 Thread Jani Nikula
On Fri, 20 Sep 2019, Thierry Reding wrote: > On Mon, Sep 02, 2019 at 01:31:00PM +0200, Thierry Reding wrote: >> From: Thierry Reding >> >> Hi, >> >> this series of patches improves the DP helpers a bit and cleans up some >> inconsistencies along the way. >> >> v2 incorporates all review commen

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Prevent bonded requests from overtaking each other on preemption

2019-09-23 Thread Chris Wilson
Quoting Tvrtko Ursulin (2019-09-23 14:48:44) > > On 21/09/2019 10:55, Chris Wilson wrote: > > Force bonded requests to run on distinct engines so that they cannot be > > shuffled onto the same engine where timeslicing will reverse the order. > > A bonded request will often wait on a semaphore sign

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Gen12 E2E compression

2019-09-23 Thread Patchwork
== Series Details == Series: Gen12 E2E compression URL : https://patchwork.freedesktop.org/series/67078/ State : warning == Summary == $ dim checkpatch origin/drm-tip b66ba0b6ed71 drm/framebuffer: Format modifier for Intel Gen-12 render compression 3d964432ccb8 drm/i915: Use intel_tile_height

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Fixup preempt-to-busy vs reset of a virtual request

2019-09-23 Thread Chris Wilson
Quoting Tvrtko Ursulin (2019-09-23 14:46:27) > > On 21/09/2019 10:55, Chris Wilson wrote: > > Due to the nature of preempt-to-busy the execlists active tracking and > > the schedule queue may become temporarily desync'ed (between resubmission > > to HW and its ack from HW). This means that we may

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Fixup preempt-to-busy vs resubmission of a virtual request

2019-09-23 Thread Tvrtko Ursulin
On 23/09/2019 14:39, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-09-23 14:32:23) On 21/09/2019 10:55, Chris Wilson wrote: As preempt-to-busy leaves the request on the HW as the resubmission is processed, that request may complete in the background and even cause a second virtual request

Re: [Intel-gfx] [PATCH 0/6] mdev based hardware virtio offloading support

2019-09-23 Thread Michael S. Tsirkin
On Mon, Sep 23, 2019 at 09:03:25PM +0800, Jason Wang wrote: > Hi all: > > There are hardware that can do virtio datapath offloading while having > its own control path. This path tries to implement a mdev based > unified API to support using kernel virtio driver to drive those > devices. This is d

Re: [Intel-gfx] [PATCH v2] drm: Add high-precision time to vblank trace event

2019-09-23 Thread Heinrich Fink
On Mon, 23 Sep 2019 at 14:06, Daniel Vetter wrote: > > On Sat, Sep 21, 2019 at 10:33 AM Heinrich Fink > wrote: > > > > On Tue, 3 Sep 2019 at 11:53, Daniel Vetter wrote: > > > > > > On Tue, Sep 03, 2019 at 11:19:19AM +0200, Heinrich Fink wrote: > > > > On Tue, 3 Sep 2019 at 09:46, Daniel Vetter

[Intel-gfx] ✗ Fi.CI.BAT: failure for Gen12 E2E compression

2019-09-23 Thread Patchwork
== Series Details == Series: Gen12 E2E compression URL : https://patchwork.freedesktop.org/series/67078/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6939 -> Patchwork_14496 Summary --- **FAILURE** Serious unknow

Re: [Intel-gfx] [PATCH] drm/i915/dp: Fix dsc bpp calculations, v3.

2019-09-23 Thread kbuild test robot
option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Maarten-Lankhorst/drm-i915-dp-Fix-dsc-bpp-calculations-v3/20190923-205540 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: i386

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_exec_balancer: Check for scheduling bonded-pairs on the same engine

2019-09-23 Thread Tvrtko Ursulin
On 20/09/2019 23:26, Chris Wilson wrote: The expectation for bonded submission is that they are run concurrently, in parallel on multiple engines. However, given a lack of constraints in the scheduler's selection combined with timeslicing could mean that the bonded requests could be run in oppos

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Fix doc not corresponding to code

2019-09-23 Thread Kulkarni, Vandita
> -Original Message- > From: Karas, Anna > Sent: Monday, September 23, 2019 6:15 PM > To: intel-gfx@lists.freedesktop.org > Cc: Kulkarni, Vandita > Subject: [PATCH] drm/i915/tgl: Fix doc not corresponding to code > > Replace PPLs names used in documentation to that used in the code. "PL

[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/5] drm/i915/execlists: Refactor -EIO markup of hung requests (rev3)

2019-09-23 Thread Patchwork
== Series Details == Series: series starting with [1/5] drm/i915/execlists: Refactor -EIO markup of hung requests (rev3) URL : https://patchwork.freedesktop.org/series/67033/ State : failure == Summary == Applying: drm/i915/execlists: Refactor -EIO markup of hung requests Applying: drm/i915:

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_render_copy: Add hang detector

2019-09-23 Thread Ville Syrjälä
On Mon, Sep 23, 2019 at 10:24:32AM +0100, Chris Wilson wrote: > Die early if the GPU hangs during our basic render copy testing, and > clean up rather than waiting for multiple different failing batches > before detecting our failure. Seems sensible. Reviewed-by: Ville Syrjälä > > Signed-off-b

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/4] drm/i915/execlists: Relax assertion for a pinned context image on reset

2019-09-23 Thread Patchwork
== Series Details == Series: series starting with [CI,1/4] drm/i915/execlists: Relax assertion for a pinned context image on reset URL : https://patchwork.freedesktop.org/series/67080/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9ee0411b89ae drm/i915/execlists: Relax asserti

[Intel-gfx] [PATCH] drm/i915/dp: Fix dsc bpp calculations, v4.

2019-09-23 Thread Maarten Lankhorst
There was a integer wraparound when mode_clock became too high, and we didn't correct for the FEC overhead factor when dividing, with the calculations breaking at HBR3. As a result our calculated bpp was way too high, and the link width limitation never came into effect. Print out the resulting b

Re: [Intel-gfx] [PATCH] drm/i915/dp: Fix dsc bpp calculations, v4.

2019-09-23 Thread Maarten Lankhorst
Op 23-09-2019 om 16:49 schreef Maarten Lankhorst: > There was a integer wraparound when mode_clock became too high, > and we didn't correct for the FEC overhead factor when dividing, > with the calculations breaking at HBR3. > > As a result our calculated bpp was way too high, and the link width >

Re: [Intel-gfx] [PATCH v2 00/21] drm/dp: Various helper improvements and cleanups

2019-09-23 Thread Thierry Reding
On Mon, Sep 23, 2019 at 04:52:50PM +0300, Jani Nikula wrote: > On Fri, 20 Sep 2019, Thierry Reding wrote: > > On Mon, Sep 02, 2019 at 01:31:00PM +0200, Thierry Reding wrote: > >> From: Thierry Reding > >> > >> Hi, > >> > >> this series of patches improves the DP helpers a bit and cleans up some

Re: [Intel-gfx] [PATCH] drm/i915/dp: Fix dsc bpp calculations, v4.

2019-09-23 Thread Ville Syrjälä
On Mon, Sep 23, 2019 at 04:49:47PM +0200, Maarten Lankhorst wrote: > There was a integer wraparound when mode_clock became too high, > and we didn't correct for the FEC overhead factor when dividing, > with the calculations breaking at HBR3. > > As a result our calculated bpp was way too high, and

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/execlists: Relax assertion for a pinned context image on reset

2019-09-23 Thread Patchwork
== Series Details == Series: drm/i915/execlists: Relax assertion for a pinned context image on reset URL : https://patchwork.freedesktop.org/series/67069/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6939_full -> Patchwork_14492_full ==

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915/execlists: Relax assertion for a pinned context image on reset

2019-09-23 Thread Patchwork
== Series Details == Series: series starting with [CI,1/4] drm/i915/execlists: Relax assertion for a pinned context image on reset URL : https://patchwork.freedesktop.org/series/67080/ State : success == Summary == CI Bug Log - changes from CI_DRM_6940 -> Patchwork_14498 =

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