On Fri, 20 Sep 2019, Animesh Manna <animesh.ma...@intel.com> wrote:
> This patch adds a function, which will internally get the gem buffer
> for DSB engine. The GEM buffer is from global GTT, and is mapped into
> CPU domain, contains the data + opcode to be feed to DSB engine.
>
> v1: Initial version.
>
> v2:
> - removed some unwanted code. (Chris)
> - Used i915_gem_object_create_internal instead of _shmem. (Chris)
> - cmd_buf_tail removed and can be derived through vma object. (Chris)
>
> v3: vma realeased if i915_gem_object_pin_map() failed. (Shashank)
>
> v4: for simplification and based on current usage added single dsb
> object in intel_crtc. (Shashank)
>
> v5: seting NULL to cmd_buf moved outside of mutex in dsb-put(). (Shashank)
>
> v6:
> - refcount machanism added.
> - Used atomic_add_return and atomic_dec_and_test instead of
> atomic_inc and atomic_dec. (Jani)
>
> Cc: Imre Deak <imre.d...@intel.com>
> Cc: Michel Thierry <michel.thie...@intel.com>
> Cc: Jani Nikula <jani.nik...@intel.com>
> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> Cc: Shashank Sharma <shashank.sha...@intel.com>
> Signed-off-by: Animesh Manna <animesh.ma...@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> .../drm/i915/display/intel_display_types.h | 3 +
> drivers/gpu/drm/i915/display/intel_dsb.c | 80 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dsb.h | 31 +++++++
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> 5 files changed, 116 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 658b930d34a8..6313e7b4bd78 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -172,6 +172,7 @@ i915-y += \
> display/intel_display_power.o \
> display/intel_dpio_phy.o \
> display/intel_dpll_mgr.o \
> + display/intel_dsb.o \
> display/intel_fbc.o \
> display/intel_fifo_underrun.o \
> display/intel_frontbuffer.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d5cc4b810d9e..49c902b00484 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1033,6 +1033,9 @@ struct intel_crtc {
>
> /* scalers available on this crtc */
> int num_scalers;
> +
> + /* per pipe DSB related info */
> + struct intel_dsb dsb;
> };
>
> struct intel_plane {
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> new file mode 100644
> index 000000000000..2ed277670f15
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -0,0 +1,80 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + */
> +
> +#include "i915_drv.h"
> +#include "intel_display_types.h"
> +
> +#define DSB_BUF_SIZE (2 * PAGE_SIZE)
> +
> +struct intel_dsb *
> +intel_dsb_get(struct intel_crtc *crtc)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *i915 = to_i915(dev);
> + struct intel_dsb *dsb = &crtc->dsb;
> + struct drm_i915_gem_object *obj;
> + struct i915_vma *vma;
> + intel_wakeref_t wakeref;
> +
> + if (!HAS_DSB(i915))
> + return dsb;
> +
> + if (atomic_add_return(1, &dsb->refcount) != 1)
> + return dsb;
> +
> + dsb->id = DSB1;
> + wakeref = intel_runtime_pm_get(&i915->runtime_pm);
> +
> + obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
> + if (IS_ERR(obj)) {
> + DRM_ERROR("Gem object creation failed\n");
> + goto err;
> + }
> +
> + mutex_lock(&i915->drm.struct_mutex);
> + vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
> + mutex_unlock(&i915->drm.struct_mutex);
> + if (IS_ERR(vma)) {
> + DRM_ERROR("Vma creation failed\n");
> + i915_gem_object_put(obj);
> + atomic_dec(&dsb->refcount);
> + goto err;
> + }
> +
> + dsb->cmd_buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
> + if (IS_ERR(dsb->cmd_buf)) {
> + DRM_ERROR("Command buffer creation failed\n");
> + i915_vma_unpin_and_release(&vma, 0);
> + dsb->cmd_buf = NULL;
> + atomic_dec(&dsb->refcount);
> + goto err;
> + }
> + dsb->vma = vma;
> +
> +err:
> + intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> + return dsb;
> +}
> +
> +void intel_dsb_put(struct intel_dsb *dsb)
> +{
> + struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +
> + if (!HAS_DSB(i915))
> + return;
> +
> + if (WARN_ON(atomic_read(&dsb->refcount) == 0))
> + return;
> +
> + if (atomic_dec_and_test(&dsb->refcount)) {
> + mutex_lock(&i915->drm.struct_mutex);
> + i915_gem_object_unpin_map(dsb->vma->obj);
> + i915_vma_unpin_and_release(&dsb->vma, 0);
> + mutex_unlock(&i915->drm.struct_mutex);
> + dsb->cmd_buf = NULL;
> + }
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
> b/drivers/gpu/drm/i915/display/intel_dsb.h
> new file mode 100644
> index 000000000000..2c0f60c5f66c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2019 Intel Corporation
> + */
> +
> +#ifndef _INTEL_DSB_H
> +#define _INTEL_DSB_H
> +
> +struct intel_crtc;
> +struct i915_vma;
> +
> +enum dsb_id {
> + INVALID_DSB = -1,
> + DSB1,
> + DSB2,
> + DSB3,
> + MAX_DSB_PER_PIPE
> +};
> +
> +struct intel_dsb {
> + atomic_t refcount;
> + enum dsb_id id;
> + u32 *cmd_buf;
atomic_t and u32 required #include <linux/types.h> here, added while
applying.
Please consider using DRM_I915_WERROR=y config option while developing.
BR,
Jani.
> + struct i915_vma *vma;
> +};
> +
> +struct intel_dsb *
> +intel_dsb_get(struct intel_crtc *crtc);
> +void intel_dsb_put(struct intel_dsb *dsb);
> +
> +#endif
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 84b9b138d7ac..07f1e89a55ca 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -67,6 +67,7 @@
> #include "display/intel_display.h"
> #include "display/intel_display_power.h"
> #include "display/intel_dpll_mgr.h"
> +#include "display/intel_dsb.h"
> #include "display/intel_frontbuffer.h"
> #include "display/intel_gmbus.h"
> #include "display/intel_opregion.h"
--
Jani Nikula, Intel Open Source Graphics Center
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