On Mon, Oct 30, 2017 at 05:29:13PM +0100, Maarten Lankhorst wrote:
> Op 30-10-17 om 17:07 schreef Ville Syrjälä:
> > On Mon, Oct 30, 2017 at 09:59:29AM +0100, Maarten Lankhorst wrote:
> >> Op 27-10-17 om 21:31 schreef Ville Syrjala:
> >>> From: Ville Syrjälä
> >>>
> >>> Currently the DDI encoder->
From: Ville Syrjälä
Explicitly pass the crtc and connector states into the audio
code enable/disable hooks, and plumb them all the way down.
This gets rid of almost all crtc->config and encoder->crtc
uses. The one place where we still use them is
i915_audio_component_sync_audio_rate() since that
From: Ville Syrjälä
encoder->type isn't genreally safe around DDI ports, so let's
replace some uses in the audio code with the crtc state's
output_types instead.
Actually in these cases encoder->type would work since the DP
SST case is only relevant for VLV/CHV and encoder->type==DP
is a thing o
We've been supporting reset-engine in execlist submission mode for a
while, but with GuC, the resubmission path had to be different because we
used to re-enable the engines before GuC... so we've been using full gpu
reset when GuC submission is enabled (which reset the fw).
Thanks to Michal Winiar
From: Michal Wajdeczko
Also revert ("drm/i915/guc: Assert that we switch between
known ggtt->invalidate functions")
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++--
drivers/gpu/drm/i915/i915_params.h | 4 ++--
2 files changed, 4 insertions(+), 8 deletions(
This patch adds per engine reset and recovery (TDR) support when GuC is
used to submit workloads to GPU.
In the case of i915 directly submission to ELSP, driver manages hang
detection, recovery and resubmission. With GuC submission these tasks
are shared between driver and GuC. i915 is still respo
intel_guc_reset sounds more like the microcontroller is the one performing
a reset, while in this case is the opposite. intel_reset_guc not only
makes it clearer, it follows the other intel_reset functions available.
v2: Print error message in English (Tvrtko).
Cc: Tvrtko Ursulin
Signed-off-by:
== Series Details ==
Series: drm/i915: Replace "cc-option -Wno-foo" with "cc-disable-warning foo"
URL : https://patchwork.freedesktop.org/series/32852/
State : success
== Summary ==
Test kms_flip:
Subgroup dpms-vs-vblank-race:
pass -> FAIL (shard-hsw) fdo#10
On Mon, Oct 30, 2017 at 12:00 AM, Fengguang Wu wrote:
> CC intel-gfx.
Thanks, these are all interesting (even if some of them seem to be
from random kernels).
Fengguang, is this a new script that you started running? Because I'm
*hoping* it's not that rc6 suddenly seems so flaky, and it's really
== Series Details ==
Series: tests/kms_fbcon_fbt: Report fbc_status on error (rev3)
URL : https://patchwork.freedesktop.org/series/32256/
State : success
== Summary ==
Test kms_setmode:
Subgroup basic:
pass -> FAIL (shard-hsw) fdo#99912
Test kms_busy:
== Series Details ==
Series: series starting with [1/2] drm/i915: Pass around crtc and connector
states for audio
URL : https://patchwork.freedesktop.org/series/32858/
State : success
== Summary ==
Series 32858v1 series starting with [1/2] drm/i915: Pass around crtc and
connector states for
On 10/16/2017 02:05 AM, Petri Latvala wrote:
On Fri, Oct 13, 2017 at 01:32:58PM -0700, Oscar Mateo wrote:
On 10/12/2017 05:40 AM, Petri Latvala wrote:
On Wed, Oct 11, 2017 at 11:15:40AM -0700, Oscar Mateo wrote:
Apart from context based workarounds, we can now also test for global
MMIO and
On Mon, Oct 30, 2017 at 07:10:11PM +, Linus Torvalds wrote:
> On Mon, Oct 30, 2017 at 12:00 AM, Fengguang Wu wrote:
> > CC intel-gfx.
>
> Thanks, these are all interesting (even if some of them seem to be
> from random kernels).
>
> Fengguang, is this a new script that you started running? B
== Series Details ==
Series: GuC based reset engine
URL : https://patchwork.freedesktop.org/series/32859/
State : success
== Summary ==
Series 32859v1 GuC based reset engine
https://patchwork.freedesktop.org/api/1.0/series/32859/revisions/1/mbox/
Test chamelium:
Subgroup dp-crc-fast:
On 10/18/2017 05:44 AM, Ville Syrjälä wrote:
On Fri, Oct 13, 2017 at 01:54:05PM -0700, Oscar Mateo wrote:
To their rightful place inside intel_workarounds.c
Signed-off-by: Oscar Mateo
Cc: Rodrigo Vivi
Cc: Chris Wilson
Cc: Mika Kuoppala
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_p
On 10/17/2017 06:06 AM, Chris Wilson wrote:
Quoting Oscar Mateo (2017-10-13 21:53:54)
Main difference with v2 is the split into GT and Display workarounds (suggested
by Ville). Because that makes review even more important (which WA goes where?)
I have split the movement of WAs from init_clock
On 10/17/2017 06:03 AM, Chris Wilson wrote:
Quoting Oscar Mateo (2017-10-13 21:54:14)
@@ -840,6 +859,30 @@ static int display_wa_add(struct drm_i915_private
*dev_priv,
static int bdw_display_workarounds_init(struct drm_i915_private *dev_priv)
{
+ enum pipe pipe;
+
+ /* WaP
To their rightful place inside intel_workarounds.c
v2: classify WaSarbUnitClockGatingDisable as GT WA (Ville)
Signed-off-by: Oscar Mateo
Reviewed-by: Chris Wilson (v1)
Cc: Rodrigo Vivi
Cc: Mika Kuoppala
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 32 +---
Display workarounds do not need to be re-applied on a GPU reset
(this is, in Ville's words: "at the very least wasted effort [...]
and could even be actively harmful in case we end up clobbering
something the current display configuration depends on"). Therefore,
they have to be applied in a differ
To their rightful place inside intel_workarounds.c
TODO: Notice that we are leaving WaProgramL3SqcReg1Default (and the
associated WaTempDisableDOPClkGating) behind because it requires extra
careful reviewing. We'll deal with it in a separate patch.
v2: Classify WaDisableCSUnitClockGating and WaDi
This means moving WaTempDisableDOPClkGating as well.
Notice that BXT implements a similar WA to WaProgramL3SqcReg1Default
but, according to the BSpec, it does not require WaTempDisableDOPClkGating.
v2: Use pre-/post- hook calls (Chris)
Signed-off-by: Oscar Mateo
Cc: Rodrigo Vivi
Cc: Chris Wils
To their rightful place inside intel_workarounds.c
v2: Classify WaDisableSDEUnitClockGating as GT WA
Signed-off-by: Oscar Mateo
Reviewed-by: Chris Wilson (v1)
Cc: Rodrigo Vivi
Cc: Mika Kuoppala
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 26 ++
d
To their rightful place inside intel_workarounds.c
Signed-off-by: Oscar Mateo
Cc: Rodrigo Vivi
Cc: Mika Kuoppala
Cc: Ville Syrjälä
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_pm.c | 23 +--
drivers/gpu/drm/i915/intel_workarounds.c | 9 +
2 f
To their rightful place inside intel_workarounds.c
v2:
- Rebase on WA removed
- Rebased to carry the init_early nomenclature over (Chris)
Signed-off-by: Oscar Mateo
Cc: Rodrigo Vivi
Cc: Mika Kuoppala
Cc: Ville Syrjälä
Reviewed-by: Chris Wilson (v1)
---
drivers/gpu/drm/i915/intel_pm.c
Apart from context based workarounds, we can now also test for global
MMIO and whitelisting ones.
Do take into account that this test does not guarantee that all known
WAs for a given platform are applied. It only checks that the WAs the
kernel does know about are correctly applied (e.g. they didn
GEN8_CONFIG0 (0xD00) is a protected by a lock (bit 31) which is set by
the BIOS, so there is no way we can enable the three chicken bits
mandated by the WA (the BIOS should be doing it instead).
v2: Rebased
v3: Standalone patch
Signed-off-by: Oscar Mateo
Cc: Chris Wilson
Cc: Mika Kuoppala
---
This has grown to be a sizable amount of code, so move it to
its own file before we try to refactor anything. For the moment,
we are leaving behind the WA BB code and the WAs that get applied
(incorrectly) in init_clock_gating, but we will deal with it later.
v2: Use intel_ prefix for code that de
Some WAs touch registers that get saved/restored together with the logical
context.
Make this very explicit by renaming a few things in the code.
v2:
- Improved naming
- Rebased
v3: Also rename I915_MAX_CTX_WA_REGS
Signed-off-by: Oscar Mateo
Cc: Chris Wilson
Cc: Mika Kuoppala
---
driver
Does what it says on the tin (plus a few fixes in some old comments).
v2: Include display WAs as a separate category.
Signed-off-by: Oscar Mateo
Cc: Chris Wilson
Cc: Mika Kuoppala
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 4 +--
drivers/gpu/drm/i915/intel_workarounds.
This v4 implements review comments from Chris and Ville and removes the
early bug fixes that have already been upstreamed.
Currently, deciding how/where to apply new workarounds is challenging. Often,
workarounds end up applied incorrectly and get lost under certain circumstances
(e.g. a context s
Let's try to make sure that all WAs are applied correctly and survive
resumes, resets, etc... (with some help from a companion i-g-t patch).
v2:
- Rebased
- Print display WAs as well (Ville)
v3:
- Grab the forcewake once for everyone, so that all reads are from
the same powercontext (Ch
By doing this, we can dump these workarounds in debugfs for validation (which,
at the moment, we are only able to do for the contexts WAs).
v2:
- Wrong macro used for MMIO set bit masked
- Improved naming
- Rebased
v3:
- GT instead of MMIO (Chris, Mika)
- Leave L3_PRIO_CREDITS_MASK for
To their rightful place inside intel_workarounds.c
v2: Classify WaDisableSDEUnitClockGating and WaDisableGamClockGating
as GT WAs
Signed-off-by: Oscar Mateo
Reviewed-by: Chris Wilson (v1)
Cc: Rodrigo Vivi
Cc: Mika Kuoppala
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 21
To their rightful place inside intel_workarounds.c
Signed-off-by: Oscar Mateo
Cc: Rodrigo Vivi
Cc: Mika Kuoppala
Cc: Ville Syrjälä
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_pm.c | 33 ++--
drivers/gpu/drm/i915/intel_workarounds.c | 17 +
There are different kind of workarounds (those that modify registers that
live in the context image, those that modify global registers, those that
whitelist registers, etc...) and they have different requirements in terms
of where they are applied and how. Also, by splitting them apart, it should
To their rightful place inside intel_workarounds.c
Signed-off-by: Oscar Mateo
Cc: Rodrigo Vivi
Cc: Mika Kuoppala
Cc: Ville Syrjälä
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_pm.c | 15 +--
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
2 files change
Since we are trying to put all WA stuff together, do not forget about the BB
WAs.
v2: s/intel_bb_workarounds_init/intel_engine_init_bb_workarounds (Chris)
Signed-off-by: Oscar Mateo
Cc: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 253 +--
Same as we have been doing for other types, this allow us to dump
the whole list of workarounds to debugs, for validation purposes.
v2:
- Improved naming
- Rebased
Signed-off-by: Oscar Mateo
Cc: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
To their rightful place inside intel_workarounds.c
TODO: Notice that we are leaving WaProgramL3SqcReg1Default (and the
associated WaTempDisableDOPClkGating) behind because it requires
extra careful reviewing. We'll deal with it in a separate patch.
TODO2: Decide what to do with lpt_init_clock_gat
On Mon, Oct 30, 2017 at 12:10:11PM -0700, Linus Torvalds wrote:
On Mon, Oct 30, 2017 at 12:00 AM, Fengguang Wu wrote:
CC intel-gfx.
Thanks, these are all interesting (even if some of them seem to be
from random kernels).
Fengguang, is this a new script that you started running? Because I'm
*
== Series Details ==
Series: drm/i915/cnl: Remove unnecessary check in cnl_setup_private_ppat
URL : https://patchwork.freedesktop.org/series/32792/
State : failure
== Summary ==
Series 32792v1 drm/i915/cnl: Remove unnecessary check in cnl_setup_private_ppat
https://patchwork.freedesktop.org/ap
== Series Details ==
Series: Refactor HW workaround code (rev4)
URL : https://patchwork.freedesktop.org/series/31611/
State : warning
== Summary ==
Series 31611v4 Refactor HW workaround code
https://patchwork.freedesktop.org/api/1.0/series/31611/revisions/4/mbox/
Test gem_exec_suspend:
Quoting Michel Thierry (2017-10-30 18:56:15)
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index af745749509c..02fb35744f66 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1984,10 +1984,15 @@ int i915_reset_engine(str
== Series Details ==
Series: igt/gem_workarounds: Test all types of workarounds (rev3)
URL : https://patchwork.freedesktop.org/series/31612/
State : failure
== Summary ==
IGT patchset tested on top of latest successful build
7aac0e88606ce453b111ce80419dc58519db05ad assembler: Fix bashism in ru
Quoting Michel Thierry (2017-10-30 18:56:14)
> intel_guc_reset sounds more like the microcontroller is the one performing
> a reset, while in this case is the opposite. intel_reset_guc not only
> makes it clearer, it follows the other intel_reset functions available.
>
> v2: Print error message in
Expanding on Jani's work to sign tags, this patch adds signing for git
commit/am.
Signed-off-by: Sean Paul
---
This has been lightly tested with dim apply-branch/dim push-branch.
Sean
dim | 78 +
1 file changed, 51 insertions
On 30/10/17 13:58, Chris Wilson wrote:
Quoting Michel Thierry (2017-10-30 18:56:15)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index af745749509c..02fb35744f66 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1984,10 +1984
Quoting Michel Thierry (2017-10-30 18:56:15)
> This patch adds per engine reset and recovery (TDR) support when GuC is
> used to submit workloads to GPU.
>
> In the case of i915 directly submission to ELSP, driver manages hang
> detection, recovery and resubmission. With GuC submission these tasks
Quoting Patchwork (2017-10-30 20:05:05)
> == Series Details ==
>
> Series: GuC based reset engine
> URL : https://patchwork.freedesktop.org/series/32859/
> State : success
>
> == Summary ==
>
> Series 32859v1 GuC based reset engine
> https://patchwork.freedesktop.org/api/1.0/series/32859/revis
Quoting Ville Syrjälä (2017-10-30 17:41:51)
> On Mon, Oct 30, 2017 at 05:29:27PM +, Chris Wilson wrote:
> > To quote kbuild/makefiles.txt:
> >
> > cc-disable-warning checks if gcc supports a given warning and returns
> > the commandline switch to disable it. This special function is ne
Updating the mask is needed to clear all the three power state bits before
setting the required power state. Also add a comment documenting that
D3 Aux-On state has been available DPCD v1.2 onwards. Thanks to Ville for
pointing this out.
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: Dhinakara
Apart from context based workarounds, we can now also test for global
MMIO and whitelisting ones.
Do take into account that this test does not guarantee that all known
WAs for a given platform are applied. It only checks that the WAs the
kernel does know about are correctly applied (e.g. they didn
== Series Details ==
Series: drm/i915: Replace "cc-option -Wno-foo" with "cc-disable-warning foo"
URL : https://patchwork.freedesktop.org/series/32852/
State : success
== Summary ==
Series 32852v1 drm/i915: Replace "cc-option -Wno-foo" with "cc-disable-warning
foo"
https://patchwork.freedeskt
== Series Details ==
Series: series starting with [1/2] drm/i915: Pass around crtc and connector
states for audio
URL : https://patchwork.freedesktop.org/series/32858/
State : warning
== Summary ==
Test kms_flip:
Subgroup plain-flip-fb-recreate:
pass -> FAIL
== Series Details ==
Series: GuC based reset engine
URL : https://patchwork.freedesktop.org/series/32859/
State : warning
== Summary ==
Test drv_module_reload:
Subgroup basic-no-display:
pass -> DMESG-WARN (shard-hsw) fdo#102707
Test gem_softpin:
Subgroup
== Series Details ==
Series: drm/dp: Update SET_POWER_MASK to include the D3 Aux-On state too.
URL : https://patchwork.freedesktop.org/series/32867/
State : success
== Summary ==
Series 32867v1 drm/dp: Update SET_POWER_MASK to include the D3 Aux-On state too.
https://patchwork.freedesktop.org/
== Series Details ==
Series: drm/i915: Replace "cc-option -Wno-foo" with "cc-disable-warning foo"
URL : https://patchwork.freedesktop.org/series/32852/
State : success
== Summary ==
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
Test km
== Series Details ==
Series: igt/gem_workarounds: Test all types of workarounds (rev4)
URL : https://patchwork.freedesktop.org/series/31612/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
7aac0e88606ce453b111ce80419dc58519db05ad assembler: Fix bashism in ru
On Sun, 2017-10-29 at 03:04 +, Kumar, Abhay wrote:
> + Subhransu
>
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Kumar, Abhay
> Sent: Thursday, October 26, 2017 12:10 PM
> To: Jani Nikula ; Dhinakaran Pandiyan
> ; subransu.s.pr
Ville Syrjälä writes:
> On Tue, Oct 03, 2017 at 09:35:33AM -0700, Ben Widawsky wrote:
>> On 17-09-27 15:34:17, Gabriel Krisman Bertazi wrote:
>> >Signed-off-by: Gabriel Krisman Bertazi
>> >---
>> > tests/kms_ccs.c | 37 +++--
>> > 1 file changed, 27 insertions(+),
== Series Details ==
Series: drm/dp: Update SET_POWER_MASK to include the D3 Aux-On state too.
URL : https://patchwork.freedesktop.org/series/32867/
State : warning
== Summary ==
Test perf:
Subgroup oa-exponents:
fail -> PASS (shard-hsw) fdo#102254
Test kms_
== Series Details ==
Series: igt/gem_workarounds: Test all types of workarounds (rev4)
URL : https://patchwork.freedesktop.org/series/31612/
State : success
== Summary ==
Test drv_module_reload:
Subgroup basic-reload-inject:
pass -> DMESG-WARN (shard-hsw) fdo#1027
Hi:
Thanks for your quickly response.
I have updated the comments in the following text
Thanks!
Best Wishes!
Xinda
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Monday, October 30, 2017 11:14 PM
> To: Zhao, Xinda
> Cc: intel-gfx@lists.freedes
On 30/10/17 14:09, Chris Wilson wrote:
Quoting Michel Thierry (2017-10-30 18:56:15)
This patch adds per engine reset and recovery (TDR) support when GuC is
used to submit workloads to GPU.
In the case of i915 directly submission to ELSP, driver manages hang
detection, recovery and resubmission.
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