To their rightful place inside intel_workarounds.c
v2: classify WaSarbUnitClockGatingDisable as GT WA (Ville)
Signed-off-by: Oscar Mateo <oscar.ma...@intel.com>
Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk> (v1)
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 32 +-------------------------------
drivers/gpu/drm/i915/intel_workarounds.c | 26 +++++++++++++++++++++++++-
2 files changed, 26 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0d0e84b..ff3ac6c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8519,36 +8519,6 @@ static void cnp_init_clock_gating(struct
drm_i915_private *dev_priv)
CNP_PWM_CGE_GATING_DISABLE);
}
-static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
-{
- u32 val;
- cnp_init_clock_gating(dev_priv);
-
- /* This is not an Wa. Enable for better image quality */
- I915_WRITE(_3D_CHICKEN3,
- _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
-
- /* WaEnableChickenDCPR:cnl */
- I915_WRITE(GEN8_CHICKEN_DCPR_1,
- I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
-
- /* WaFbcWakeMemOn:cnl */
- I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
- DISP_FBC_MEMORY_WAKE);
-
- /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
- if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
- I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
- I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
- SARBUNIT_CLKGATE_DIS);
-
- /* Display WA #1133: WaFbcSkipSegments:cnl */
- val = I915_READ(ILK_DPFC_CHICKEN);
- val &= ~GLK_SKIP_SEG_COUNT_MASK;
- val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
- I915_WRITE(ILK_DPFC_CHICKEN, val);
-}
-
static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
{
cnp_init_clock_gating(dev_priv);
@@ -9040,7 +9010,7 @@ static void nop_init_clock_gating(struct drm_i915_private
*dev_priv)
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_CANNONLAKE(dev_priv))
- dev_priv->display.init_clock_gating = cnl_init_clock_gating;
+ dev_priv->display.init_clock_gating = nop_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv))
dev_priv->display.init_clock_gating = cfl_init_clock_gating;
else if (IS_SKYLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 3e643b6..82defb1 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -724,6 +724,15 @@ static int cfl_gt_workarounds_init_early(struct
drm_i915_private *dev_priv)
static int cnl_gt_workarounds_init_early(struct drm_i915_private *dev_priv)
{
+ /* This is not an Wa. Enable for better image quality */
+ GT_WA_SET_BIT_MASKED(_3D_CHICKEN3,
+ _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
+
+ /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
+ if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
+ GT_WA_SET_BIT(SLICE_UNIT_LEVEL_CLKGATE,
+ SARBUNIT_CLKGATE_DIS);
+
/* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
GT_WA_SET_BIT(GAMT_CHKN_BIT_REG,
@@ -856,6 +865,22 @@ static int cfl_display_workarounds_init_early(struct
drm_i915_private *dev_priv)
static int cnl_display_workarounds_init_early(struct drm_i915_private
*dev_priv)
{
+ if (HAS_PCH_CNP(dev_priv)) {
+ /* Wa #1181 */
+ DISPLAY_WA_SET_BIT(SOUTH_DSPCLK_GATE_D,
+ CNP_PWM_CGE_GATING_DISABLE);
+ }
+
+ /* WaEnableChickenDCPR:cnl */
+ DISPLAY_WA_SET_BIT(GEN8_CHICKEN_DCPR_1, MASK_WAKEMEM);
+
+ /* WaFbcWakeMemOn:cnl */
+ DISPLAY_WA_SET_BIT(DISP_ARB_CTL, DISP_FBC_MEMORY_WAKE);
+
+ /* Display WA #1133: WaFbcSkipSegments:cnl */
+ DISPLAY_WA_SET_FIELD(ILK_DPFC_CHICKEN, GLK_SKIP_SEG_COUNT_MASK,
+ GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1));
+
return 0;
}
@@ -863,7 +888,6 @@ static int display_workarounds_init_early(struct
drm_i915_private *dev_priv)
{
int err;
- DISPLAY_WA_SET_BIT(_MMIO(0), 0); /* shut up gcc temporarily */
dev_priv->workarounds.display_wa_count = 0;
if (INTEL_GEN(dev_priv) < 8)
--
1.9.1
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