To their rightful place inside intel_workarounds.c
TODO: Notice that we are leaving WaProgramL3SqcReg1Default (and the
associated WaTempDisableDOPClkGating) behind because it requires
extra careful reviewing. We'll deal with it in a separate patch.
TODO2: Decide what to do with lpt_init_clock_gating (shouldn't
WADPOClockGatingDisable be marked as "bdw"? shouldn't it be
protected by HAS_PCH_LPT_LP? do we want to move the whole thing
to the workarounds file or not?).
v2: Classify WaDisableSDEUnitClockGating as GT WA
Signed-off-by: Oscar Mateo <oscar.ma...@intel.com>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 47 --------------------------------
drivers/gpu/drm/i915/intel_workarounds.c | 43 +++++++++++++++++++++++++++++
2 files changed, 43 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b15892b..f1e3a04 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8419,59 +8419,12 @@ static void gen8_set_l3sqc_credits(struct
drm_i915_private *dev_priv,
static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
{
- /* The GTT cache must be disabled if the system is using 2M pages. */
- bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv,
- I915_GTT_PAGE_SIZE_2M);
- enum pipe pipe;
-
ilk_init_lp_watermarks(dev_priv);
- /* WaSwitchSolVfFArbitrationPriority:bdw */
- I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
-
- /* WaPsrDPAMaskVBlankInSRD:bdw */
- I915_WRITE(CHICKEN_PAR1_1,
- I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
-
- /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
- for_each_pipe(dev_priv, pipe) {
- I915_WRITE(CHICKEN_PIPESL_1(pipe),
- I915_READ(CHICKEN_PIPESL_1(pipe)) |
- BDW_DPRS_MASK_VBLANK_SRD);
- }
-
- /* WaVSRefCountFullforceMissDisable:bdw */
- /* WaDSRefCountFullforceMissDisable:bdw */
- I915_WRITE(GEN7_FF_THREAD_MODE,
- I915_READ(GEN7_FF_THREAD_MODE) &
- ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
-
- I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
- _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
-
- /* WaDisableSDEUnitClockGating:bdw */
- I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
- GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
-
/* WaProgramL3SqcReg1Default:bdw */
gen8_set_l3sqc_credits(dev_priv, 30, 2);
- /* WaGttCachingOffByDefault:bdw */
- I915_WRITE(HSW_GTT_CACHE_EN, can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);
-
- /* WaKVMNotificationOnConfigChange:bdw */
- I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
- | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
-
lpt_init_clock_gating(dev_priv);
-
- /* WaDisableDopClockGating:bdw
- *
- * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
- * clock gating.
- */
- I915_WRITE(GEN6_UCGCTL1,
- I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
}
static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index c0f4513..0a88c92 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -563,6 +563,28 @@ static int gt_wa_add(struct drm_i915_private *dev_priv,
static int bdw_gt_workarounds_init_early(struct drm_i915_private *dev_priv)
{
+ /* The GTT cache must be disabled if the system is using 2M pages. */
+ bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv,
I915_GTT_PAGE_SIZE_2M);
+
+ /* WaSwitchSolVfFArbitrationPriority:bdw */
+ GT_WA_SET_BIT(GAM_ECOCHK, HSW_ECOCHK_ARB_PRIO_SOL);
+
+ /* WaVSRefCountFullforceMissDisable:bdw */
+ /* WaDSRefCountFullforceMissDisable:bdw */
+ GT_WA_CLR_BIT(GEN7_FF_THREAD_MODE, GEN8_FF_DS_REF_CNT_FFME |
+ GEN7_FF_VS_REF_CNT_FFME);
+
+ /* WaDisableSemaphoreAndSyncFlipWait:bdw */
+ GT_WA_SET_BIT_MASKED(GEN6_RC_SLEEP_PSMI_CONTROL,
+ GEN8_RC_SEMA_IDLE_MSG_DISABLE);
+
+ /* WaDisableSDEUnitClockGating:bdw */
+ GT_WA_SET_BIT(GEN8_UCGCTL6, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
+ /* WaGttCachingOffByDefault:bdw */
+ GT_WA_SET_FIELD(HSW_GTT_CACHE_EN, 0xFFFFFFFF,
+ can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);
+
return 0;
}
@@ -862,6 +884,27 @@ static int display_wa_add(struct drm_i915_private
*dev_priv,
static int bdw_display_workarounds_init_early(struct drm_i915_private
*dev_priv)
{
+ enum pipe pipe;
+
+ /* WaPsrDPAMaskVBlankInSRD:bdw */
+ DISPLAY_WA_SET_BIT(CHICKEN_PAR1_1, DPA_MASK_VBLANK_SRD);
+
+ /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
+ for_each_pipe(dev_priv, pipe) {
+ DISPLAY_WA_SET_BIT(CHICKEN_PIPESL_1(pipe),
+ BDW_DPRS_MASK_VBLANK_SRD);
+ }
+
+ /* WaKVMNotificationOnConfigChange:bdw */
+ DISPLAY_WA_SET_BIT(CHICKEN_PAR2_1,
KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
+
+ /* WaDisableDopClockGating:bdw
+ *
+ * Also see the CHICKEN2 write in bdw_gt_workarounds_init() to disable
+ * DOP clock gating.
+ */
+ DISPLAY_WA_SET_BIT(GEN6_UCGCTL1, GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
+
return 0;
}
--
1.9.1
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