From: Ville Syrjälä
Implement the POST_LT_ADJ_REQ sequence, which should be used
to further fine tune the link if TPS4 is not supported.
The POST_LT_ADJ_REQ sequence will be performed after
the normal link training has succeeded.
Only the final hop between the last LTTPR and DPRX will
perform th
From: Ville Syrjälä
Disable TPS4 in favor of POST_LT_ADJ_REQ for testing purposes.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/
From: Ville Syrjälä
Add the bit definitions needed for POST_LT_ADJ sequence.
v2: DP_POST_LT_ADJ_REQ_IN_PROGRESS is bit 1 not 5 (Jani)
Tested-by: Imre Deak
Reviewed-by: Imre Deak
Signed-off-by: Ville Syrjälä
---
include/drm/display/drm_dp.h | 3 +++
1 file changed, 3 insertions(+)
diff --gi
From: Ville Syrjälä
Add small helpers (drm_dp_post_lt_adj_req_supported() and
drm_dp_post_lt_adj_req_in_progress()) to help with implementing
the POST_LT_ADJ_REQ sequence.
Tested-by: Imre Deak
Reviewed-by: Imre Deak
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/display/drm_dp_helper.c | 8
From: Ville Syrjälä
Implement the POST_LT_ADJ_REQ sequence, which is supposed
to be used to further tune the link vswing/pre-emphasis
when TPS4 is not supported.
Unfortunately I don't have any displays/dongles that support
this so I wasn't able to test anything. Imre has tested this
with a DP te
From: Ville Syrjälä
GLK doesn't use the DSI C clock at all, no need to program
the divider for it. Bspec even says: "Do not program this field".
However looks like some firmware versions program this and
some do not. In order to avoid bogus fastset mismatches
we should also filter it out during
From: Ville Syrjälä
Currently we pre-compute the plane surface/base address
partially (only for cursor_needs_physical cases) in
intel_plane_pin_fb() and finish the calculation in the
plane->update_arm(). Let's just precompute the whole thing
instead.
One benefit is that we get rid of all the vma
From: Ville Syrjälä
dpt_total_entries() is not used anywhere. Remove it.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpt.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers/gpu/drm/i915/dis
From: Ville Syrjälä
The *_plane_ctl() functions only consider the state of the
plane (the state of the crtc is handled by the corresponding
*_plane_ctl_crtc()), and thus they don't need the crtc_state
at all. Don't pass it in.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/
From: Ville Syrjälä
Replace the open coded vma mm node stuff in intel_dpt_offset()
with i915_vma_offset(). This will also include the VT-d guard
in the result. Granted that should always be 0 for DPT, but
it seems prudent to include that in our DPT vma offset check
anyway.
Reviewed-by: Jani Niku
From: Ville Syrjälä
Now that we handle all the other vma offset stuff in
intel_plane_pin_fb() it seems more proper to do the
dpt_vma offset check there as well.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fb_pin.c| 7 +++
drivers/gp
From: Ville Syrjälä
We don't really need the extra intel_plane_ggtt_offset() wrapper
anymore. Get rid of it.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fb_pin.c| 3 ++-
drivers/gpu/drm/i915/display/intel_plane.c | 6 --
dri
From: Ville Syrjälä
Currently we pre-compute the plane surface/base address
partially (only for cursor_needs_physical cases) in
intel_plane_pin_fb() and finish the calculation in the
plane->update_arm(). Let's just precompute the whole thing
instead.
One benefit is that we get rid of all the vma
From: Ville Syrjälä
Include a precomputed plane SURF address in the plane state,
so that all the vma stuff is contained in the *_fb_pin.c code.
Additionally we can also now easily include the SURF address in
some of the plane tracepoints to aid in eg. analyzing faults.
v2: Drop the plane_state->
From: Ville Syrjälä
Everyone implements the .set_idle_link_train() hook now.
Just make it mandatory.
Tested-by: Imre Deak
Reviewed-by: Imre Deak
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(
From: Ville Syrjälä
We are supposed to switch off the training pattern in DPCD before
we start transmitting the idle pattern. For LTTPRs we do that
correctly, but for the sink DPRX we only do this correctly
for some platforms.
On pre-HSW (where we don't implement the .set_idle_link_train()
hook)
From: Ville Syrjälä
Move intel_dp_training_pattern() upwards to avoid the forward
declaration for the POST_LT_ADJ_REQ stuff.
Tested-by: Imre Deak
Reviewed-by: Imre Deak
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_dp_link_training.c | 114 +-
1 file changed, 57
From: Ville Syrjälä
All platforms are capable of explicitly transmitting the idle
pattern. Implement it for everyone (so far it as implemented
only for HSW+).
The immediate benefit is that we gain the possibility of
implementing the POST_LT_ADJ_REQ sequence for all platforms.
Another potential
From: Ville Syrjälä
A few DP related things:
- Fix 2.7 Gbps link training on g4x
- Adjust the idle pattern handling (most of this was part
of my POST_LT_ADJ_REQ series earlier, but I reordered
things to leave the actual POST_LT_ADJ_REQ support for
later)
- shuffle the link training code a b
From: Ville Syrjälä
In order to implement the POST_LT_ADJ_REQ sequence we need to
know whether the sink actually requested a changed to the
vswing/pre-emph values.
Tested-by: Imre Deak
Reviewed-by: Imre Deak
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_dp_link_training.c | 18
From: Ville Syrjälä
For some reason we are switching over to the idle pattern before
disabling the DP port on pre-hsw. AFAICS this has never been part
of the documented sequence (and on hsw+ the spec explicitly says
not to do this). Get rid of it.
The code goes all the way back to commit 5eb08b6
From: Ville Syrjälä
On g4x we currently use the 96MHz non-SSC refclk, which can't actually
generate an exact 2.7 Gbps link rate. In practice we end up with 2.688
Gbps which seems to be close enough to actually work, but link training
is currently failing due to miscalculating the DP_LINK_BW value
From: Ville Syrjälä
intel_opregion_notify_adapter() is no longer needed outside
intel_opregion.c. Make it static.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_opregion.c | 4 ++--
drivers/gpu/drm/i915/display/intel_opregion.h | 8
2 files changed, 2 insertions(+
From: Ville Syrjälä
Extract the opregion runtime PM stuff to new functions. We'll
need to add a bit more to the suspend side, and we don't want
to clutter the top level runtime PM code with such details.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_opregion.c | 41 ++
From: Ville Syrjälä
For good measure make sure asle_work has finished whatever it
was doing before we runtime suspend the device.
This probably isn't really necessary as long asle_work only
pokes at the mailbox as it should remain accessible even if
the device has been suspended. But seems bette
From: Ville Syrjälä
The GU_MISC/GSE interrupt may be raised even when we're not
holding a runtime PM wakeref. Disable the asserts while
processing GU_MISC irqs. Previously this was covered by
the use of raw_reg_{read,write}() which lack the assert.
Not having an assert is fine since we synchroni
From: Ville Syrjälä
While read_poll_timeout() & co. were originally introduced just
for simple I/O usage scenarios they have since been generalized to
be useful in more cases.
However the interface is very cumbersome to use in the general case.
Attempt to make it more flexible by combining the '
From: Ville Syrjälä
Make sure poll_timeout_us() works by using it in i915
instead of the custom __wait_for().
Remaining difference between two:
| poll_timeout_us() | __wait_for()
---
backoff| fixed interval| exponential
u
From: Ville Syrjälä
Currently poll_timeout_us() evaluates 'op' and 'cond' twice
within the loop, once at the start, and a second time after
the timeout check. While it's probably not a big deal to do
it twice almost back to back, it does make the macro a bit messy.
Simplify the implementation to
From: Ville Syrjälä
While read_poll_timeout() & co. were originally introduced just
for simple I/O usage scenarios they have since been generalized to
be useful in more cases.
However the interface is very cumbersome to use in the general case.
Attempt to make it more flexible by combining the '
From: Ville Syrjälä
Currently poll_timeout_us() evaluates 'cond' twice at the end
of the success case. This not desirable in case 'cond' itself
is expensive.
Avoid the double evaluation by tracking the return value in
a variable. Need to use a triple undescore '___ret' name to
avoid a conflict w
From: Ville Syrjälä
Now that everyone passes along the format info to
drm_helper_mode_fill_fb_struct() we can make this behaviour
mandatory and drop the extra lookup.
Reviewed-by: Thomas Zimmermann
Reviewed-by: Laurent Pinchart
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_modeset_hel
From: Ville Syrjälä
I noticed a bunch of redundant (and rather expensive) drm_format_info
lookups in some traces recently. This series is an attempt to eliminate
them.
v2: Rebase
Ville Syrjälä (19):
drm: Pass pixel_format+modifier to .get_format_info()
drm: Pass pixel_format+modifier direct
From: Ville Syrjälä
Plumb the format info from .fb_create() all the way to
drm_helper_mode_fill_fb_struct() to avoid the redundant
lookup.
For the fbdev case a manual drm_get_format_info() lookup
is needed.
Reviewed-by: Thomas Zimmermann
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/
From: Ville Syrjälä
Plumb the format info from .fb_create() all the way to
drm_helper_mode_fill_fb_struct() to avoid the redundant
lookup.
Cc: David Airlie
Cc: Gerd Hoffmann
Cc: Dmitry Osipenko
Cc: Gurchetan Singh
Cc: Chia-I Wu
Cc: virtualizat...@lists.linux.dev
Reviewed-by: Thomas Zimmerma
From: Ville Syrjälä
Plumb the format info from .fb_create() all the way to
drm_helper_mode_fill_fb_struct() to avoid the redundant
lookup.
Cc: Liviu Dudau
Reviewed-by: Thomas Zimmermann
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c | 2 +-
1 file ch
From: Ville Syrjälä
Plumb the format info from .fb_create() all the way to
drm_helper_mode_fill_fb_struct() to avoid the redundant
lookup.
For the fbdev case a manual drm_get_format_info() lookup
is needed.
Cc: Thierry Reding
Cc: Mikko Perttunen
Cc: linux-te...@vger.kernel.org
Reviewed-by: Th
From: Ville Syrjälä
Plumb the format info from .fb_create() all the way to
drm_helper_mode_fill_fb_struct() to avoid the redundant
lookup.
Cc: Zack Rusin
Cc: Broadcom internal kernel review list
Reviewed-by: Thomas Zimmermann
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/vmwgfx/vmwgfx_km
From: Ville Syrjälä
Plumb the format info from .fb_create() all the way to
drm_helper_mode_fill_fb_struct() to avoid the redundant
lookups.
For the fbdev case a manual drm_get_format_info() lookup
is needed.
Cc: Rob Clark
Cc: Abhinav Kumar
Cc: Dmitry Baryshkov
Cc: Sean Paul
Cc: Marijn Suijt
From: Ville Syrjälä
Plumb the format info from .fb_create() all the way to
drm_helper_mode_fill_fb_struct() to avoid the redundant
lookup.
For the fbdev case a manual drm_get_format_info() lookup
is needed.
Cc: Patrik Jakobsson
Reviewed-by: Thomas Zimmermann
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Plumb the format info from .fb_create() all the way to
drm_helper_mode_fill_fb_struct() to avoid the redundant
lookup.
For the fbdev case a manual drm_get_format_info() lookup
is needed.
Cc: Inki Dae
Cc: Seung-Woo Kim
Cc: Kyungmin Park
Reviewed-by: Thomas Zimmermann
Sign
From: Ville Syrjälä
Plumb the format info from .fb_create() all the way to
drm_helper_mode_fill_fb_struct() to avoid the redundant
lookup.
For the fbdev case a manual drm_get_format_info() lookup
is needed.
Cc: Russell King
Reviewed-by: Thomas Zimmermann
Signed-off-by: Ville Syrjälä
---
dri
From: Ville Syrjälä
Pass along the format info from .fb_create() to aliminate the
redundant drm_get_format_info() calls from the afbc code.
Cc: Sandy Huang
Cc: "Heiko Stübner"
Cc: Andy Yan
Reviewed-by: Thomas Zimmermann
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_gem_framebuffer_h
From: Ville Syrjälä
Plumb the format info from .fb_create() all the way to
malidp_verify_afbc_framebuffer_size() to avoid the
redundant lookup.
Cc: Liviu Dudau
Reviewed-by: Thomas Zimmermann
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/arm/malidp_drv.c | 10 --
1 file changed, 4
From: Ville Syrjälä
Plumb the format info from .fb_create() all the way to
drm_helper_mode_fill_fb_struct() to avoid the redundant
lookup.
Cc: Alex Deucher
Cc: amd-...@lists.freedesktop.org
Reviewed-by: Thomas Zimmermann
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/amd/amdgpu/amdgpu_disp
From: Ville Syrjälä
Pass along the format info from .fb_create() to aliminate the
redundant drm_get_format_info() calls from the gem fb code.
v2: Fix kernel docs (Laurent)
Cc: Dave Airlie
Cc: Gerd Hoffmann
Cc: Sandy Huang
Cc: "Heiko Stübner"
Cc: Andy Yan
Cc: Oleksandr Andrushchenko
Cc: vi
From: Ville Syrjälä
Soon all drivers should have the format info already available in the
places where they call drm_helper_mode_fill_fb_struct(). Allow it to
be passed along into drm_helper_mode_fill_fb_struct() instead of doing
yet another redundant lookup.
Start by always passing in NULL and
From: Ville Syrjälä
Pass along the format information from the top to .fb_create()
so that we can avoid redundant (and somewhat expensive) lookups
in the drivers.
Done with cocci (with some manual fixups):
@@
identifier func =~ ".*create.*";
identifier dev, file, mode_cmd;
@@
struct drm_framebuf
From: Ville Syrjälä
Look up the format info already in drm_internal_framebuffer_create()
so that we can later pass it along to .fb_create(). Currently various
drivers are doing additional lookups in their .fb_create()
implementations, and these lookups are rather expensive now (given
how many dif
From: Ville Syrjälä
Decouple .get_format_info() from struct drm_mode_fb_cmd2 and just
pass the pixel format+modifier combo in by hand.
We may want to use .get_format_info() outside of the normal
addfb paths where we won't have a struct drm_mode_fb_cmd2, and
creating a temporary one just for this
From: Ville Syrjälä
Decouple drm_get_format_info() from struct drm_mode_fb_cmd2 and just
pass the pixel format+modifier combo in by hand.
We may want to use drm_get_format_info() outside of the normal
addfb paths where we won't have a struct drm_mode_fb_cmd2, and
creating a temporary one just fo
From: Ville Syrjälä
The current PKG_C_LATENCY stuff looks busted in several ways:
- doesn't account for multiple pipes from different commits
correctly
- WM_LINETIME is in units of 0.125usec, PKG_C_LATENCY wants
units on 1 usec
- weird VRR state stuff being checked
- use of pointless RMW
Fix
From: Ville Syrjälä
AFAIK PKG_C_LATENCY.added_wake_time only matters for flip queue.
As long as we're not using that there's no point in adding any
extra wake time.
Reviewed-by: Uma Shankar
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_watermark.c | 9 -
1 file cha
From: Ville Syrjälä
Add a function for dumping the entries of a specific flip queue.
Reviewed-by: Uma Shankar
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_flipq.c | 46 ++
drivers/gpu/drm/i915/display/intel_flipq.h | 2 +
2 files changed, 48 inserti
From: Ville Syrjälä
Implement the driver side of Wa_18034343758, which is supposed to
prevent the DSB and DMC from accessing registers in parallel, and
thus potentially corrupting the registers due to a hardware issue
(which should be fixed in PTL-B0).
The w/a sequence goes as follows:
DMC start
From: Ville Syrjälä
Flip on the enable_flipq modparam to see if CI blows up.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display_params.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_params.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/d
From: Ville Syrjälä
Add the register definitions for a bunch of flip queue related
PIPEDMC registers.
v2: The layout of flip queue entries changed on PTL
Bump the DMC_FQ_W2_PTS_CFG_SEL bitfields sizes (Uma)
Reduce the scanlines to 21 bits for now (Uma)
v3: Also define some undocumented D
From: Ville Syrjälä
Initial stab at implementing the PIPEDMC based flip queue.
Briefly smoke tested on LNL and PTL-A0, not much more.
Still has quite a few warts..
v2: cleaned up a few of the warts at least
should work on PTL now
v3: Rebase due to DSB GOSUB stuff getting merged
Try to f
From: Ville Syrjälä
Support commits via the flip queue (as opposed to DSB or MMIO).
As it's somewhat unknown if we can actually use it is currently
gated behind the new use_flipq modparam, which defaults to disabled.
The implementation has a bunch of limitations that would need
real though to s
From: Ville Syrjälä
The normal flip queue completion interrupt doesn't work on LNL-A0,
and instead the firmware implements a workaround via the delayed
vblank event handler. Implement said workaround on the driver side
by enabling the appropriate event and handling the result interrupt
vector val
From: Ville Syrjälä
Provide the lower level code for PIPEDMC based flip queue.
We'll use the so called semi-full flip queue mode where the
PIPEDMC will start the provided DSB on a scanline a little
ahead of the vblank. We need to program the triggering scanline
early enough so that the DSB has e
From: Ville Syrjälä
On TGL/derivatives the pipe DMC state is lost when PG1 is disabled,
and the main DMC does not restore any of it. This means the state will
also be lost during PSR+DC5/6. It seems safest to not even enable the
pipe DMC in that case (the main DMC does restore the pipe DMC enable
From: Ville Syrjälä
I'll need to examine the crtc state during intel_dmc_enable_pipe().
To that end pass the whole crtc into intel_dmc_{enable,disable}_pipe().
Reviewed-by: Uma Shankar
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 16
dri
From: Ville Syrjälä
Currently we have some asserts to make sure the main DMC has been
loaded. Add similar asserts for the pipe DMCs. And we might as well
just check all the mmio registers the firmware has asked us to
initialize. That also covers the hardcoded SSP/HTP registers we were
checking fo
From: Ville Syrjälä
Shuffle the DMC_EVT_CTL related stuff around once more. We'll need
this stuff during intel_dmc_enable_pipe(), and this lets us avoid
forward declarations.
Reviewed-by: Uma Shankar
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dmc.c | 144 +++--
From: Ville Syrjälä
The MTL+ pipe DMC clock gating bits can be parametrized.
Make it so.
Reviewed-by: Uma Shankar
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dmc.c | 3 ++-
drivers/gpu/drm/i915/i915_reg.h | 3 +--
2 files changed, 3 insertions(+), 3 deletions(
From: Ville Syrjälä
On ADL/MTL pipe DMC MMIO state evidently lives in PG0. The main DMC
saves/restores it for pipes A/B, but for pipes C/D we have to do it
in the driver.
On PTL the situation is mostly the same, except the main DMC firmware
doesn't seem to have the PG0 save/restore code anymore,
From: Ville Syrjälä
Supposedly nothing post-MTL (even BMG) needs the pipe DMC clock
gating w/a (Wa_16015201720), so don't apply it.
TODO: check if the ADL/DG2 "clock gating needed during DMC loading" part
is actuall needed, not seeing anything in the docs about it...
Reviewed-by: Uma Shan
From: Ville Syrjälä
We'll be needing to reload the program for individual DMCs.
To make that possible pull the code to load the program for
a single DMC into a new function.
This does change the order of things during init/resume
a bit; previously we loaded the program RAM for all DMCs first,
an
From: Ville Syrjälä
Attempt to deal with the fact that pipe DMCs can sometimes
lose their state.
v2: Handle more platforms
Ville Syrjälä (9):
drm/i915/dmc: Limit pipe DMC clock gating w/a to just ADL/DG2/MTL
drm/i915/dmc: Parametrize MTL_PIPEDMC_GATING_DIS
drm/i915/dmc: Shuffle code aroun
From: Ville Syrjälä
On TGL/derivatives the entire pipe DMC state (program + MMIO) is
lost when PG1 is disabled, and the main DMC does not restore
any of it. Reload the state when enabling a pipe.
The other option would be to not load the pipe DMC at all since
it's only needed for "fast LACE" (wh
From: Ville Syrjälä
Pull the magic 20 usec DSB execution deadline into
intel_dsb_arm_exec_time_us(), and also add its counterpart
for the non-arming register write section. For the non-arming
part we'll just throw in a random 80 usec for now so the total
is 100usec. The total exec time will be ne
From: Ville Syrjälä
Current DSB hardware is apparently a bit borked and likes to signal
spurious GOSUB errors. We already have most for the workarounds for
this in place, but the last part is simply not enabling the corresponding
interrupt.
While at it polish up the w/a comments with the w/a num
From: Ville Syrjälä
When using the flip queue, due to the DMC vs. DSB register corruption
problem, we must not issue any register writes from the DSB after
unhalting the DMC. Currently we are doing just that by trying to
restore DSB_PMCTRL* back to a sane state from intel_dsb_finish().
Since the
From: Ville Syrjälä
If the free_post is not QW aligned we don't have to memset the
extra DW needed to make it so, as the only way that can happen
is via intel_dsb_reg_write_indexed() which already makes sure
the next DW is zeroed.
Not a big deal, but this is more consistent how all the other
stu
From: Ville Syrjälä
Since the introduction of DSB chaining we no longer need the
DEwake tricks in intel_dsb_commit().
I also need to relocate the DSB_PMCTRL* writes out of
intel_dsb_finish() (due to the flip queue DMC vs. DSB register
corruption issues), and it'll be a bit more straightforward i
From: Ville Syrjälä
The upcoming flip queue implementation will need to know the
DSB buffer head and size. Expose those outside intel_dsb.c.
Reviewed-by: Uma Shankar
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsb.c | 9 +++--
drivers/gpu/drm/i915/display/intel_dsb
From: Ville Syrjälä
Some fixes and flip queue related prep work for the DSB.
Extracted from the larger flip queue series just to get a CI run
without the rest of the flip queue cruft possibly getting in the way.
Ville Syrjälä (6):
drm/i915/dsb: Use intel_dsb_ins_align() in intel_dsb_align_tai
From: Ville Syrjälä
Currently we have some asserts to make sure the main DMC has been
loaded. Add similar assers for the pipe DMCs. And we migth as well
just check all the mmio registers the firmware has asked us to
initialize. That also covers the hardcoded SSP/HTP registers we were
checking for
From: Ville Syrjälä
On PTL+ the pipe DMC on pipes C/D loses its MMIO state occasionally.
Not quite sure what the specific sequence is that makes this happen
(eg. simply disabling PG2 doesn't seem to be enough to trigger this
on its own).
Reload the MMIO registers for the affected pipes when enab
From: Ville Syrjälä
I'll need to examine the crtc state during intel_dmc_enable_pipe().
To that end pass the whole crtc into intel_dmc_{enable,disable}_pipe().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 16
drivers/gpu/drm/i915/display/
From: Ville Syrjälä
Supposedly nothing post-MTL (even BMG) needs the pipe DMC clock
gating w/a (Wa_16015201720), so don't apply it.
TODO: check if the ADL/DG2 "clock gating needed during DMC loading" part
is actuall needed, not seeing anything in the docs about it...
Reviewed-by: Uma Shan
From: Ville Syrjälä
On TGL/derivatives the pipe DMC state is lost when PG1 is disabled,
and the main DMC does not restore any of it. This means the state will
also be lost during PSR+DC5/6. It seems safest to not even enable the
pipe DMC in that case (the main DMC does restore the pipe DMC enable
From: Ville Syrjälä
On TGL/derivatives the entire pipe DMC state (program + MMIO) is
lost when PG1 is disabled, and the main DMC does not restore
any of it. Reload the state when enabling a pipe.
The other option would be to not load the pipe DMC at all since
it's only needed for "fast LACE" (wh
From: Ville Syrjälä
Shuffle the DMC_EVT_CTL related stuff around once more. We'll need
this stuff during intel_dmc_enable_pipe(), and this lets us avoid
forward declarations.
Reviewed-by: Uma Shankar
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dmc.c | 144 +++--
From: Ville Syrjälä
The MTL+ pipe DMC clock gating bits can be parametrized.
Make it so.
Reviewed-by: Uma Shankar
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dmc.c | 3 ++-
drivers/gpu/drm/i915/i915_reg.h | 3 +--
2 files changed, 3 insertions(+), 3 deletions(
From: Ville Syrjälä
We'll be needing to reload the program for individual DMCs.
To make that possible pull the code to load the program for
a single DMC into a new function.
This does change the order of things during init/resume
a bit; previously we loaded the program RAM for all DMCs first,
an
From: Ville Syrjälä
Attempt to deal with the fact that pipe DMCs can sometimes
lose their state.
Ville Syrjälä (9):
drm/i915/dmc: Limit pipe DMC clock gating w/a to just ADL/DG2/MTL
drm/i915/dmc: Parametrize MTL_PIPEDMC_GATING_DIS
drm/i915/dmc: Shuffle code around
drm/i915/dmc: Extract d
From: Ville Syrjälä
On PTL+ the PIPEDMC on pipes C/D loses its MMIO state occasionally.
Not quite sure what the specific sequence is that makes this happen
(eg. simply disbling PG2 doesn't seem to be enough to trigger this
on its own).
Reload the MMIO registers for the affected pipes when enabli
From: Ville Syrjälä
The upcoming flip queue implementation will need to know the
DSB buffer head and size. Expose those outside intel_dsb.c.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsb.c | 9 +++--
drivers/gpu/drm/i915/display/intel_dsb.h | 2 ++
2 files changed
From: Ville Syrjälä
Pull the magic 20 usec DSB execution deadline into
intel_dsb_arm_exec_time_us(), and also add its counterapart
for the non-arming register write section. For the non-arming
part we'll just throw in a random 80 usec for now so the total
is 100usec. The total exec time will be n
From: Ville Syrjälä
Support commits via the flip queue (as opposed to DSB or MMIO).
As it's somewhat unknown if we can actually use it is currently
gated behind the new use_flipq modparam, which defaults to disabled.
The implementation has a bunch of limitations that would need
real though to s
From: Ville Syrjälä
Current DSB hardware is apparently a bit borked and likes to signal
spurious GOSUB errors. We already have most for the workarounds for
this in place, but the last part is simply not enabling the corresponding
interrupt.
While at it polish up the w/a comments with the w/a num
From: Ville Syrjälä
When using the flip queue, due to the DMC vs. DSB register corruption
problem, we must not issue any register writes from the DSB after
unhalting the DMC. Currently we are doign just that by trying to
restore DSB_PMCTRL* back to a sane state from intel_dsb_finish().
Since the
From: Ville Syrjälä
Provide the lower level code for PIPEDMC based flip queue.
We'll use the so called semi-full flip queue mode where the
PIPEDMC will start the provided DSB on a scanline a little
ahead of the vblank. We need to program the triggering scanline
early enough so that the DSB has e
From: Ville Syrjälä
Since the introduction of DSB chaining we no longer need the
DEwake tricks in intel_dsb_commit().
I also need to relocate the DSB_PMCTRL* writes out of
intel_dsb_finish() (due to the flip queue DMC vs. DSB register
corruption issues), and it'll be a bit more straightforward i
From: Ville Syrjälä
Currently we have some asserts to make sure the main DMC has been
loaded. Add similar assers for the pipe DMCs. And we migth as well
just check all the mmio registers the firmware has asked us to
initialize. That also covers the hardcoded SSP/HTP registers we were
checking for
From: Ville Syrjälä
AFAIK PKG_C_LATENCY.added_wake_time only matters for flip queue.
As long as we're not using that there's no point in adding any
extra wake time.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_watermark.c | 9 -
1 file changed, 9 deletions(-)
diff
From: Ville Syrjälä
Supposedly nothing post-MTL (even BMG) needs the PIPEDMC clock
gating w/a (Wa_16015201720), so don't apply it.
TODO: check if the ADL/DG2 "clock gating needed during DMC loading" part
is actuall needed, not seeing anything in the docs about it...
Signed-off-by: Ville S
From: Ville Syrjälä
Add a function for dumping the entries of a specific flip queue.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_flipq.c | 46 ++
drivers/gpu/drm/i915/display/intel_flipq.h | 2 +
2 files changed, 48 insertions(+)
diff --git a/drive
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