From: Ville Syrjälä <ville.syrj...@linux.intel.com> We are supposed to switch off the training pattern in DPCD before we start transmitting the idle pattern. For LTTPRs we do that correctly, but for the sink DPRX we only do this correctly for some platforms.
On pre-HSW (where we don't implement the .set_idle_link_train() hook), we directly switch from transmitting the training pattern to normal pixel transmission (the hardware should hopefully guarantee that the minimum number of required idle patters will be transmitted during this transition). The DPCD write correctly precedes the actual switch away from the training pattern. For HSW+ we start transmitting the idle pattern earlier, and only switch off the DPCD training pattern after we switch from the idle pattern to normal pixel transmission. Adjust the code to disable the DPCD training pattern before we start transmitting the idle pattern. v2: Tweak the commit message a bit Tested-by: Imre Deak <imre.d...@intel.com> Reviewed-by: Imre Deak <imre.d...@intel.com> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index a479b63112ea..322a26c1910c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1130,7 +1130,9 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp, intel_dp->link.active = true; - intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX); + if (!intel_dp->set_idle_link_train) + intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX); + intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX, DP_TRAINING_PATTERN_DISABLE); @@ -1371,8 +1373,10 @@ intel_dp_link_train_all_phys(struct intel_dp *intel_dp, if (ret) ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX); - if (intel_dp->set_idle_link_train) + if (intel_dp->set_idle_link_train) { + intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX); intel_dp->set_idle_link_train(intel_dp, crtc_state); + } return ret; } -- 2.49.0