Test-with: <20200407215146.5331-1-bob.j.paa...@intel.com>
Stanislav Lisovskiy (1):
drm/i915: Adding YUV444 packed format support for skl+ (V15)
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 8
drivers/gpu/drm/i915/i915_reg.h
d-by: Matt Roper
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 8
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 14 insertions(+), 1 deletio
sues/454
> [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46
> [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
> [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
> [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
> [i915#677]: https
d-by: Matt Roper
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 8
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 14 insertions(+), 1 deletio
Test-with: 20200127192859.20029-1-bob.j.paa...@intel.com
Stanislav Lisovskiy (1):
drm/i915: Adding YUV444 packed format support for skl+ (V15)
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 8
drivers/gpu/drm/i915/i915_reg.h
3: Rebased.
Added format to ICL format lists.
V14: Added format to TGL format lists.
Rebased.
v12:
Reviewed-by: Ville Syrjälä
Reviewed-by: Matt Roper
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gp
Test-with: 20200127192859.20029-1-bob.j.paa...@intel.com
Stanislav Lisovskiy (1):
drm/i915: Adding YUV444 packed format support for skl+ (V14)
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++
drivers/gpu/drm/i915/i915_reg.h
Add XYUV to the list of DRM Formats to test.
Also fix the byte order for the format.
Signed-off-by: Bob Paauwe
Reviewed-by: Uma Shankar
---
lib/igt_color_encoding.c | 1 +
lib/igt_fb.c | 6 +++---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/lib
3: Rebased.
Added format to ICL format lists.
v12:
Reviewed-by: Ville Syrjälä
Reviewed-by: Matt Roper
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +
drivers/gp
3: Rebased.
Added format to ICL format lists.
v12:
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
This has been updated to support GEN11 along with rebasing it to
the latest drm-tip. A patch to igt has also been posted that gives
igt the
Add XYUV to the list of DRM Formats to test.
Also fix the byte order for the format.
Signed-off-by: Bob Paauwe
---
lib/igt_color_encoding.c | 1 +
lib/igt_fb.c | 6 +++---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/lib/igt_color_encoding.c b/lib
3: Rebased.
v12:
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 9
On Tue, 16 Apr 2019 16:56:26 +0100
Chris Wilson wrote:
> Quoting Bob Paauwe (2019-04-16 00:05:26)
> > There are real-time use cases where having deterministic CPU processes
> > can be more important than GPU power/performance. Parking the GPU at a
> > specific freqency by
t; (combo port A external usage).
>
> - DPLL4 cannot be enabled when DC5 or DC6 are enabled.
>
> - The DPLL4 enable, lock, power enabled, and power state are connected
> to the MGPLL1_ENABLE register.
>
> v2: (suggestions from Bob Paauwe)
> - Rework ehl_get_dpll() fun
On Mon, 15 Apr 2019 17:33:30 -0700
Vanshidhar Konda wrote:
> On Mon, Apr 15, 2019 at 04:05:26PM -0700, Bob Paauwe wrote:
> >There are real-time use cases where having deterministic CPU processes
> >can be more important than GPU power/performance. Parking the GPU at a
> >
nal code"). What got merged fails to do cdclk init/uninit on
> ehl.
Good catch!
Reviewed-by: Bob Paauwe
>
> Fixes: 39564ae86d51 ("drm/i915/ehl: Inherit Ice Lake conditional code")
> Cc: José Roberto de Souza
> Cc: Lucas De Marchi
> Cc: Bob Paauwe
> Cc: Rodri
the ability to configure the GPU "idle" frequecy
using the same method that already exists for minimum and maximum
frequencies.
In addition, parking the idle frequency may reduce spool up latencies
on GPU workloads.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_sy
Unlike ICL, all of the output ports are combo phys so just return
true in intel_port_is_combophy for all EHL ports to indicate that.
v2: Return false in intel_port_is_tc since no EHL ports are TC. (Jose)
Cc: Jose Souza
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm
On Fri, 15 Mar 2019 10:57:11 -0700
Rodrigo Vivi wrote:
> From: Anusha Srivatsa
>
> EHL uses the same firmware as ICL.
Reviewed-by: Bob Paauwe
>
> Cc: Bob Paauwe
> Signed-off-by: Anusha Srivatsa
> Signed-off-by: Rodrigo Vivi
> Reviewed-by: Lucas De
patch cc'ing the appropriated list and maintainers for
> > proper ack.
> > v3: (Rodrigo): - Removed .num_pipes = 3 that is coming since
> > GEN&_FEATURES.
> > - Added ppgtt type and size after rework from Bob and
>
On Fri, 15 Mar 2019 10:01:51 -0700
Rodrigo Vivi wrote:
> On Fri, Mar 15, 2019 at 09:55:47AM -0700, Bob Paauwe wrote:
> > On Fri, 15 Mar 2019 09:09:11 +
> > Chris Wilson wrote:
> >
> > > Quoting Rodrigo Vivi (2019-03-14 22:53:44)
> > > > On Th
that into a common routine.
> > >
> > > Signed-off-by: Chris Wilson
> > > Cc: Bob Paauwe
> > > Cc: Matthew Auld
> > > Cc: Joonas Lahtinen
> >
> > Reviewed-by: Rodrigo Vivi
>
> I've pushed this series so that 36 bits should be
Chris,
Any thoughts on how I can best address your comment on this patch?
Bob
On Thu, 7 Feb 2019 11:13:15 -0800
Bob Paauwe wrote:
> On Thu, 7 Feb 2019 16:41:58 +
> Chris Wilson wrote:
>
> > Quoting Bob Paauwe (2019-02-07 16:29:53)
> > > With the address range
On Thu, 7 Feb 2019 16:41:58 +
Chris Wilson wrote:
> Quoting Bob Paauwe (2019-02-07 16:29:53)
> > With the address range being specified for each platform, we can use
> > that instead of the .ppgtt enum to handle the differences between
> > 3 level and 4 level PPGTT. In
We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.
Signed-off-by: Bob Paauwe
CC: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 4
se on current drm-tip
Signed-off-by: Bob Paauwe
CC: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 7 ++-
drivers/gpu/drm/i915/i915_drv.h | 8 +---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c
ppgtt (both 3-lvl and 4-lvl) so name cap
define appropriately (Chris)
v9: rebase on latest
v10: fix missed vgpu change of FULL_48BIT to FULL in CAPS define (Bob)
v11: rebase on current drm-tip
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
CC: Chris Wilson
---
drivers/g
It's not just GEN9 platforms that allow for pipes to be disabled via
the DFSM register, but all later platforms as well.
v2: drop pointless parentheses (Ville)
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
It's not just GEN9 platforms that allow for pipes to be disabled via
the DFSM register, but all later platforms as well.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
ff-by: Bob Paauwe
CC: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 7 ++-
drivers/gpu/drm/i915/i915_drv.h | 8 +---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm
ppgtt (both 3-lvl and 4-lvl) so name cap
define appropriately (Chris)
v9: rebase on latest
v10: fix missed vgpu change of FULL_48BIT to FULL in CAPS define (Bob)
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
CC: Chris Wilson
---
drivers/gpu/drm/i915/gvt/
We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915
ppgtt (both 3-lvl and 4-lvl) so name cap
define appropriately (Chris)
v9: rebase on latest
v10: fix missed vgpu change of FULL_48BIT to FULL in CAPS define (Bob)
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
CC: Chris Wilson
---
drivers/gpu/drm/i915/gvt/
We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915
ff-by: Bob Paauwe
CC: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 7 ++-
drivers/gpu/drm/i915/i915_drv.h | 8 +---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm
ff-by: Bob Paauwe
CC: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 7 ++-
drivers/gpu/drm/i915/i915_drv.h | 8 +---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm
We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915
ppgtt (both 3-lvl and 4-lvl) so name cap
define appropriately (Chris)
v9: rebase on latest
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
CC: Chris Wilson
---
drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
d
ppgtt (both 3-lvl and 4-lvl) so name cap
define appropriately (Chris)
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
CC: Chris Wilson
---
drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/dr
ff-by: Bob Paauwe
CC: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 7 ++-
drivers/gpu/drm/i915/i915_drv.h | 8 +---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm
We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915
We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915
n now remove the HAS_FULL_PPGTT macro and the devcie
info ppgtt type.
However, there are still a few places where GEN 6's aliasing ppgtt
differences matter. For those cases, it makes just as much sense to
check if we're running on GEN 6 as it does to check a device info flag.
Signed-off
explised in setting vm.total to 1ULL << 32 (Rodrigo)
Gen 7 is 31 bits, not 32 (Chris)
v5: Mock device is 64b(63b) not 48b (Chris)
v6: Rebase to latest drm-tip (Bob)
v7: Combine common code for gen6/gen8 ppgtt create (Chris)
Improve comment on device info field (Chris)
Signed-off-by: Bob Paau
explised in setting vm.total to 1ULL << 32 (Rodrigo)
Gen 7 is 31 bits, not 32 (Chris)
v5: Mock device is 64b(63b) not 48b (Chris)
v6: Rebase to latest drm-tip (Bob)
v7: Combine common code for gen6/gen8 ppgtt create (Chris)
Improve comment on device info field (Chris)
Signed-off-by: Bob Paau
rm-tip (Bob)
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
CC: Chris Wilson
---
drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/dr
On Thu, 13 Sep 2018 20:22:14 +0300
Ville Syrjälä wrote:
> On Thu, Sep 13, 2018 at 10:12:06AM -0700, Bob Paauwe wrote:
> > On Thu, 13 Sep 2018 20:05:54 +0300
> > Ville Syrjälä wrote:
> >
> > > On Thu, Sep 13, 2018 at 10:02:57AM -0700, Bob Paauwe wrote:
> &
On Thu, 13 Sep 2018 20:05:54 +0300
Ville Syrjälä wrote:
> On Thu, Sep 13, 2018 at 10:02:57AM -0700, Bob Paauwe wrote:
> > On Wed, 12 Sep 2018 17:10:58 +0100
> > Chris Wilson wrote:
> >
> > > Quoting Bob Paauwe (2018-09-12 17:04:30)
> > > > d
On Wed, 12 Sep 2018 17:10:58 +0100
Chris Wilson wrote:
> Quoting Bob Paauwe (2018-09-12 17:04:30)
> > diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > index 43ed8b28aeaa..33d7225edbbb 100644
> >
)
Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
v4: Rename FULL_4LVL_PPGTT to simply 4LVL_PPGTT (Rodrigo)
Be explised in setting vm.total to 1ULL << 32 (Rodrigo)
Gen 7 is 31 bits, not 32 (Chris)
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thier
On Mon, 10 Sep 2018 20:56:51 +0100
Chris Wilson wrote:
> Quoting Bob Paauwe (2018-09-10 18:12:25)
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c
> > index d6f7b9fe1d26..e0619952ff52 100644
> > --- a/drivers/gpu/drm/i915/i915_
On Mon, 10 Sep 2018 10:32:42 -0700
Rodrigo Vivi wrote:
> On Mon, Sep 10, 2018 at 10:12:25AM -0700, Bob Paauwe wrote:
> 1;5202;0c> 48 bit ppgtt device configuration is really just extended address
> > range full ppgtt and may actually be something other than 48 bits.
(Rodrigo/Bob)
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
CC: Chris Wilson
Additional work to rename 48bit to 4 level
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu
On Thu, 6 Sep 2018 14:10:35 -0700
Rodrigo Vivi wrote:
> On Thu, Sep 06, 2018 at 01:04:09PM -0700, Bob Paauwe wrote:
> > 48 bit ppgtt device configuration is really just extended address
> > range full ppgtt and may actually be something other than 48 bits.
> >
> > C
On Thu, 6 Sep 2018 21:08:33 +0100
Chris Wilson wrote:
> Quoting Bob Paauwe (2018-09-06 21:04:09)
> > @@ -1647,9 +1647,10 @@ static struct i915_hw_ppgtt
> > *gen8_ppgtt_create(struct drm_i915_private *i915)
> > ppgtt->vm.i915 = i915;
> > ppgtt-
field that specifies the number of
bits to prepare for cases where the range is not 32 or 48 bits.
v2: keep USES_FULL_PPGTT() unchanged (Chris)
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
CC: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu
On Fri, 31 Aug 2018 13:21:40 -0700
Rodrigo Vivi wrote:
> On Fri, Aug 31, 2018 at 04:51:29PM +0100, Chris Wilson wrote:
> > Quoting Bob Paauwe (2018-08-31 16:47:04)
> > > For ppgtt, what we're really interested in is the number of page
> > > walk levels for each
On Fri, 31 Aug 2018 16:51:29 +0100
Chris Wilson wrote:
> Quoting Bob Paauwe (2018-08-31 16:47:04)
> > For ppgtt, what we're really interested in is the number of page
> > walk levels for each platform. Rename the device info fields to
> > reflect this:
&g
the actual
address range. This gives us more flexibility and will work for
cases where we have platforms with different address ranges but
share the same page walk levels.
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 4 +
915/intel_pm.c | 29 ++-
> > drivers/gpu/drm/i915/intel_sprite.c | 38 +++-
> > include/uapi/drm/drm_fourcc.h| 20 ++
> > 7 files changed, 428 insertions(+), 39 deletions(-)
> >
> > --
> > 1.9.1
> >
> > ___
t a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index a38b4f3..24f769a 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -817,7 +817,8 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state
> *crtc_state,
>
On Thu, 30 Mar 2017 09:22:19 +0300
Jani Nikula wrote:
> On Wed, 29 Mar 2017, Bob Paauwe wrote:
> > On Wed, 29 Mar 2017 13:32:58 +0300
> > Jani Nikula wrote:
> >
> >> Sometimes it would be most enlightening to debug systems by replacing
> >> the VBT to
f (!intel_load_vbt_firmware(dev_priv))
> + goto out;
I find the condition a bit confusing. It reads to me as "if firmware
not loaded, goto out" which is backwards from what it's really doing.
Since you're ignoring the error return value anyway, making
intel_loa
On Wed, 29 Mar 2017 13:32:57 +0300
Jani Nikula wrote:
> Leave more breadcrumbs for debuggers.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Bob Paauwe
> ---
> drivers/gpu/drm/i915/intel_opregion.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --gi
On Wed, 29 Mar 2017 13:32:56 +0300
Jani Nikula wrote:
> Seems more sensible this way, and reduces indent for the more common
> case.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Bob Paauwe
> ---
> drivers/gpu/drm/i915/intel_opregion.c | 41
> +---
On Wed, 29 Mar 2017 13:32:55 +0300
Jani Nikula wrote:
> Reduce indent. No functional changes.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Bob Paauwe
> ---
> drivers/gpu/drm/i915/intel_opregion.c | 64
> +--
> 1 file changed, 32 insert
; between the core and the VBT stuff. Let's keep things that way, but
> without the interface.
>
> BR,
> Jani.
This all looks good to me also, so with the update to patch 5
Reviewed-by: Bob Paauwe
>
> Jani Nikula (7):
> drm/i915/dsi: remove support for m
it more obvious any
differences between the different sequences. Thanks Hans!
The rest of the patches in this series look good too. So for the series:
Reviewed-by: Bob Paauwe
> ---
> Changes in v2:
> -Make the comment a table with 3 columns for easier comparison of the
> 3 sequenc
ug.cgi?id=97061
> Signed-off-by: Hans de Goede
Reviewed-by: Bob Paauwe
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index
On Sat, 25 Feb 2017 11:47:32 +0100
Hans de Goede wrote:
> Hi,
>
> On 24-02-17 18:02, Bob Paauwe wrote:
> > On Mon, 20 Feb 2017 15:08:44 +0100
> > Hans de Goede wrote:
> >
> >> According to the spec we should call MIPI_SEQ_TEAR_ON and DISPLAY_ON
>
On Sat, 25 Feb 2017 11:49:09 +0100
Hans de Goede wrote:
> HI,
>
> On 24-02-17 18:02, Bob Paauwe wrote:
> > On Mon, 20 Feb 2017 15:08:45 +0100
> > Hans de Goede wrote:
> >
> >> For v3 VBTs in vid-mode the delays are part of the VBT sequences, so
>
On Sat, 25 Feb 2017 11:42:09 +0100
Hans de Goede wrote:
> Hi,
>
> On 24-02-17 18:02, Bob Paauwe wrote:
> > On Mon, 20 Feb 2017 15:08:42 +0100
> > Hans de Goede wrote:
> >
> >> According to the spec for v2 VBTs we should call MIPI_SEQ_DISPLAY_OFF
> >
On Sat, 25 Feb 2017 11:37:50 +0100
Hans de Goede wrote:
> Hi,
>
> On 24-02-17 18:00, Bob Paauwe wrote:
> > On Mon, 20 Feb 2017 15:08:41 +0100
> > Hans de Goede wrote:
> >
> >> Execute the MIPI_SEQ_BACKLIGHT_ON/OFF VBT sequences at the same time as
>
On Sat, 25 Feb 2017 11:35:03 +0100
Hans de Goede wrote:
> Hi,
>
> On 24-02-17 18:00, Bob Paauwe wrote:
> > On Mon, 20 Feb 2017 15:08:37 +0100
> > Hans de Goede wrote:
> >
> >> MIPI_SEQ_ASSERT_RESET before POWER_ON is not necessary for 2 reasons:
> >
uence(intel_dsi, MIPI_SEQ_POWER_OFF);
> if (intel_dsi->gpio_panel)
> gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
> @@ -814,7 +825,7 @@ static void intel_dsi_post_disable(struct intel_encoder
> *encoder,
>* FIXME As we do wi
PI_SEQ_DISPLAY_ON);
> } else {
> msleep(20); /* XXX */
> for_each_dsi_port(port, intel_dsi->ports)
--
--
Bob Paauwe
bob.j.paa...@intel.com
IOTG / PED Software Organization
Intel Corp. Folsom, CA
(916) 356-6193
_
I_SEQ_TEAR_OFF);
> intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
>
> /* Transition to LP-00 */
--
--
Bob Paauwe
bob.j.paa...@intel.com
IOTG / PED Software Organization
Intel Corp. Folsom, CA
(916) 356-6193
_
tdown packet then in
>* some next enable sequence send turn on packet error is observed
> + * XXX spec specifies SHUTDOWN before MIPI_SEQ_DISPLAY_OFF for
> + * v3 VBTs, but not for v2 VBTs?
>*/
> intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OF
On Mon, 20 Feb 2017 15:08:38 +0100
Hans de Goede wrote:
> Now that we are no longer bound to the drm_panel_ callbacks, call
> MIPI_SEQ_POWER_ON/OFF at the proper place.
>
> Signed-off-by: Hans de Goede
Reviewed-by: Bob Paauwe
> ---
> drivers/gpu/drm/i915/intel_dsi.c |
lp-00
> + * - MIPIAssertResetPin
> + * - wait t3
> + * - power off
> + * - wait t4
> + */
> +
> static void intel_dsi_pre_enable(struct intel_encoder *encoder,
>struct intel_crtc_state *pipe_config,
>struct drm_co
EQ_POWER_ON);
> intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
> intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
--
--
Bob Paauwe
bob.j.paa...@intel.com
IOTG / PED Software Organization
Intel Corp. Folsom, CA
(916) 356-
> if (IS_BROXTON(dev_priv)) {
> @@ -785,6 +789,7 @@ static void intel_dsi_post_disable(struct intel_encoder
> *encoder,
> I915_WRITE(DSPCLK_GATE_D, val);
> }
>
> + /* Assert reset */
Again, the comment doesn't provide any additional info.
But the rest looks
nable
>
> Signed-off-by: Hans de Goede
Makes sense and looks better too.
Reviewed-by: Bob Paauwe
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 16
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/
nts are necessary. Maybe if there was
some explanation for why we're using two different mechanisms to
enable/disable backlight instead.
Reviewed-by: Bob Paauwe
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --g
anel _enable/disable and prepare/unprepare callbacks and instead
> export intel_dsi_exec_vbt_sequence() from intel_dsi_panel_vbt.c
> and call that from intel_dsi_enable/disable().
>
> No functional changes.
>
> Signed-off-by: Hans de Goede
Reviewed-by: Bob Paauwe
> ---
&g
tting in the middle of them.
>
> This commit purely moves code around, it does not make any
> changes what-so-ever.
>
> Signed-off-by: Hans de Goede
> Acked-by: Jani Nikula
Reviewed-by: Bob Paauwe
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 86
> ---
tel_dsi = enc_to_intel_dsi(&encoder->base);
> - enum port port;
> - u32 temp;
> -
> - DRM_DEBUG_KMS("\n");
> -
> - if (is_vid_mode(intel_dsi)) {
> - for_each_dsi_port(port, intel_dsi->ports)
> -
isable paths. No functional changes.
>
> Signed-off-by: Hans de Goede
> Acked-by: Jani Nikula
Reviewed-by: Bob Paauwe
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 37 -
> 1 file changed, 24 insertions(+), 13 deletions(-)
>
> diff --gi
FIFO status into one function. But that's probably a separate patch.
I like what this is doing.
Reviewed-by: Bob Paauwe
> +void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
> {
> struct drm_encoder *encoder = &intel_dsi->base.base;
>
gt; return 0;
> @@ -550,6 +547,7 @@ static int vbt_panel_get_modes(struct drm_panel *panel)
> static int vbt_panel_power_on(struct drm_panel *panel)
> {
> generic_exec_sequence(panel, MIPI_SEQ_POWER_ON);
> + generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET);
> retur
o expand
the use of the drm_panel interfaces but instead move to an i915 only
panel interface. This would allow us to have more granular control
over the sequences.
But since this is actually adding new drm_panel interfaces,
Acknowledged-by: Bob Paauwe
> ---
> drivers/gpu/drm/i915/i
On Wed, 8 Feb 2017 16:20:57 +0530
Vidya Srinivas wrote:
> From: Uma Shankar
>
> Enable support for BXT DSI dual link mode.
>
> Signed-off-by: Uma Shankar
> Signed-off-by: Vidya Srinivas
Reviewed-by: Bob Paauwe
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +
On Wed, 8 Feb 2017 16:20:56 +0530
Vidya Srinivas wrote:
> From: Uma Shankar
>
> Disable device ready before MIPI port shutdown command.
> This helps to avoid mipi split screen issues.
>
> Signed-off-by: Uma Shankar
> Signed-off-by: Vidya Srinivas
Reviewed-by: Bob Paau
drm_panel_power_off(intel_dsi->panel);
This depends on the previous patch, which I don't think is the
direction we want to go. If the code is reworked to not use the
drm_panel interface, then this would need to change also.
> msleep(i
On Wed, 8 Feb 2017 16:20:54 +0530
Vidya Srinivas wrote:
> From: Uma Shankar
>
> Fix the Sequence to program BXT DSI Latch and ULPS.
>
> Signed-off-by: Uma Shankar
> Signed-off-by: Vidya Srinivas
Reviewed-by: Bob Paauwe
> ---
> drivers/gpu/d
"panel", GPIOD_OUT_HIGH);
>
It makes sense to restrict this as it isn't valid for other platforms
as written. But is there something similar for other platforms that we
should set up here?
Since it makes sense to limit this today..
Reviewed-by: Bob Paauwe
--
--
B
On Wed, 21 Dec 2016 08:45:46 +0200
Mika Kahola wrote:
> Hi Bob,
>
> On Tue, 2016-12-20 at 09:53 -0800, Bob Paauwe wrote:
> > On Tue, 13 Dec 2016 16:11:20 +0200
> > Jani Nikula wrote:
> >
> > >
> > > On Mon, 05 Dec 2016, Mika Kahola
sion == 2)
> > @@ -328,11 +354,11 @@ static const u8 *mipi_exec_gpio(struct intel_dsi
> > *intel_dsi, const u8 *data)
> > value = *data++ & 1;
> >
> > if (IS_VALLEYVIEW(dev_priv))
> > - vlv_exec_gpio(dev_priv, gpio_so
I currently have this same patch in my tree (well with the two changes
below) and have been testing it so with the changes.
Reviewed-by: Bob Paauwe
Tested-by: Bob Paauwe
On Wed, 7 Dec 2016 20:32:18 +0530 Vidya Srinivas
wrote:
> Currently the backlight controller is taken as 0. It needs
For BXT, there is only one bit that enables/disables dual-link mode
and not different bits depending on which pipe is being used.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_dsi.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
1 - 100 of 227 matches
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