On Mon, 20 Feb 2017 15:08:33 +0100
Hans de Goede <hdego...@redhat.com> wrote:
> The enable path has an intel_dsi_prepare() helper which prepares various
> registers for the mode-set. Move the code undoing this to a new
> intel_dsi_unprepare() helper function for better symmetry between the
> enable and disable paths. No functional changes.
>
> Signed-off-by: Hans de Goede <hdego...@redhat.com>
> Acked-by: Jani Nikula <jani.nik...@intel.com>
Reviewed-by: Bob Paauwe <bob.j.paa...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 37 ++++++++++++++++++++++++-------------
> 1 file changed, 24 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index e808dce..d741280 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -507,6 +507,7 @@ static void intel_dsi_port_disable(struct intel_encoder
> *encoder)
>
> static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> struct intel_crtc_state *pipe_config);
> +static void intel_dsi_unprepare(struct intel_encoder *encoder);
>
> static void intel_dsi_pre_enable(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config,
> @@ -682,19 +683,7 @@ static void intel_dsi_post_disable(struct intel_encoder
> *encoder,
> usleep_range(2000, 5000);
> }
>
> - for_each_dsi_port(port, intel_dsi->ports) {
> - /* Panel commands can be sent when clock is in LP11 */
> - I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
> -
> - intel_dsi_reset_clocks(encoder, port);
> - I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> -
> - val = I915_READ(MIPI_DSI_FUNC_PRG(port));
> - val &= ~VID_MODE_FORMAT_MASK;
> - I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
> -
> - I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
> - }
> + intel_dsi_unprepare(encoder);
>
> /*
> * if disable packets are sent before sending shutdown packet then in
> @@ -1303,6 +1292,28 @@ static void intel_dsi_prepare(struct intel_encoder
> *intel_encoder,
> }
> }
>
> +static void intel_dsi_unprepare(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + enum port port;
> + u32 val;
> +
> + for_each_dsi_port(port, intel_dsi->ports) {
> + /* Panel commands can be sent when clock is in LP11 */
> + I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
> +
> + intel_dsi_reset_clocks(encoder, port);
> + I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> +
> + val = I915_READ(MIPI_DSI_FUNC_PRG(port));
> + val &= ~VID_MODE_FORMAT_MASK;
> + I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
> +
> + I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
> + }
> +}
> +
> static int intel_dsi_get_modes(struct drm_connector *connector)
> {
> struct intel_connector *intel_connector = to_intel_connector(connector);
--
--
Bob Paauwe
bob.j.paa...@intel.com
IOTG / PED Software Organization
Intel Corp. Folsom, CA
(916) 356-6193
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