From: Suraj Kandpal
Add new bit range for Max PHY Swing Setup in PORT_ALPM_CTL
register for DISPLAY_VER >= 30.
v2: implement as two seperate macros instead of a single macro
v3: extend previous definition by 2 bits that were previously reserved
Bspec: 70277
Signed-off-by: Suraj Kandpal
Signed-
On Fri, Oct 11, 2024 at 03:54:26PM -0700, Lucas De Marchi wrote:
> Both the documentation and most of other users call the return of
> cpuhp_setup_state_multi() as "state". Follow that.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_pmu.c | 14 +++
On Fri, Oct 11, 2024 at 03:54:25PM -0700, Lucas De Marchi wrote:
> When an i915 PMU counter is enabled and the driver is then unbound, the
> PMU will be unregistered via perf_pmu_unregister(), however the event
> will still be alive. i915 currently tries to deal with this situation
> by:
>
>
On Fri, Oct 11, 2024 at 03:54:24PM -0700, Lucas De Marchi wrote:
> There's no need to free the resources during unbind. Since perf events
> may still access them due to open events, it's safer to free them when
> dropping the last i915 reference. It will also allow to ask perf to
> release its own
On Fri, Oct 18, 2024 at 01:49:34PM -0700, Matt Atwood wrote:
> From: Ravi Kumar Vodapalli
>
> From platforms xe3 Underrun recovery does not exist
>
> BSpec: 68849
> Signed-off-by: Ravi Kumar Vodapalli
> Signed-off-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
>
On Fri, Oct 18, 2024 at 01:49:33PM -0700, Matt Atwood wrote:
> From: Dnyaneshwar Bhadane
>
> The async flip moved from PLANE_CTL to PLANE_SURF for PTL.
The subject and commit message should be referring to Xe3_LPD rather
than Panther Lake. This is a change in the display IP and if other
non-PTL
On Fri, Oct 18, 2024 at 01:49:31PM -0700, Matt Atwood wrote:
> From: Dnyaneshwar Bhadane
>
> Common display code requires IS_PANTHERLAKE macro.
> Define the macro and set 0 as PTL is no longer support for i915.
>
> Signed-off-by: Dnyaneshwar Bhadane
> Signed-off-by: Matt Atwood
Jani is refact
On Fri, Oct 18, 2024 at 01:49:30PM -0700, Matt Atwood wrote:
> From: Mitul Golani
>
> In progress to make VRR timing generator as the default timing generator,
> rest other timings will be derived based on vrr.vmin and vrr.vmax. Call
I'm having trouble following what this first sentence is tryin
On Fri, Oct 18, 2024 at 01:03:09PM -0700, Matt Atwood wrote:
> From: Suraj Kandpal
>
> Add new bit range for Max PHY Swing Setup in PORT_ALPM_CTL
> register for DISPLAY_VER >= 30.
>
> v2: implement as two seperate macros instead of a single macro
> v3: extend previous definition by 2 bits that w
During GuC reset prepare, interrupt disabled before hardware reset.
Add disable ct to prevent unnecessary message processing.
Signed-off-by: Zhanjun Dong
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 3 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 ++
2 files changed, 5 in
== Series Details ==
Series: FOR-CI: drm/i915/guc: Disable ct during GuC reset
URL : https://patchwork.freedesktop.org/series/140197/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15562 -> Patchwork_140197v1
Summary
---
== Series Details ==
Series: drm/i915/xe3lpd: ptl display patches
URL : https://patchwork.freedesktop.org/series/140196/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15562 -> Patchwork_140196v1
Summary
---
**FAILURE
From: Dnyaneshwar Bhadane
Common display code requires IS_PANTHERLAKE macro.
Define the macro and set 0 as PTL is no longer support for i915.
Signed-off-by: Dnyaneshwar Bhadane
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/d
== Series Details ==
Series: drm/i915/xe3lpd: ptl display patches
URL : https://patchwork.freedesktop.org/series/140196/
State : warning
== Summary ==
Error: dim checkpatch failed
a321afa49956 drm/i915/display/ptl: Fill VRR crtc_state timings before other
transcoder timings
-:9: WARNING:TYPO_
== Series Details ==
Series: drm/i915/xe3lpd: ptl display patches
URL : https://patchwork.freedesktop.org/series/140196/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
From: Suraj Kandpal
>From DISPLAY_VER() >= 30 C20 PHY consolidated programming table of
DP and eDP been merged and now use the same rates and values. eDP
over TypeC has also been introduced.
Moreover it allows more granular and higher rates. Add new table to
represent this change.
Bspec: 68961
S
== Series Details ==
Series: Add xe3lpd edp enabling (rev4)
URL : https://patchwork.freedesktop.org/series/139731/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15562 -> Patchwork_139731v4
Summary
---
**SUCCESS**
== Series Details ==
Series: Add xe3lpd edp enabling (rev4)
URL : https://patchwork.freedesktop.org/series/139731/
State : warning
== Summary ==
Error: dim checkpatch failed
a9981eac7be9 drm/i915/xe3lpd: Update pmdemand programming
-:75: ERROR:ELSE_AFTER_BRACE: else should follow close brace '
== Series Details ==
Series: Add xe3lpd edp enabling (rev4)
URL : https://patchwork.freedesktop.org/series/139731/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/display: Fuse bit for power management disable removed (rev2)
URL : https://patchwork.freedesktop.org/series/139583/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15562 -> Patchwork_139583v2
On Fri, Oct 18, 2024 at 1:56 PM André Almeida wrote:
>
> Em 18/10/2024 12:31, Alex Deucher escreveu:
> > On Fri, Oct 18, 2024 at 11:23 AM Rodrigo Vivi
> > wrote:
> >>
> >> On Thu, Oct 17, 2024 at 04:16:09PM -0300, André Almeida wrote:
> >>> Hi Raag,
> >>>
> >>> Em 30/09/2024 04:38, Raag Jadav es
From: Mitul Golani
In progress to make VRR timing generator as the default timing generator,
rest other timings will be derived based on vrr.vmin and vrr.vmax. Call
intel_vrr_get_config before intel_get_transcoder_timings to accomodate
values getting pre-filled.
Signed-off-by: Mitul Golani
Sign
During GuC reset prepare, interrupt disabled before hardware reset.
Add disable ct to prevent unnecessary message processing.
Signed-off-by: Zhanjun Dong
Zhanjun Dong (1):
drm/i915/guc: Disable ct during GuC reset
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 3 +++
drivers/gpu/drm/i91
From: Mika Kahola
There is a HW issue that arises when there are race conditions
between TCSS entering/exiting TC7 or TC10 states while the
driver is asserting/deasserting TCSS power request. As a
workaround, Display driver will implement a mailbox sequence
to ensure that the TCSS is in TC0 when
From: Suraj Kandpal
Spec states that PSR max active is same as max pipe active values.
Now that each pipe supports 6k resolution increasing max_h and
max_v for PSR too.
Signed-off-by: Suraj Kandpal
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/intel_psr.c | 6 +-
1 file chan
From: Suraj Kandpal
With 6k resolution support for a single crtc being added
bigjoiner will only come into picture when hdisplay > 6144
Signed-off-by: Suraj Kandpal
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
From: "Heikkila, Juha-pekka"
Xe3 has no more support for x-tile on display.
Signed-off-by: Heikkila, Juha-pekka
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b
From: Suraj Kandpal
We only support resolution upto 4k for single pipe when using
YUV420 format so we prune these modes and restrict the plane size
at src.
Signed-off-by: Suraj Kandpal
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/intel_dp.c| 11 +--
drivers/
From: Ravi Kumar Vodapalli
Spec does not request to disable VRR in the modeset disabling
sequence for DP and HDMI for xe3_lpd.
Bspec: 68848
Signed-off-by: Ravi Kumar Vodapalli
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/intel_display.c | 8 +---
1 file changed, 5 insertion
From: Suraj Kandpal
DISPLAY_VER >= 30 onwards CRTC can now support 6k resolution.
Increase pipe and plane max width and height to reflect this
increase in resolution.
Signed-off-by: Arun R Murthy
Signed-off-by: Suraj Kandpal
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/intel_d
This series builds on the previous one, further enabling new features
for the platform.
Dnyaneshwar Bhadane (3):
drm/i915/ptl: Define IS_PANTHERLAKE macro
drm/i915/cx0: Extend C10 check to PTL
drm/i915/ptl: Move async flip bit to PLANE_SURF register
Heikkila, Juha-pekka (1):
drm/i915/dis
From: Ravi Kumar Vodapalli
>From platforms xe3 Underrun recovery does not exist
BSpec: 68849
Signed-off-by: Ravi Kumar Vodapalli
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
From: Dnyaneshwar Bhadane
The async flip moved from PLANE_CTL to PLANE_SURF for PTL.
Bspec: 69853,69878
Signed-off-by: Dnyaneshwar Bhadane
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 13 +
.../gpu/drm/i915/display/skl_universal_plane_regs.h
From: Dnyaneshwar Bhadane
When deciding the type of the phy, Add PTL support to make
sure the correct path is taken for selection of C10 PHY.
Only port A is connected C10 PHY for Pantherlake.
Bspec: 72571
Signed-off-by: Dnyaneshwar Bhadane
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/
This series defines the xe3lpd definition, which is functionally
identical to the xe2lpd definition for now. This series then adds
additional requirements mostly for edp output of display through type c.
Additional patches will be required for display and will follow.
v2: cdclk table upda
From: Suraj Kandpal
Read PICA register to see if edp over type C is possible and then
add the appropriate tables for it.
--v2
-remove bool from intel_encoder have it in runtime_info [Jani]
-initialize the bool in runtime_info init [Jani]
-dont abbreviate the bool [Jani]
Bspec: 68846
Signed-off-
From: Radhakrishna Sripada
Xe3_LPD has new max cdclk of 691200 which requires reusing the lnl table
and modify/add higher frequencies. Updating the max cdclk supported by
the platform and voltage_level determination is also updated.
There are minor changes in cdclk programming sequence compared
From: Suraj Kandpal
We need to disable HDCP Line Rekeying for Xe3 when we are using an HDMI
encoder.
v2: add additional definition instead of function, commit message typo
fix and update.
v3: restore lost conditional from v2.
v4: subject line and subject message updated, fix the if ladder order,
From: Matt Roper
There are some minor changes to pmdemand handling on Xe3:
- Active scalers are no longer tracked. We can simply skip the readout
and programming of this field.
- Active dbuf slices are no longer tracked. We should skip the readout
and programming of this field and also
From: Suraj Kandpal
Add condition for P2.PG power down value.
v2: change subject line to better match patch condition
Bspec: 74494
Signed-off-by: Suraj Kandpal
Signed-off-by: Matt Atwood
Reviewed-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 ++-
1 file changed, 2 ins
Starting with Display 13 the fuse bit to disable Display PM has been
removed.
v2: Bit removed starting with Display13 (MattR)
BSPEC: 69464
Cc: Matt Roper
Signed-off-by: Clint Taylor
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/intel_display_device.c | 6 --
1 file changed, 4
Em 18/10/2024 12:31, Alex Deucher escreveu:
On Fri, Oct 18, 2024 at 11:23 AM Rodrigo Vivi wrote:
On Thu, Oct 17, 2024 at 04:16:09PM -0300, André Almeida wrote:
Hi Raag,
Em 30/09/2024 04:38, Raag Jadav escreveu:
Introduce device wedged event, which will notify userspace of wedged
(hanged/unu
On 18-10-2024 21:29, Gustavo Sousa wrote:
Quoting Pottumuttu, Sai Teja (2024-10-18 11:16:43-03:00)
On 18-10-2024 02:23, Gustavo Sousa wrote:
There has been an update to the Bspec in which we need to set
tx_misc=0x5 field for C20 TX Context programming for HDMI TMDS for
Xe2_LPD and newer. That
Quoting Pottumuttu, Sai Teja (2024-10-18 11:16:43-03:00)
>
>On 18-10-2024 02:23, Gustavo Sousa wrote:
>> There has been an update to the Bspec in which we need to set
>> tx_misc=0x5 field for C20 TX Context programming for HDMI TMDS for
>> Xe2_LPD and newer. That field is mapped to the bits 7:0 of
On Fri, Oct 18, 2024 at 11:23 AM Rodrigo Vivi wrote:
>
> On Thu, Oct 17, 2024 at 04:16:09PM -0300, André Almeida wrote:
> > Hi Raag,
> >
> > Em 30/09/2024 04:38, Raag Jadav escreveu:
> > > Introduce device wedged event, which will notify userspace of wedged
> > > (hanged/unusable) state of the DRM
On Thu, Oct 17, 2024 at 04:16:09PM -0300, André Almeida wrote:
> Hi Raag,
>
> Em 30/09/2024 04:38, Raag Jadav escreveu:
> > Introduce device wedged event, which will notify userspace of wedged
> > (hanged/unusable) state of the DRM device through a uevent. This is
> > useful especially in cases wh
On 18-10-2024 02:23, Gustavo Sousa wrote:
There has been an update to the Bspec in which we need to set
tx_misc=0x5 field for C20 TX Context programming for HDMI TMDS for
Xe2_LPD and newer. That field is mapped to the bits 7:0 of
SRAM_GENERIC__TX_CNTX_CFG_1, which in turn translates to tx[1] of
On Fri, Oct 18, 2024 at 02:54:38PM +0200, Christian König wrote:
> Am 18.10.24 um 14:46 schrieb Raag Jadav:
> > > As far as I can see this makes the enum how to recover the device
> > > superfluous because you will most likely always need a bus reset to get
> > > out
> > > of this again.
> > That
Quoting Patchwork (2024-10-16 16:32:12-03:00)
>== Series Details ==
>
>Series: Miscelaneous fixes for display tracepoints (rev4)
>URL : https://patchwork.freedesktop.org/series/137978/
>State : warning
>
>== Summary ==
>
>Error: patch
>https://patchwork.freedesktop.org/api/1.0/series/137978/revi
Am 18.10.24 um 14:46 schrieb Raag Jadav:
As far as I can see this makes the enum how to recover the device
superfluous because you will most likely always need a bus reset to get out
of this again.
That depends on the kind of fault the device has encountered and the bus it is
sitting on. There c
On Fri, Oct 18, 2024 at 12:58:09PM +0200, Christian König wrote:
> Am 17.10.24 um 18:43 schrieb Rodrigo Vivi:
> > On Thu, Oct 17, 2024 at 09:59:10AM +0200, Christian König wrote:
> > > > > Purpose of this implementation is to provide drivers a generic way to
> > > > > recover with the help of users
Am 17.10.24 um 18:43 schrieb Rodrigo Vivi:
On Thu, Oct 17, 2024 at 09:59:10AM +0200, Christian König wrote:
Purpose of this implementation is to provide drivers a generic way to
recover with the help of userspace intervention. Different drivers may
have different ideas of a "wedged device" depen
> -Original Message-
> From: Intel-xe On Behalf Of Matt
> Atwood
> Sent: Wednesday, 16 October 2024 2.11
> To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Kandpal, Suraj ; Atwood, Matthew S
>
> Subject: [PATCH v3 7/7] drm/i915/xe3lpd: Add condition for EDP to pow
> -Original Message-
> From: Intel-gfx On Behalf Of Matt
> Atwood
> Sent: Wednesday, 16 October 2024 2.11
> To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Kandpal, Suraj ; Atwood, Matthew S
>
> Subject: [PATCH v3 6/7] drm/i915/xe3lpd: Add check to see if edp ove
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