From: Mika Kahola <mika.kah...@intel.com>
There is a HW issue that arises when there are race conditions
between TCSS entering/exiting TC7 or TC10 states while the
driver is asserting/deasserting TCSS power request. As a
workaround, Display driver will implement a mailbox sequence
to ensure that the TCSS is in TC0 when TCSS power request is
asserted/deasserted.
The sequence is the following
1. Read mailbox command status and wait until run/busy bit is
clear
2. Write mailbox data value '1' for power request asserting
and '0' for power request deasserting
3. Write mailbox command run/busy bit and command value with 0x1
4. Read mailbox command and wait until run/busy bit is clear
before continuing power request.
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atw...@intel.com>
---
drivers/gpu/drm/i915/display/intel_tc.c | 40 +++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 7 +++++
2 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index 6f2ee7dbc43b..7d9f87db381c 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -1013,6 +1013,39 @@ xelpdp_tc_phy_wait_for_tcss_power(struct intel_tc_port
*tc, bool enabled)
return true;
}
+static bool xelpdp_tc_phy_wait_for_tcss_ready(struct drm_i915_private *i915,
+ bool enable)
+{
+ if (DISPLAY_VER(i915) < 30)
+ return true;
+
+ /* check if mailbox is running busy */
+ if (intel_de_wait_for_clear(i915, TCSS_DISP_MAILBOX_IN_CMD,
+ TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY, 10)) {
+ drm_dbg_kms(&i915->drm,
+ "timeout waiting for TCSS mailbox run/busy bit to
clear\n");
+ return false;
+ }
+
+ if (enable)
+ intel_de_write(i915, TCSS_DISP_MAILBOX_IN_DATA, 1);
+ else
+ intel_de_write(i915, TCSS_DISP_MAILBOX_IN_DATA, 0);
+
+ intel_de_write(i915, TCSS_DISP_MAILBOX_IN_CMD,
+ TCSS_DISP_MAILBOX_IN_CMD_DATA(1));
+
+ /* wait to clear mailbox running busy bit before continuing */
+ if (intel_de_wait_for_clear(i915, TCSS_DISP_MAILBOX_IN_CMD,
+ TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY, 10)) {
+ drm_dbg_kms(&i915->drm,
+ "timeout waiting for TCSS mailbox run/busy bit to
clear\n");
+ return false;
+ }
+
+ return true;
+}
+
static void __xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool
enable)
{
struct drm_i915_private *i915 = tc_to_i915(tc);
@@ -1022,6 +1055,13 @@ static void __xelpdp_tc_phy_enable_tcss_power(struct
intel_tc_port *tc, bool ena
assert_tc_cold_blocked(tc);
+ /*
+ * Gfx driver workaround for PTL tcss_rxdetect_clkswb_req/ack handshake
+ * violation when pwwreq= 0->1 during TC7/10 entry
+ */
+ drm_WARN_ON(&i915->drm,
+ !xelpdp_tc_phy_wait_for_tcss_ready(i915, enable));
+
val = intel_de_read(i915, reg);
if (enable)
val |= XELPDP_TCSS_POWER_REQUEST;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2743a2dd0a3d..d2775a32bf18 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4539,6 +4539,13 @@ enum skl_power_gate {
#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
+#define TCSS_DISP_MAILBOX_IN_CMD _MMIO(0x161300)
+#define TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY REG_BIT(31)
+#define TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK REG_GENMASK(7, 0)
+#define TCSS_DISP_MAILBOX_IN_CMD_DATA(x)
TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY | \
+
REG_FIELD_PREP(TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK, (x))
+#define TCSS_DISP_MAILBOX_IN_DATA _MMIO(0x161304)
+
#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
--
2.45.0
