On Fri, Oct 18, 2024 at 01:03:09PM -0700, Matt Atwood wrote: > From: Suraj Kandpal <suraj.kand...@intel.com> > > Add new bit range for Max PHY Swing Setup in PORT_ALPM_CTL > register for DISPLAY_VER >= 30. > > v2: implement as two seperate macros instead of a single macro > v3: extend previous definition by 2 bits that were previously reserved > > Bspec: 70277 > Signed-off-by: Suraj Kandpal <suraj.kand...@intel.com> > Signed-off-by: Matt Atwood <matthew.s.atw...@intel.com>
Reviewed-by: Matt Roper <matthew.d.ro...@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > index 0841242543ca..9ad7611506e8 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > @@ -298,7 +298,7 @@ > #define _PORT_ALPM_CTL_B 0x16fc2c > #define PORT_ALPM_CTL(port) _MMIO_PORT(port, > _PORT_ALPM_CTL_A, _PORT_ALPM_CTL_B) > #define PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(31) > -#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(23, 20) > +#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(25, 20) > #define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) > REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val) > #define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK REG_GENMASK(19, 16) > #define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(val) > REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK, val) > -- > 2.45.0 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
