> -Original Message-
> From: Cheng, Michael
> Sent: Friday, January 28, 2022 2:10 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Cheng, Michael ; Bowman, Casey G
> ; De Marchi, Lucas
> ; Boyer, Wayne ;
> ville.syrj...@linux.intel.com; Kuoppala, Mika ;
> Auld, Matthew
> Subject: [PATCH
> -Original Message-
> From: Cheng, Michael
> Sent: Friday, January 28, 2022 2:10 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Cheng, Michael ; Bowman, Casey G
> ; De Marchi, Lucas
> ; Boyer, Wayne ;
> ville.syrj...@linux.intel.com; Kuoppala, Mika ;
> Auld, Matthew
> Subject: [PATCH
> -Original Message-
> From: Cheng, Michael
> Sent: Friday, January 28, 2022 2:10 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Cheng, Michael ; Bowman, Casey G
> ; De Marchi, Lucas
> ; Boyer, Wayne ;
> ville.syrj...@linux.intel.com; Kuoppala, Mika ;
> Auld, Matthew
> Subject: [PATCH
> -Original Message-
> From: Cheng, Michael
> Sent: Friday, January 28, 2022 2:10 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Cheng, Michael ; Bowman, Casey G
> ; De Marchi, Lucas
> ; Boyer, Wayne ;
> ville.syrj...@linux.intel.com; Kuoppala, Mika ;
> Auld, Matthew
> Subject: [PATCH
> -Original Message-
> From: Cheng, Michael
> Sent: Thursday, January 27, 2022 3:41 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Cheng, Michael ; Bowman, Casey G
> ; De Marchi, Lucas
> ; Boyer, Wayne ;
> ville.syrj...@linux.intel.com; Kuoppala, Mika ;
> ch...@chris-wilson.co.uk
> Subj
== Series Details ==
Series: Use drm_clflush* instead of clflush (rev2)
URL : https://patchwork.freedesktop.org/series/99450/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11159_full -> Patchwork_22141_full
Summary
---
== Series Details ==
Series: Misc DG2 enabling patches
URL : https://patchwork.freedesktop.org/series/99490/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11159_full -> Patchwork_22140_full
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915/dg2: s/engine->i915/i915/ for engine workarounds
URL : https://patchwork.freedesktop.org/series/99484/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11159_full -> Patchwork_22139_full
S
== Series Details ==
Series: Use drm_clflush* instead of clflush (rev2)
URL : https://patchwork.freedesktop.org/series/99450/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11159 -> Patchwork_22141
Summary
---
**SUCCE
On 28/01/2022 21:53, John Harrison wrote:
On 1/28/2022 01:34, Tvrtko Ursulin wrote:
John,
What CI results were used to merge this particular single patch?
Unless I am not seeing it, it was always set in pair with something else.
First with "drm/i915/pmu: Use PM timestamp instead of RING T
== Series Details ==
Series: Use drm_clflush* instead of clflush (rev2)
URL : https://patchwork.freedesktop.org/series/99450/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On 27/01/2022 11:56, Thomas Hellström wrote:
The vma destruction code was using an unlocked advisory check for
drm_mm_node_allocated() to avoid racing with eviction code unbinding
the vma.
This is very fragile and prohibits the dereference of non-refcounted
pointers of dying vmas after a call
== Series Details ==
Series: Use drm_clflush* instead of clflush (rev2)
URL : https://patchwork.freedesktop.org/series/99450/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c57ea525b16d drm/i915/gt: Re-work intel_write_status_page
addcbfa4043f drm/i915/gt: Re-work invalidate_csb
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/
Re-work invalidate_csb_entries to use drm_clflush_virt_range. This will
prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/d
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/driv
This patch series re-work a few i915 functions to use drm_clflush_virt_range
instead of calling clflush or clflushopt directly. This will prevent errors
when building for non-x86 architectures.
v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added
more patches to convert ad
On 1/28/2022 01:34, Tvrtko Ursulin wrote:
John,
What CI results were used to merge this particular single patch?
Unless I am not seeing it, it was always set in pair with something else.
First with "drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP
for reference", which was merged ea
== Series Details ==
Series: drm/i915: M/N cleanup (rev4)
URL : https://patchwork.freedesktop.org/series/99409/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11158_full -> Patchwork_22138_full
Summary
---
**SUCCESS**
== Series Details ==
Series: Misc DG2 enabling patches
URL : https://patchwork.freedesktop.org/series/99490/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11159 -> Patchwork_22140
Summary
---
**SUCCESS**
No regres
== Series Details ==
Series: Misc DG2 enabling patches
URL : https://patchwork.freedesktop.org/series/99490/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
From: Stuart Summers
The driver is set currently to fail modprobe when GuC is disabled
(enable_guc=0) after GuC has been loaded on a previous modprobe.
For GuC deprivilege, the BIOS is setting the locked bit, so the
driver always considers the GuC to have been loaded and thus does
not support ena
Align the plane vma size to the stolem memory regions' min_page_size.
Signed-off-by: Ramalingam C
cc: Matthew Auld
cc: Chris P Wilson
---
drivers/gpu/drm/i915/display/intel_plane_initial.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/int
From: Bruce Chang
Whenever Full soft reset is required, reset all individual engines
first, and then do a full soft reset.
Signed-off-by: Bruce Chang
cc: Matt Roper
Cc: Rodrigo Vivi
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_reset.c | 9 +
1 file changed, 9 insert
On i915_selftest@live@gt_timelines, we create many contexts in loop and
create and submit request and then destoy contexts. Destroying the context
needs to disable scheduling, wait for G2H, deregister context and wait
for G2H to destroy each context. Idling of the gt has to wait for all
this to com
An indirect ctx wabb is implemented as per Wa_22011450934 to avoid rcs
restore hang during context restore of a preempted context in GPGPU mode
Signed-off-by: Ramalingam C
cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 28
drivers/gpu/drm/i915/i915_reg.h
Assorted DG2 enabling patches.
Bruce Chang (1):
drm/i915/dg2: Add Wa_22011100796
Ramalingam C (3):
drm/i915/dg2: Add Wa_22011450934
drm/i915: align the plane_vma to min_page_size of stolen mem
drm/i915: More gt idling time with guc submission
Stuart Summers (1):
drm/i915/guc: Allow use
== Series Details ==
Series: drm/i915/dg2: s/engine->i915/i915/ for engine workarounds
URL : https://patchwork.freedesktop.org/series/99484/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11159 -> Patchwork_22139
Summary
---
== Series Details ==
Series: drm/i915: Allow dead vm to unbind vma's without lock.
URL : https://patchwork.freedesktop.org/series/99471/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11157_full -> Patchwork_22135_full
Summa
On Fri, Jan 28, 2022 at 09:34:28AM +, Tvrtko Ursulin wrote:
John,
What CI results were used to merge this particular single patch?
Unless I am not seeing it, it was always set in pair with something
else.
First with "drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP
for referenc
rcs_engine_wa_init() has a local 'i915' variable; we should use that
rather than 'engine->i915' for consistency with how we handle other
platforms.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 30 ++---
1 file changed,
On Fri, Jan 28, 2022 at 12:32:14AM -0800, Dhanavanthri, Swathi wrote:
> Reviewed-by: Swathi Dhanavanthri
Applied to drm-intel-gt-next. Thanks for the review.
I'll follow up with a patch to make that entire function use the local
'i915' variable rather than 'engine->i915' consistently throughout
Facepalming myself - yes you're right - that's an easy fix...
move the device specific ext-list into the guc_capture_priv structure
which is allocated per gt.
Thanks Jani.
...alan
On Thu, 2022-01-27 at 11:30 +0200, Jani Nikula wrote:
> On Wed, 26 Jan 2022, "Teres Alexis, Alan Previn"
> wrote
Hi,
On 19/01/2022 23:12, Vivek Kasireddy wrote:
On platforms capable of allowing 8K (7680 x 4320) modes, pinning 2 or
more framebuffers/scanout buffers results in only one that is mappable/
fenceable. Therefore, pageflipping between these 2 FBs where only one
is mappable/fenceable creates late
Op 28-01-2022 om 16:49 schreef Tvrtko Ursulin:
>
>
> On 28/01/2022 15:21, Matt Roper wrote:
>> On Fri, Jan 28, 2022 at 08:44:17AM +, Patchwork wrote:
>>> == Series Details ==
>>>
>>> Series: Second round of i915_reg.h splitting (rev3)
>>> URL : https://patchwork.freedesktop.org/series/99079/
On 28/01/2022 15:21, Matt Roper wrote:
On Fri, Jan 28, 2022 at 08:44:17AM +, Patchwork wrote:
== Series Details ==
Series: Second round of i915_reg.h splitting (rev3)
URL : https://patchwork.freedesktop.org/series/99079/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_
On Fri, Jan 28, 2022 at 08:44:17AM +, Patchwork wrote:
> == Series Details ==
>
> Series: Second round of i915_reg.h splitting (rev3)
> URL : https://patchwork.freedesktop.org/series/99079/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11154_full -> Patchwork_221
== Series Details ==
Series: drm/i915: M/N cleanup (rev4)
URL : https://patchwork.freedesktop.org/series/99409/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11158 -> Patchwork_22138
Summary
---
**SUCCESS**
No reg
On Thu, 27 Jan 2022 at 14:11, Arunpravin
wrote:
>
> - Remove drm_mm references and replace with drm buddy functionalities
> - Add res cursor support for drm buddy
>
> v2(Matthew Auld):
> - replace spinlock with mutex as we call kmem_cache_zalloc
> (..., GFP_KERNEL) in drm_buddy_alloc() funct
== Series Details ==
Series: drm/i915: M/N cleanup (rev4)
URL : https://patchwork.freedesktop.org/series/99409/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Fri, 2022-01-28 at 09:36 +0300, Dan Carpenter wrote:
> On Fri, Jan 28, 2022 at 07:20:02AM +0100, Thomas Hellström wrote:
> > On Thu, 2022-01-27 at 17:26 -0500, Rodrigo Vivi wrote:
> > > On Thu, Jan 27, 2022 at 11:51:15AM +0300, Dan Carpenter wrote:
> > > > This "ret" declaration shadows an exist
== Series Details ==
Series: drm/i915: Refactor the display power domain mappings
URL : https://patchwork.freedesktop.org/series/99476/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11158 -> Patchwork_22137
Summary
---
== Series Details ==
Series: drm/i915: Refactor the display power domain mappings
URL : https://patchwork.freedesktop.org/series/99476/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Refactor the display power domain mappings
URL : https://patchwork.freedesktop.org/series/99476/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b526cacc94dc drm/i915: Fix the VDSC_PW2 power domain enum value
2f95deec7aed drm/i915: Unexport
Use the shortest descriptive name for all power wells for simplicity and
to use the same name for the same type of power wells on multiple
platforms.
Signed-off-by: Imre Deak
---
.../i915/display/intel_display_power_map.c| 254 +-
1 file changed, 127 insertions(+), 127 deleti
The spec calls the XELPD_D/E ports just D/E, the platform prefix in the
domain names was only needed by the port->domain mapping relying on
matching enum values for the whole port/domain range (and the
corresponding aliasing between the platform specific domain enums).
Since a previous patch we can
The DDI and AUX domain -> power well mappings are identical for a few
platforms/power well instances, reuse the mappings of earlier platforms
for these removing the duplicate mapping of new platforms.
Signed-off-by: Imre Deak
---
.../i915/display/intel_display_power_map.c| 89 +++
Atm the port -> DDI and AUX power domain mapping is specified by relying
on the aliasing of the platform specific intel_display_power_domain enum
values. For instance D12+ platforms refer to the 'D' port and power
domain instances, which doesn't match the bspec terminology, on these
platforms the c
Simplify the definition of DG1 power wells by reusing the identical
RKL DDI/AUX descriptors.
This reorders the DG1 DDI/AUX vs. PW4/5 power wells, but this shouldn't
make a difference (it is the order on RKL and the DDI/AUX power wells
don't have a dependency on PW4/5).
Signed-off-by: Imre Deak
-
All the port specific AUX/DDI_IO power wells share the same power well
ops struct and flags, so we can save some space and simplify the
definition of these by listing for all such power wells only the params
specific to them (name, domains, power well register index, id). Move
these params to a new
The next patch converts the i915_power_well_desc::domain mask from a u64
mask to a bitmap. I didn't find a reasonably simple way to initialize
bitmaps statically, so prepare for the next patch here by converting the
masks to a list and initing the masks from these lists during module
loading.
Sign
Instead of the skip_mask special casing of the ADL-S power well
descriptors, add a power well descriptor list for ADL-S as well reusing
the TGL descriptors, w/o the TC-cold power well. ADL-S doesn't have
TypeC PHYs, so a better way would be having ADL-S specific AUX
descriptors, but I left changing
Some power wells - like always-on and skl+/icl+ PW_1 - with the same
name, domain list, flags, ops are used by multiple platforms, so allow
platforms to reuse the descriptors of such power wells.
This change also lets the follow up patches to simplify the DG1/RKL
power well definitions, and remove
Make all power domain names end with the pipe/port instance for
consistency.
No functional changes.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/icl_dsi.c| 8 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 34 +-
The spec calls the ICL TBT AUX power well instances TBT1-4 (similarly to
all later platforms), align the power domain names with the spec.
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_display_power.h| 4 ---
.../i915/display/intel_display_power_map.c| 26 +++
To remove the aliasing of the power domain enum values in a follow-up
patch in this patchset (requiring a bigger mask) and allow for defining
additional power domains in the future (at least some upcoming TypeC
changes requires this) convert the u64 i915_power_well_desc::domains
mask to a bitmap.
Aliasing the intel_display_power_domain enum values was required because
of the u64 power domain mask size limit. This makes the dmesg/debugfs
printouts of the domain names somewhat unclear, for instance domain
names for port D are shown on D12+ platforms where the corresponding
port is called TC1.
Move the i915_power_well_regs struct into i915_power_well_ops. Most of
the power wells use the same ops/regs combination, so this saves some
space and also simplifies the platform power domain->power well
definitions.
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_display_power.c| 2
Move the list of platform specific power domain -> power well
definitions to intel_display_power_map.c. While at it group the
platforms' power domain macros with the corresponding power well lists
and keep all the power domain lists in the same order (matching the enum
order).
No functional change
Save some space by grouping the HSW power well descriptor flags along
with other flags in one bitfield.
This change also lets simplifying the definition of power well
descriptors sharing the same flags in an upcoming patch.
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_display_power.c
The DG2 fixed delay duration is always 600usec, so save some space in
the power well descriptors by converting the parameter to a flag. While
at it also use a bitfield for both the always_on and fixed_enable_delay
flag.
This change also lets simplifying the definiton of power wells sharing
the sam
The for_each_power_well() macros are only used in intel_display_power.c,
so unexport them.
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_display_power.c| 20 +++
.../drm/i915/display/intel_display_power.h| 20 ---
2 files changed, 20 insertions(+
This patchset moves the per-platform display power domain->power well
mapping descriptors to a separate file and simplifies them by sharing
descriptor data among port power well instances and platforms where
possible.
The power well and domain names are also sanitized to match the actual
specifica
The POWER_DOMAIN_TRANSCODER() macro depends on the
POWER_DOMAIN_TRANSCODER_A/B .. DSI_A/C enum values to be consecutive,
move POWER_DOMAIN_TRANSCODER_VDSC_PW2 after these to ensure this. The
wrong order didn't cause a problem, since the DSI_A/C domains are in
always-on power wells on all relevant p
== Series Details ==
Series: drm/i915: M/N cleanup (rev3)
URL : https://patchwork.freedesktop.org/series/99409/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11157 -> Patchwork_22136
Summary
---
**FAILURE**
Seriou
Op 28-01-2022 om 12:02 schreef Thomas Hellström (Intel):
>
> On 1/28/22 09:57, Maarten Lankhorst wrote:
>> i915_gem_vm_close may take the lock, and we currently have no better way
>> of handling this. At least for now, allow a path in which holding vm->mutex
>> is sufficient. This is the case, beca
== Series Details ==
Series: drm/i915: M/N cleanup (rev3)
URL : https://patchwork.freedesktop.org/series/99409/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On 1/28/22 09:57, Maarten Lankhorst wrote:
i915_gem_vm_close may take the lock, and we currently have no better way
of handling this. At least for now, allow a path in which holding vm->mutex
is sufficient. This is the case, because the object destroy path will
forcefully take vm->mutex now.
S
== Series Details ==
Series: drm/i915: Allow dead vm to unbind vma's without lock.
URL : https://patchwork.freedesktop.org/series/99471/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11157 -> Patchwork_22135
Summary
---
From: Ville Syrjälä
When reprogramming M/N live on BDW+ we must write the LINK_N
register last as it's the one that arms the double buffered
register update for all the M/N registers. Document this so
that we don't accidentally break things.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i91
From: Ville Syrjälä
No point in special casing the check of dp_m2_n2 on pre-bdw platforms.
Either the transcoder has M2/N2 in which case the values should be
set to something sensible, or it doesn't in which case dp_m2_n2 is
always zeroed.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/
From: Ville Syrjälä
M2/N2 values are present for all ilk-ivb,vlv,chv (and hsw edp).
Make the code reflect that.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/in
From: Ville Syrjälä
No point in special casing the dp_m2_n2 dumping. Just do it always.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/d
From: Ville Syrjälä
Program the PCH transcoder M2/N2 values appropriately. We're
still missing a few things for PCH port DRRS but at least this
means we can do readout/state check for dp_m2_n2 unconditionally.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/g4x_dp.c | 3
From: Ville Syrjälä
Make life simpler by always programming DP M2/N2 with a consistent
value. This will lets use do state readout+chec unconditionally.
I was first going to just set M2/N2=M1/N1 but then it occurred
to me that it might interfere with fastboot on account of BIOS
likely leaving the
From: Ville Syrjälä
Pull the "can we do DRRS?" check into helper in order
to reduce the clutter in intel_drrs_compute_config().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_drrs.c | 31 ++-
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git
From: Ville Syrjälä
Currently we allow DRRS on IVB PCH ports, but we're missing a
few programming steps meaning it is guaranteed to not work.
And on HSW DRRS is not supported on anything but port A ever
as only transcoder EDP has the M2/N2 registers (though I'm
not sure if HSW ever has eDP on any
From: Ville Syrjälä
Follow the path laid out by hsw+ and extract helpers to configure
the cpu transcoder for earlier platforms as well.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 68 ++--
1 file changed, 35 insertions(+), 33 deletions(-)
di
From: Ville Syrjälä
Do the PCH transcoder M/N setup next to where all the other
PCH transcoder stuff is programmed. Matches the spec modeset
sequence better.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/g4x_dp.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 6
From: Ville Syrjälä
Let's do the cpu transcoder M/N setup next to where we program
most other cpu transcoder timings/etc.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +-
drivers/gpu/drm/i915/display/intel_display.c | 14 ++
drivers/gpu
From: Ville Syrjälä
Instead of passing in the whole crtc state let's pass in just
the bits of state we need. This will help with the DRRS code
which shouldn't really be accessing the atomic state stuff directly
as it gets called outside the normal atomic flows.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
As with intel_cpu_transcoder_set_m_n() let's split the readout
counterpart into explicit M1/N1 vs. M2/N2 variants as well.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/g4x_dp.c | 12 ---
drivers/gpu/drm/i915/display/intel_ddi.c | 12 +++
From: Ville Syrjälä
Make things a bit more explicit by splitting
intel_cpu_transcoder_set_m_n() into separate variants for M1/N1 vs.
M2/N2. Makes the DRRS M/N programming at least more obvious.
Note that for the MST and DRRS cases we don't need to call the
M2/N2 variant at all since the transcod
From: Ville Syrjälä
Get rid of the entirely pointless ilk_get_fdi_m_n_config() wrapper
and just call the CPU transcoder function directly.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 7 ---
drivers/gpu/drm/i915/display/intel_display.h | 2 --
dri
From: Ville Syrjälä
As with intel_dp_set_m_n() let's get rid of the wrapper and just
call the relevant PCH vs. CPU transcoder functions directly.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/g4x_dp.c| 14 +++-
drivers/gpu/drm/i915/display/intel_ddi.c | 9 +
From: Ville Syrjälä
I want to make a clean split betwen the CPU vs. PCH transcoder
programming. To that end eliminate intel_dp_set_m_n() and just
call the individual CPU/PCH transcoder functions directly.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
d
From: Ville Syrjälä
Rehashed version of the M/N cleanup after Jani (rightly)
complained about the legibility of some of the patches in
the v1 series. These are chunked to a finer pulp, some got
revised a bit, and I left out a few of the FDI related
things for now. I'll revisit the PCH port/FDI to
== Series Details ==
Series: drm/i915/dg2: Add Wa_14015227452 (rev2)
URL : https://patchwork.freedesktop.org/series/99446/
State : failure
== Summary ==
Applying: drm/i915/dg2: Add Wa_14015227452
error: patch failed: drivers/gpu/drm/i915/gt/intel_workarounds.c:2045
error: drivers/gpu/drm/i915/
On Thu, 27 Jan 2022 at 23:41, Michael Cheng wrote:
>
> Re-work invalidate_csb_entries to use drm_clflush_virt_range. This will
> prevent compiler errors when building for non-x86 architectures.
>
> Signed-off-by: Michael Cheng
> ---
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 4 ++--
On Thu, 27 Jan 2022 at 23:41, Michael Cheng wrote:
>
> Re-work intel_write_status_page to use drm_clflush_virt_range. This
> will prevent compiler errors when building for non-x86 architectures.
>
> Signed-off-by: Michael Cheng
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h | 13 -
>
John,
What CI results were used to merge this particular single patch? Unless
I am not seeing it, it was always set in pair with something else.
First with "drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for
reference", which was merged earlier in the week and it had a standalone
i915_gem_vm_close may take the lock, and we currently have no better way
of handling this. At least for now, allow a path in which holding vm->mutex
is sufficient. This is the case, because the object destroy path will
forcefully take vm->mutex now.
Signed-off-by: Maarten Lankhorst
---
drivers/g
Op 27-01-2022 om 13:45 schreef Thomas Hellström:
>
> On 1/27/22 13:38, Maarten Lankhorst wrote:
>> Op 27-01-2022 om 13:09 schreef Thomas Hellström:
>>> On 1/27/22 13:05, Thomas Hellström wrote:
> The bug on vm_close is a separate bug, and would probably best be
> fixed in a separate patch.
On 27/01/2022 19:48, Matt Roper wrote:
Note that the bspec doesn't list the bit we're programming here (bit 11)
as being present on DG2, but we've confirmed with the hardware team that
this is a documentation mistake and the bit does indeed exist on all
Xe_HP-based platforms.
Signed-off-by: Ma
== Series Details ==
Series: Second round of i915_reg.h splitting (rev3)
URL : https://patchwork.freedesktop.org/series/99079/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11154_full -> Patchwork_22133_full
Summary
---
Hi
Am 28.01.22 um 09:15 schrieb Thomas Zimmermann:
...
While with the construct below
other_map;
...
other_map = INITIALIZER()
I can rely on the compiler complaining about uninitialized var. And
in most of the cases I can just have this single line in the begginin
Reviewed-by: Swathi Dhanavanthri
-Original Message-
From: Intel-gfx On Behalf Of Matt
Roper
Sent: Thursday, January 27, 2022 11:49 AM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915/dg2: Add Wa_14015227452
Note that the bspec doesn't list the bit we're program
Hi
Am 27.01.22 um 17:34 schrieb Lucas De Marchi:
On Thu, Jan 27, 2022 at 03:26:43PM +0100, Thomas Zimmermann wrote:
Hi
Am 26.01.22 um 21:36 schrieb Lucas De Marchi:
In certain situations it's useful to be able to read or write to an
offset that is calculated by having the memory layout given
Hi
Am 27.01.22 um 16:59 schrieb Lucas De Marchi:
On Thu, Jan 27, 2022 at 03:33:12PM +0100, Thomas Zimmermann wrote:
Am 26.01.22 um 21:36 schrieb Lucas De Marchi:
When dma_buf_map struct is passed around, it's useful to be able to
initialize a second map that takes care of reading/writing to
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