The DG2 fixed delay duration is always 600usec, so save some space in
the power well descriptors by converting the parameter to a flag. While
at it also use a bitfield for both the always_on and fixed_enable_delay
flag.
This change also lets simplifying the definiton of power wells sharing
the same flags in an upcoming patch.
Signed-off-by: Imre Deak <imre.d...@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++---
.../i915/display/intel_display_power_internal.h | 14 +++++++-------
.../gpu/drm/i915/display/intel_display_power_map.c | 10 +++++-----
3 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 2ec9c7bd65640..ceac9c1a7693c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -265,15 +265,14 @@ static void hsw_wait_for_power_well_enable(struct
drm_i915_private *dev_priv,
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
int pw_idx = power_well->desc->hsw.idx;
- int enable_delay = power_well->desc->hsw.fixed_enable_delay;
/*
* For some power wells we're not supposed to watch the status bit for
* an ack, but rather just wait a fixed amount of time and then
* proceed. This is only used on DG2.
*/
- if (IS_DG2(dev_priv) && enable_delay) {
- usleep_range(enable_delay, 2 * enable_delay);
+ if (IS_DG2(dev_priv) && power_well->desc->fixed_enable_delay) {
+ usleep_range(600, 1200);
return;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_internal.h
b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
index 3fc7c7d0bc9e9..540668a1708b7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_internal.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
@@ -16,8 +16,14 @@ struct i915_power_well_regs;
/* Power well structure for haswell */
struct i915_power_well_desc {
const char *name;
- bool always_on;
u64 domains;
+ u8 always_on:1;
+ /*
+ * Instead of waiting for the status bit to ack enables,
+ * just wait a specific amount of time and then consider
+ * the well enabled.
+ */
+ u8 fixed_enable_delay:1;
/* unique identifier for this power well */
enum i915_power_well_id id;
/*
@@ -43,12 +49,6 @@ struct i915_power_well_desc {
u8 idx;
/* Mask of pipes whose IRQ logic is backed by the pw */
u8 irq_pipe_mask;
- /*
- * Instead of waiting for the status bit to ack enables,
- * just wait a specific amount of time and then consider
- * the well enabled.
- */
- u16 fixed_enable_delay;
/* The pw is backing the VGA functionality */
bool has_vga:1;
bool has_fuses:1;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c
b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index e8732f6e85098..5daa20168b1e5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -2057,37 +2057,37 @@ static const struct i915_power_well_desc
xelpd_power_wells[] = {
.name = "AUX A",
.domains = ICL_AUX_A_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- .hsw.fixed_enable_delay = 600,
},
}, {
.name = "AUX B",
.domains = ICL_AUX_B_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- .hsw.fixed_enable_delay = 600,
},
}, {
.name = "AUX C",
.domains = TGL_AUX_C_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
- .hsw.fixed_enable_delay = 600,
},
}, {
.name = "AUX D_XELPD",
.domains = XELPD_AUX_IO_D_XELPD_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = XELPD_PW_CTL_IDX_AUX_D,
- .hsw.fixed_enable_delay = 600,
},
}, {
.name = "AUX E_XELPD",
@@ -2101,10 +2101,10 @@ static const struct i915_power_well_desc
xelpd_power_wells[] = {
.name = "AUX USBC1",
.domains = XELPD_AUX_IO_USBC1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- .hsw.fixed_enable_delay = 600,
},
}, {
.name = "AUX USBC2",
--
2.27.0
