Make all power domain names end with the pipe/port instance for
consistency.
No functional changes.
Signed-off-by: Imre Deak <imre.d...@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 8 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 34 +-
.../drm/i915/display/intel_display_power.h | 66 ++--
.../i915/display/intel_display_power_map.c | 300 +++++++++---------
5 files changed, 205 insertions(+), 205 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 2d5bb9195b20f..990671e7aba21 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -398,8 +398,8 @@ static void get_dsi_io_power_domains(struct
drm_i915_private *dev_priv,
intel_dsi->io_wakeref[port] =
intel_display_power_get(dev_priv,
port == PORT_A ?
- POWER_DOMAIN_PORT_DDI_A_IO :
- POWER_DOMAIN_PORT_DDI_B_IO);
+ POWER_DOMAIN_PORT_DDI_IO_A :
+ POWER_DOMAIN_PORT_DDI_IO_B);
}
}
@@ -1425,8 +1425,8 @@ static void gen11_dsi_disable_io_power(struct
intel_encoder *encoder)
wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
intel_display_power_put(dev_priv,
port == PORT_A ?
- POWER_DOMAIN_PORT_DDI_A_IO :
- POWER_DOMAIN_PORT_DDI_B_IO,
+ POWER_DOMAIN_PORT_DDI_IO_A :
+ POWER_DOMAIN_PORT_DDI_IO_B,
wakeref);
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 5d1f7d6218c51..530032f3bb2c2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4475,7 +4475,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
}
drm_WARN_ON(&dev_priv->drm, port > PORT_I);
- dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
+ dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_IO_A +
port - PORT_A;
if (init_dp) {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 91add3d85151c..3094cfc668c81 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2289,23 +2289,23 @@ enum intel_display_power_domain
intel_port_to_power_domain(enum port port)
{
switch (port) {
case PORT_A:
- return POWER_DOMAIN_PORT_DDI_A_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_A;
case PORT_B:
- return POWER_DOMAIN_PORT_DDI_B_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_B;
case PORT_C:
- return POWER_DOMAIN_PORT_DDI_C_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_C;
case PORT_D:
- return POWER_DOMAIN_PORT_DDI_D_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_D;
case PORT_E:
- return POWER_DOMAIN_PORT_DDI_E_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_E;
case PORT_F:
- return POWER_DOMAIN_PORT_DDI_F_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_F;
case PORT_G:
- return POWER_DOMAIN_PORT_DDI_G_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_G;
case PORT_H:
- return POWER_DOMAIN_PORT_DDI_H_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_H;
case PORT_I:
- return POWER_DOMAIN_PORT_DDI_I_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_I;
default:
MISSING_CASE(port);
return POWER_DOMAIN_PORT_OTHER;
@@ -2318,22 +2318,22 @@ intel_aux_power_domain(struct intel_digital_port
*dig_port)
if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
switch (dig_port->aux_ch) {
case AUX_CH_C:
- return POWER_DOMAIN_AUX_C_TBT;
+ return POWER_DOMAIN_AUX_TBT_C;
case AUX_CH_D:
- return POWER_DOMAIN_AUX_D_TBT;
+ return POWER_DOMAIN_AUX_TBT_D;
case AUX_CH_E:
- return POWER_DOMAIN_AUX_E_TBT;
+ return POWER_DOMAIN_AUX_TBT_E;
case AUX_CH_F:
- return POWER_DOMAIN_AUX_F_TBT;
+ return POWER_DOMAIN_AUX_TBT_F;
case AUX_CH_G:
- return POWER_DOMAIN_AUX_G_TBT;
+ return POWER_DOMAIN_AUX_TBT_G;
case AUX_CH_H:
- return POWER_DOMAIN_AUX_H_TBT;
+ return POWER_DOMAIN_AUX_TBT_H;
case AUX_CH_I:
- return POWER_DOMAIN_AUX_I_TBT;
+ return POWER_DOMAIN_AUX_TBT_I;
default:
MISSING_CASE(dig_port->aux_ch);
- return POWER_DOMAIN_AUX_C_TBT;
+ return POWER_DOMAIN_AUX_TBT_C;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index a0e68ae691021..c3232809b95f9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -26,10 +26,10 @@ enum intel_display_power_domain {
POWER_DOMAIN_PIPE_B,
POWER_DOMAIN_PIPE_C,
POWER_DOMAIN_PIPE_D,
- POWER_DOMAIN_PIPE_A_PANEL_FITTER,
- POWER_DOMAIN_PIPE_B_PANEL_FITTER,
- POWER_DOMAIN_PIPE_C_PANEL_FITTER,
- POWER_DOMAIN_PIPE_D_PANEL_FITTER,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_A,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_D,
POWER_DOMAIN_TRANSCODER_A,
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
@@ -41,17 +41,17 @@ enum intel_display_power_domain {
/* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
POWER_DOMAIN_TRANSCODER_VDSC_PW2,
- POWER_DOMAIN_PORT_DDI_A_LANES,
- POWER_DOMAIN_PORT_DDI_B_LANES,
- POWER_DOMAIN_PORT_DDI_C_LANES,
- POWER_DOMAIN_PORT_DDI_D_LANES,
- POWER_DOMAIN_PORT_DDI_E_LANES,
- POWER_DOMAIN_PORT_DDI_F_LANES,
- POWER_DOMAIN_PORT_DDI_G_LANES,
- POWER_DOMAIN_PORT_DDI_H_LANES,
- POWER_DOMAIN_PORT_DDI_I_LANES,
+ POWER_DOMAIN_PORT_DDI_LANES_A,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_PORT_DDI_LANES_D,
+ POWER_DOMAIN_PORT_DDI_LANES_E,
+ POWER_DOMAIN_PORT_DDI_LANES_F,
+ POWER_DOMAIN_PORT_DDI_LANES_G,
+ POWER_DOMAIN_PORT_DDI_LANES_H,
+ POWER_DOMAIN_PORT_DDI_LANES_I,
- POWER_DOMAIN_PORT_DDI_LANES_TC1 = POWER_DOMAIN_PORT_DDI_D_LANES, /*
tgl+ */
+ POWER_DOMAIN_PORT_DDI_LANES_TC1 = POWER_DOMAIN_PORT_DDI_LANES_D, /*
tgl+ */
POWER_DOMAIN_PORT_DDI_LANES_TC2,
POWER_DOMAIN_PORT_DDI_LANES_TC3,
POWER_DOMAIN_PORT_DDI_LANES_TC4,
@@ -61,17 +61,17 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_LANES_D_XELPD = POWER_DOMAIN_PORT_DDI_LANES_TC5,
/* XELPD */
POWER_DOMAIN_PORT_DDI_LANES_E_XELPD,
- POWER_DOMAIN_PORT_DDI_A_IO,
- POWER_DOMAIN_PORT_DDI_B_IO,
- POWER_DOMAIN_PORT_DDI_C_IO,
- POWER_DOMAIN_PORT_DDI_D_IO,
- POWER_DOMAIN_PORT_DDI_E_IO,
- POWER_DOMAIN_PORT_DDI_F_IO,
- POWER_DOMAIN_PORT_DDI_G_IO,
- POWER_DOMAIN_PORT_DDI_H_IO,
- POWER_DOMAIN_PORT_DDI_I_IO,
+ POWER_DOMAIN_PORT_DDI_IO_A,
+ POWER_DOMAIN_PORT_DDI_IO_B,
+ POWER_DOMAIN_PORT_DDI_IO_C,
+ POWER_DOMAIN_PORT_DDI_IO_D,
+ POWER_DOMAIN_PORT_DDI_IO_E,
+ POWER_DOMAIN_PORT_DDI_IO_F,
+ POWER_DOMAIN_PORT_DDI_IO_G,
+ POWER_DOMAIN_PORT_DDI_IO_H,
+ POWER_DOMAIN_PORT_DDI_IO_I,
- POWER_DOMAIN_PORT_DDI_IO_TC1 = POWER_DOMAIN_PORT_DDI_D_IO, /* tgl+ */
+ POWER_DOMAIN_PORT_DDI_IO_TC1 = POWER_DOMAIN_PORT_DDI_IO_D, /* tgl+ */
POWER_DOMAIN_PORT_DDI_IO_TC2,
POWER_DOMAIN_PORT_DDI_IO_TC3,
POWER_DOMAIN_PORT_DDI_IO_TC4,
@@ -108,15 +108,15 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_E_XELPD,
POWER_DOMAIN_AUX_IO_A,
- POWER_DOMAIN_AUX_C_TBT,
- POWER_DOMAIN_AUX_D_TBT,
- POWER_DOMAIN_AUX_E_TBT,
- POWER_DOMAIN_AUX_F_TBT,
- POWER_DOMAIN_AUX_G_TBT,
- POWER_DOMAIN_AUX_H_TBT,
- POWER_DOMAIN_AUX_I_TBT,
+ POWER_DOMAIN_AUX_TBT_C,
+ POWER_DOMAIN_AUX_TBT_D,
+ POWER_DOMAIN_AUX_TBT_E,
+ POWER_DOMAIN_AUX_TBT_F,
+ POWER_DOMAIN_AUX_TBT_G,
+ POWER_DOMAIN_AUX_TBT_H,
+ POWER_DOMAIN_AUX_TBT_I,
- POWER_DOMAIN_AUX_TBT1 = POWER_DOMAIN_AUX_D_TBT, /* tgl+ */
+ POWER_DOMAIN_AUX_TBT1 = POWER_DOMAIN_AUX_TBT_D, /* tgl+ */
POWER_DOMAIN_AUX_TBT2,
POWER_DOMAIN_AUX_TBT3,
POWER_DOMAIN_AUX_TBT4,
@@ -159,7 +159,7 @@ enum i915_power_well_id {
#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
- ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
+ ((pipe) + POWER_DOMAIN_PIPE_PANEL_FITTER_A)
#define POWER_DOMAIN_TRANSCODER(tran) \
((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
(tran) + POWER_DOMAIN_TRANSCODER_A)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c
b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 92bf6337274eb..30c9d94b55929 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -26,14 +26,14 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
return "PIPE_C";
case POWER_DOMAIN_PIPE_D:
return "PIPE_D";
- case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
- return "PIPE_A_PANEL_FITTER";
- case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
- return "PIPE_B_PANEL_FITTER";
- case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
- return "PIPE_C_PANEL_FITTER";
- case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
- return "PIPE_D_PANEL_FITTER";
+ case POWER_DOMAIN_PIPE_PANEL_FITTER_A:
+ return "PIPE_PANEL_FITTER_A";
+ case POWER_DOMAIN_PIPE_PANEL_FITTER_B:
+ return "PIPE_PANEL_FITTER_B";
+ case POWER_DOMAIN_PIPE_PANEL_FITTER_C:
+ return "PIPE_PANEL_FITTER_C";
+ case POWER_DOMAIN_PIPE_PANEL_FITTER_D:
+ return "PIPE_PANEL_FITTER_D";
case POWER_DOMAIN_TRANSCODER_A:
return "TRANSCODER_A";
case POWER_DOMAIN_TRANSCODER_B:
@@ -50,42 +50,42 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
return "TRANSCODER_DSI_C";
case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
return "TRANSCODER_VDSC_PW2";
- case POWER_DOMAIN_PORT_DDI_A_LANES:
- return "PORT_DDI_A_LANES";
- case POWER_DOMAIN_PORT_DDI_B_LANES:
- return "PORT_DDI_B_LANES";
- case POWER_DOMAIN_PORT_DDI_C_LANES:
- return "PORT_DDI_C_LANES";
- case POWER_DOMAIN_PORT_DDI_D_LANES:
- return "PORT_DDI_D_LANES";
- case POWER_DOMAIN_PORT_DDI_E_LANES:
- return "PORT_DDI_E_LANES";
- case POWER_DOMAIN_PORT_DDI_F_LANES:
- return "PORT_DDI_F_LANES";
- case POWER_DOMAIN_PORT_DDI_G_LANES:
- return "PORT_DDI_G_LANES";
- case POWER_DOMAIN_PORT_DDI_H_LANES:
- return "PORT_DDI_H_LANES";
- case POWER_DOMAIN_PORT_DDI_I_LANES:
- return "PORT_DDI_I_LANES";
- case POWER_DOMAIN_PORT_DDI_A_IO:
- return "PORT_DDI_A_IO";
- case POWER_DOMAIN_PORT_DDI_B_IO:
- return "PORT_DDI_B_IO";
- case POWER_DOMAIN_PORT_DDI_C_IO:
- return "PORT_DDI_C_IO";
- case POWER_DOMAIN_PORT_DDI_D_IO:
- return "PORT_DDI_D_IO";
- case POWER_DOMAIN_PORT_DDI_E_IO:
- return "PORT_DDI_E_IO";
- case POWER_DOMAIN_PORT_DDI_F_IO:
- return "PORT_DDI_F_IO";
- case POWER_DOMAIN_PORT_DDI_G_IO:
- return "PORT_DDI_G_IO";
- case POWER_DOMAIN_PORT_DDI_H_IO:
- return "PORT_DDI_H_IO";
- case POWER_DOMAIN_PORT_DDI_I_IO:
- return "PORT_DDI_I_IO";
+ case POWER_DOMAIN_PORT_DDI_LANES_A:
+ return "PORT_DDI_LANES_A";
+ case POWER_DOMAIN_PORT_DDI_LANES_B:
+ return "PORT_DDI_LANES_B";
+ case POWER_DOMAIN_PORT_DDI_LANES_C:
+ return "PORT_DDI_LANES_C";
+ case POWER_DOMAIN_PORT_DDI_LANES_D:
+ return "PORT_DDI_LANES_D";
+ case POWER_DOMAIN_PORT_DDI_LANES_E:
+ return "PORT_DDI_LANES_E";
+ case POWER_DOMAIN_PORT_DDI_LANES_F:
+ return "PORT_DDI_LANES_F";
+ case POWER_DOMAIN_PORT_DDI_LANES_G:
+ return "PORT_DDI_LANES_G";
+ case POWER_DOMAIN_PORT_DDI_LANES_H:
+ return "PORT_DDI_LANES_H";
+ case POWER_DOMAIN_PORT_DDI_LANES_I:
+ return "PORT_DDI_LANES_I";
+ case POWER_DOMAIN_PORT_DDI_IO_A:
+ return "PORT_DDI_IO_A";
+ case POWER_DOMAIN_PORT_DDI_IO_B:
+ return "PORT_DDI_IO_B";
+ case POWER_DOMAIN_PORT_DDI_IO_C:
+ return "PORT_DDI_IO_C";
+ case POWER_DOMAIN_PORT_DDI_IO_D:
+ return "PORT_DDI_IO_D";
+ case POWER_DOMAIN_PORT_DDI_IO_E:
+ return "PORT_DDI_IO_E";
+ case POWER_DOMAIN_PORT_DDI_IO_F:
+ return "PORT_DDI_IO_F";
+ case POWER_DOMAIN_PORT_DDI_IO_G:
+ return "PORT_DDI_IO_G";
+ case POWER_DOMAIN_PORT_DDI_IO_H:
+ return "PORT_DDI_IO_H";
+ case POWER_DOMAIN_PORT_DDI_IO_I:
+ return "PORT_DDI_IO_I";
case POWER_DOMAIN_PORT_DSI:
return "PORT_DSI";
case POWER_DOMAIN_PORT_CRT:
@@ -118,20 +118,20 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
return "AUX_I";
case POWER_DOMAIN_AUX_IO_A:
return "AUX_IO_A";
- case POWER_DOMAIN_AUX_C_TBT:
- return "AUX_C_TBT";
- case POWER_DOMAIN_AUX_D_TBT:
- return "AUX_D_TBT";
- case POWER_DOMAIN_AUX_E_TBT:
- return "AUX_E_TBT";
- case POWER_DOMAIN_AUX_F_TBT:
- return "AUX_F_TBT";
- case POWER_DOMAIN_AUX_G_TBT:
- return "AUX_G_TBT";
- case POWER_DOMAIN_AUX_H_TBT:
- return "AUX_H_TBT";
- case POWER_DOMAIN_AUX_I_TBT:
- return "AUX_I_TBT";
+ case POWER_DOMAIN_AUX_TBT_C:
+ return "AUX_TBT_C";
+ case POWER_DOMAIN_AUX_TBT_D:
+ return "AUX_TBT_D";
+ case POWER_DOMAIN_AUX_TBT_E:
+ return "AUX_TBT_E";
+ case POWER_DOMAIN_AUX_TBT_F:
+ return "AUX_TBT_F";
+ case POWER_DOMAIN_AUX_TBT_G:
+ return "AUX_TBT_G";
+ case POWER_DOMAIN_AUX_TBT_H:
+ return "AUX_TBT_H";
+ case POWER_DOMAIN_AUX_TBT_I:
+ return "AUX_TBT_I";
case POWER_DOMAIN_GMBUS:
return "GMBUS";
case POWER_DOMAIN_INIT:
@@ -163,8 +163,8 @@ static const struct i915_power_well_desc
i9xx_always_on_power_well[] = {
#define I830_PIPES_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_A) | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -187,15 +187,15 @@ static const struct i915_power_well_desc
i830_power_wells[] = {
#define HSW_DISPLAY_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
@@ -224,14 +224,14 @@ static const struct i915_power_well_desc
hsw_power_wells[] = {
#define BDW_DISPLAY_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
@@ -262,12 +262,12 @@ static const struct i915_power_well_desc
bdw_power_wells[] = {
BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
BIT_ULL(POWER_DOMAIN_PIPE_A) | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
@@ -279,30 +279,30 @@ static const struct i915_power_well_desc
bdw_power_wells[] = {
BIT_ULL(POWER_DOMAIN_INIT))
#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -381,15 +381,15 @@ static const struct i915_power_well_desc
vlv_power_wells[] = {
BIT_ULL(POWER_DOMAIN_PIPE_A) | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
@@ -401,14 +401,14 @@ static const struct i915_power_well_desc
vlv_power_wells[] = {
BIT_ULL(POWER_DOMAIN_INIT))
#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
BIT_ULL(POWER_DOMAIN_AUX_D) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -451,15 +451,15 @@ static const struct i915_power_well_desc
chv_power_wells[] = {
#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
@@ -476,20 +476,20 @@ static const struct i915_power_well_desc
chv_power_wells[] = {
BIT_ULL(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D) | \
BIT_ULL(POWER_DOMAIN_INIT))
static const struct i915_power_well_desc skl_power_wells[] = {
@@ -574,13 +574,13 @@ static const struct i915_power_well_desc
skl_power_wells[] = {
#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
@@ -597,13 +597,13 @@ static const struct i915_power_well_desc
skl_power_wells[] = {
BIT_ULL(POWER_DOMAIN_INIT))
#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_A) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -664,13 +664,13 @@ static const struct i915_power_well_desc
bxt_power_wells[] = {
#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
@@ -686,22 +686,22 @@ static const struct i915_power_well_desc
bxt_power_wells[] = {
BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)
-#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)
-#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)
+#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A)
+#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B)
+#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C)
#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_A) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -843,22 +843,22 @@ static const struct i915_power_well_desc
glk_power_wells[] = {
*/
#define ICL_PW_4_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
/* VDSC/joining */
#define ICL_PW_3_POWER_DOMAINS ( \
ICL_PW_4_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_F) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
@@ -867,10 +867,10 @@ static const struct i915_power_well_desc
glk_power_wells[] = {
BIT_ULL(POWER_DOMAIN_AUX_D) | \
BIT_ULL(POWER_DOMAIN_AUX_E) | \
BIT_ULL(POWER_DOMAIN_AUX_F) | \
- BIT_ULL(POWER_DOMAIN_AUX_C_TBT) | \
- BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
- BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
- BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT_C) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT_D) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT_E) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT_F) | \
BIT_ULL(POWER_DOMAIN_INIT))
/*
* - transcoder WD
@@ -892,12 +892,12 @@ static const struct i915_power_well_desc
glk_power_wells[] = {
BIT_ULL(POWER_DOMAIN_DC_OFF) | \
BIT_ULL(POWER_DOMAIN_INIT))
-#define ICL_DDI_IO_A_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)
-#define ICL_DDI_IO_B_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)
-#define ICL_DDI_IO_C_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)
-#define ICL_DDI_IO_D_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO)
-#define ICL_DDI_IO_E_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO)
-#define ICL_DDI_IO_F_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO)
+#define ICL_DDI_IO_A_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A)
+#define ICL_DDI_IO_B_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B)
+#define ICL_DDI_IO_C_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C)
+#define ICL_DDI_IO_D_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D)
+#define ICL_DDI_IO_E_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E)
+#define ICL_DDI_IO_F_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_F)
#define ICL_AUX_A_IO_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
@@ -908,10 +908,10 @@ static const struct i915_power_well_desc
glk_power_wells[] = {
#define ICL_AUX_D_TC2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D)
#define ICL_AUX_E_TC3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E)
#define ICL_AUX_F_TC4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_F)
-#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_AUX_C_TBT)
-#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_AUX_D_TBT)
-#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_AUX_E_TBT)
-#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_AUX_F_TBT)
+#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_AUX_TBT_C)
+#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_AUX_TBT_D)
+#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_AUX_TBT_E)
+#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_AUX_TBT_F)
static const struct i915_power_well_desc icl_power_wells[] = {
{
@@ -1107,21 +1107,21 @@ static const struct i915_power_well_desc
icl_power_wells[] = {
#define TGL_PW_5_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_D) | \
- BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_D) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define TGL_PW_4_POWER_DOMAINS ( \
TGL_PW_5_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define TGL_PW_3_POWER_DOMAINS ( \
TGL_PW_4_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
@@ -1478,14 +1478,14 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
#define RKL_PW_4_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define RKL_PW_3_POWER_DOMAINS ( \
RKL_PW_4_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
@@ -1641,7 +1641,7 @@ static const struct i915_power_well_desc
rkl_power_wells[] = {
#define DG1_PW_3_POWER_DOMAINS ( \
TGL_PW_4_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
@@ -1816,32 +1816,32 @@ static const struct i915_power_well_desc
dg1_power_wells[] = {
#define XELPD_PW_D_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_D) | \
- BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_D) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define XELPD_PW_C_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define XELPD_PW_B_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define XELPD_PW_A_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define XELPD_PW_2_POWER_DOMAINS ( \
XELPD_PW_B_POWER_DOMAINS | \
XELPD_PW_C_POWER_DOMAINS | \
XELPD_PW_D_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
--
2.27.0
