== Series Details ==
Series: drm/i915/guc/slpc: Enable GuC based power management features (rev3)
URL : https://patchwork.freedesktop.org/series/93026/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10421 -> Patchwork_20747
== Series Details ==
Series: drm/i915/guc/slpc: Enable GuC based power management features (rev3)
URL : https://patchwork.freedesktop.org/series/93026/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separatel
== Series Details ==
Series: drm/i915/guc/slpc: Enable GuC based power management features (rev3)
URL : https://patchwork.freedesktop.org/series/93026/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
987807ad0545 drm/i915/guc/slpc: Initial definitions for SLPC
-:77: WARNING:FILE_
On Wed, 28 Jul 2021 15:20:15 -0700, Dixit, Ashutosh wrote:
>
> On Wed, 28 Jul 2021 03:30:31 -0700, Matthew Auld wrote:
> >
> > diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
> > index 4b4f2114..e2514f0c 100644
> > --- a/lib/i915/gem_mman.c
> > +++ b/lib/i915/gem_mman.c
> > @@ -497,6 +497,43
Tests that exercise the SLPC get/set frequency interfaces.
Clamp_max will set max frequency to multiple levels and check
that SLPC requests frequency lower than or equal to it.
Clamp_min will set min frequency to different levels and check
if SLPC requests are higher or equal to those levels.
v2
This feature hands over the control of HW RC6 to the GuC.
GuC decides when to put HW into RC6 based on it's internal
busyness algorithms.
GuCRC needs GuC submission to be enabled, and only
supported on Gen12+ for now.
When GuCRC is enabled, do not set HW RC6. Use a H2G message
to tell GuC to enab
Update the get/set min/max freq hooks to work for
SLPC case as well. Consolidate helpers for requested/min/max
frequency get/set to intel_rps where the proper action can
be taken depending on whether SLPC is enabled.
v2: Add wrappers for getting rp0/1/n frequencies, update
softlimits in set min/ma
Cache rp0, rp1 and rpn platform limits into SLPC structure
for range checking while setting min/max frequencies.
Also add "soft" limits which keep track of frequency changes
made from userland. These are initially set to platform min
and max.
v2: Address review comments (Michal W)
v3: Formatting
This interrupt is enabled during RPS initialization, and
now needs to be done by SLPC code. It allows ARAT timer
expiry interrupts to get forwarded to GuC.
v2: Fix comment (Matthew Brost)
v3: checkpatch()
Reviewed-by: Matthew Brost
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc
This prints out relevant SLPC info from the SLPC shared structure.
We will send a H2G message which forces SLPC to update the
shared data structure with latest information before reading it.
v2: Address review comments (Michal W)
v3: Remove unnecessary tasks from slpc_info (Michal W)
v4: Rename f
Add helpers to read the min/max frequency being used
by SLPC. This is done by send a H2G command which forces
SLPC to update the shared data struct which can then be
read. These helpers will be used in a sysfs patch later
on.
v2: Address review comments (Michal W)
v3: Return err in case of query f
Add methods for interacting with GuC for enabling SLPC. Enable
SLPC after GuC submission has been established. GuC load will
fail if SLPC cannot be successfully initialized. Add various
helper methods to set/unset the parameters for SLPC. They can
be set using H2G calls or directly setting bits in
Add param set h2g helpers to set the min and max frequencies
for use by SLPC.
v2: Address review comments (Michal W)
v3: Check for positive error code (Michal W)
v4: Print generic error in set_param (Michal W)
Reviewed-by: Michal Wajdeczko
Signed-off-by: Sundaresan Sujaritha
Signed-off-by: Vina
The assumption when it was added was that GT would not be
holding any gt_pm references. However, uc_init is called
from gt_init_hw, which holds a forcewake ref. If SLPC
enable fails, we will still be holding this ref, which will
result in the BUG_ON.
Reviewed-by: Matthew Brost
Signed-off-by: Vina
Allocate data structures for SLPC and functions for
initializing on host side.
v2: Address review comments (Michal W)
v3: Remove unnecessary header includes (Michal W)
v4: Rebase
v5: Move allocation of shared data into slpc_init() (Michal W)
Reviewed-by: Michal Wajdeczko
Signed-off-by: Vinay Bel
Add constants and params that are needed to configure SLPC.
v2: Add a new abi header for SLPC. Replace bitfields with
genmasks. Address other comments from Michal W.
v3: Add slpc H2G format in abi, other review commments (Michal W)
v4: Update status bits according to latest spec
v5: checkpatch(
Also ensure uc_init is called before we initialize RPS so that we
can check for SLPC support. We do not need to enable up/down
interrupts when SLPC is enabled. However, we still need the ARAT
interrupt, which will be enabled separately later.
v2: Explicitly return from intel_rps_enable with slpc c
This series enables Single Loop Power Control (SLPC) feature in GuC.
GuC implements various power management algorithms as part of it's
operation. These need to be specifically enabled by KMD. They replace
the legacy host based management of these features.
With this series, we will enable two PM
Add macros to check for SLPC support. This feature is currently supported
for Gen12+ and enabled whenever GuC submission is enabled/selected.
Include templates for SLPC init/fini and enable.
v2: Move SLPC helper functions to intel_guc_slpc.c/.h. Define
basic template for SLPC structure in intel_g
Hi Vinay,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next drm/drm-next v5.14-rc3 next-20210729]
[If your patch is applied to the wrong git tree, kindly
On 7/29/2021 4:40 PM, Matthew Brost wrote:
On Wed, Jul 28, 2021 at 02:11:43PM -0700, Vinay Belgaumkar wrote:
Tests that exercise the SLPC get/set frequency interfaces.
Clamp_max will set max frequency to multiple levels and check
that SLPC requests frequency lower than or equal to it.
Clamp_
== Series Details ==
Series: Remove CNL - for drm-intel-next (rev3)
URL : https://patchwork.freedesktop.org/series/93142/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10420 -> Patchwork_20746
Summary
---
**SUCCESS**
On 7/28/2021 17:34, Matthew Brost wrote:
If an engine associated with a context does not have a heartbeat, ban it
immediately. This is needed for GuC submission as a idle pulse doesn't
kick the context off the hardware where it then can check for a
heartbeat and ban the context.
It's worse than t
== Series Details ==
Series: Remove CNL - for drm-intel-next (rev3)
URL : https://patchwork.freedesktop.org/series/93142/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
94fd27e43bfd drm/i915/display: remove PORT_F workaround for CNL
ca468dd23483 drm/i915/display: remove explicit
On Thu, Jul 29, 2021 at 04:54:08PM -0700, John Harrison wrote:
> On 7/27/2021 11:20, Matthew Brost wrote:
> > With GuC submission contexts can get reordered (compared to submission
> > order), if contexts get reordered the sequential nature of the batches
> > releasing the next batch's semaphore in
On 7/27/2021 11:20, Matthew Brost wrote:
With GuC submission contexts can get reordered (compared to submission
order), if contexts get reordered the sequential nature of the batches
releasing the next batch's semaphore in function timesliceN() get broken
resulting in the test taking much longer
On Wed, Jul 28, 2021 at 02:11:43PM -0700, Vinay Belgaumkar wrote:
> Tests that exercise the SLPC get/set frequency interfaces.
>
> Clamp_max will set max frequency to multiple levels and check
> that SLPC requests frequency lower than or equal to it.
>
> Clamp_min will set min frequency to differ
The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly in intel_ddi.c.
A lot of special code for CNL can be removed. There were some
__cnl.*() functions that were created to share the implementation
between ICL and CNL. Those are now embedded in the only calle
Reviewed-by: az Yokoyama
-caz
On Wed, 2021-07-28 at 22:41 -0700, Matt Roper wrote:
> The list of shadowed registers on XeHP is identical to the set for
> earlier gen12 platforms, with additional ranges added for the new VCS
> and VECS engines. Since those register ranges were reserved on
> earli
On Wed, Jul 28, 2021 at 06:51:29PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 7/27/2021 8:22 AM, Matthew Brost wrote:
> > The i915 currently has 2k visible priority levels which are currently
> > unique. This is changing to statically map these 2k levels into 3
> > buckets:
> >
> > low: < 0
>
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: fixup igt_shrink_thp
URL : https://patchwork.freedesktop.org/series/93182/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10418_full -> Patchwork_20741_full
=
== Series Details ==
Series: lpsp with hdmi/dp outputs
URL : https://patchwork.freedesktop.org/series/93179/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10418_full -> Patchwork_20740_full
Summary
---
**FAILURE**
== Series Details ==
Series: series starting with [CI,01/10] drm/i915/bios: Allow DSI ports to be
parsed by parse_ddi_port()
URL : https://patchwork.freedesktop.org/series/93210/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10420 -> Patchwork_20745
==
== Series Details ==
Series: series starting with [CI,01/10] drm/i915/bios: Allow DSI ports to be
parsed by parse_ddi_port()
URL : https://patchwork.freedesktop.org/series/93210/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commi
== Series Details ==
Series: series starting with [CI,01/10] drm/i915/bios: Allow DSI ports to be
parsed by parse_ddi_port()
URL : https://patchwork.freedesktop.org/series/93210/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
311c3d22baba drm/i915/bios: Allow DSI ports to be pa
On Thu, Jul 29, 2021 at 02:55:17PM -0700, Yokoyama, Caz wrote:
> On Thu, 2021-07-29 at 08:21 -0700, Matt Roper wrote:
> > Rather than defining our shadow tables as a list of individual
> > registers, provide them as a list of register ranges; we'll have some
> > ranges of multiple registers being a
On Wed, 2021-07-28 at 17:32 -0700, Lucas De Marchi wrote:
> On Wed, Jul 28, 2021 at 02:59:46PM -0700, Lucas De Marchi wrote:
> > With all the users removed, finish removing the CNL platform
> > definitions.
> > We will leave the PCI IDs around as those are exposed to userspace.
> > Even if mesa doe
On Thu, 2021-07-29 at 08:21 -0700, Matt Roper wrote:
> Rather than defining our shadow tables as a list of individual
> registers, provide them as a list of register ranges; we'll have some
> ranges of multiple registers being added soon (and we already have a
> couple adjacent registers that we ca
On newer platform this opregion call always fails, also it do not
support multiple panels so dropping it.
Reviewed-by: Matt Atwood
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 19 +++
1 file changed, 7 i
Allow MIPI DSI ports to be parsed like any other DDI port.
This will be helpful to integrate into just one function the parse of
information about integrated panels(eDP and DSI).
Cc: Ville Syrjälä
Cc: Jani Nikula
Reviewed-by: Matt Atwood
Signed-off-by: José Roberto de Souza
---
drivers/gpu/dr
All the users were converted, now we can drop it.
Reviewed-by: Matt Atwood
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 36 ---
drivers/gpu/drm/i915/i915_drv.h | 1 -
2 files changed, 37 d
Tigerlake and newer has two instances of PPS, to support up to two
eDP panels.
Reviewed-by: Matt Atwood
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_pps.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/dri
Continuing the conversion from single integrated VBT data to two, now
handling PSR data.
Reviewed-by: Matt Atwood
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 73 +--
drivers/gpu/drm/i915/display/int
VBT has support for up two integrated panels but i915 only supports one.
So here stating to add the basic support for two integrated panels
and moving the DRRS to ddi_vbt_port_info instead of keeping a global
one.
Other VBT blocks will be converted in following patches.
While at is also nucking l
Continuing the conversion from single integrated VBT data to two, now
handling DSI data.
Reviewed-by: Matt Atwood
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/icl_dsi.c | 12 +-
drivers/gpu/drm/i915/display/intel_bios.c| 16
Continuing the conversion from single integrated VBT data to two, now
handling eDP data.
Reviewed-by: Matt Atwood
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/g4x_dp.c | 9 ++-
drivers/gpu/drm/i915/display/intel_bios.c |
Continuing the conversion from single integrated VBT data to two, now
handling backlight data.
Reviewed-by: Matt Atwood
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 59 +++
drivers/gpu/drm/i915/displ
Continuing the conversion from single integrated VBT data to two.
Reviewed-by: Matt Atwood
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c| 53 +---
drivers/gpu/drm/i915/display/intel_bios.h| 1 +
dr
Reviewed-by: Caz Yokoyama
-caz
On Wed, 2021-07-28 at 22:41 -0700, Matt Roper wrote:
> The forcewake read logic is identical between gen11 and gen12, only
> the
> forcewake table data (which is tracked separately) differs; there's
> no
> need to generate a separate set of gen12 read functions when
== Series Details ==
Series: Begin enabling Xe_HP SDV and DG2 platforms (rev8)
URL : https://patchwork.freedesktop.org/series/92135/
State : failure
== Summary ==
Applying: drm/i915/xehp: handle new steering options
Applying: drm/i915/xehpsdv: Define steering tables
Applying: drm/i915/dg2: Add
== Series Details ==
Series: Forcewake and shadowed register updates (rev2)
URL : https://patchwork.freedesktop.org/series/93158/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10420 -> Patchwork_20742
Summary
---
**S
== Series Details ==
Series: Remove CNL - for drm-intel-next (rev2)
URL : https://patchwork.freedesktop.org/series/93142/
State : failure
== Summary ==
Applying: drm/i915/display: remove PORT_F workaround for CNL
Applying: drm/i915/display: remove explicit CNL handling from intel_cdclk.c
Apply
drm-misc-next-2021-07-29:
drm-misc-next for v5.15:
UAPI Changes:
- Add modifiers for arm fixed rate compression.
Cross-subsystem Changes:
- Assorted dt binding fixes.
- Convert ssd1307fb to json-schema.
- Update a lot of irc channels to point to OFTC, as everyone moved there.
- Fix the same divid
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: fixup igt_shrink_thp
URL : https://patchwork.freedesktop.org/series/93176/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10418_full -> Patchwork_20739_full
=
On Wed, Jul 28, 2021 at 07:00:53PM -0700, Daniele Ceraolo Spurio wrote:
> From: Vitaly Lubart
>
> Export PAVP client to work with i915 driver,
> for binding it uses kernel component framework.
>
> v2:drop debug prints, refactor match code to match mei_hdcp (Tomas)
>
> Signed-off-by: Vitaly Luba
On Thu, Jul 29, 2021 at 08:17:44AM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 7/29/2021 4:10 AM, Rodrigo Vivi wrote:
> > On Wed, Jul 28, 2021 at 07:01:01PM -0700, Daniele Ceraolo Spurio wrote:
> > > This api allow user mode to create protected buffers and to mark
> > > contexts as making use o
== Series Details ==
Series: Forcewake and shadowed register updates (rev2)
URL : https://patchwork.freedesktop.org/series/93158/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i9
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
> Update the get/set min/max freq hooks to work for
> SLPC case as well. Consolidate helpers for requested/min/max
> frequency get/set to intel_rps where the proper action can
> be taken depending on whether SLPC is enabled.
>
> v2: Add wrappers for
== Series Details ==
Series: drm/i915/selftests: prefer the create_user helper (rev2)
URL : https://patchwork.freedesktop.org/series/93131/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10418_full -> Patchwork_20738_full
Su
On Thu, Jul 29, 2021 at 10:00:02AM -0700, Matt Roper wrote:
From: Lucas De Marchi
Like DG1, XeHP SDV doesn't have LLC/eDRAM control values due to being a
dgfx card. XeHP SDV adds 2 more bits: L3_GLBGO to "push the Go point to
memory for L3 destined transaction" and L3_LKP to "enable Lookup for
On 7/29/2021 9:21 AM, Michal Wajdeczko wrote:
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
Cache rp0, rp1 and rpn platform limits into SLPC structure
for range checking while setting min/max frequencies.
Also add "soft" limits which keep track of frequency changes
made from userland. These
DG2 supports compute DSS and has the same maximum number of DSS and EU
as XeHP SDV.
Signed-off-by: Matt Roper
Reviewed-by: Caz Yokoyama
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/dr
From: Stuart Summers
Starting in XeHP, the concept of slice has been removed in favor of
DSS (Dual-Subslice) masks for various workload types. These workloads have
been divided into those enabled for geometry and those enabled for compute.
i915 currently maintains a single set of S/SS/EU masks f
The RP_STATE_CAP register is no longer part of the MCHBAR on XEHPSDV; this
register is now a per-tile register at GTTMMADDR offset 0x250014.
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_rps.c | 4 +++-
dr
Bspec: 45101, 45427
Cc: Ramalingam C (v5)
Signed-off-by: Matt Roper
Reviewed-by: Matt Atwood
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 35 +++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/i
From: Ankit Nautiyal
Add the functions to configure HDMI2.1 pcon for DG2, before DP link
training.
Signed-off-by: Ankit Nautiyal
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi
From: Lucas De Marchi
Instead of maintaining the same if ladder in 3 different places, add a
function to read RP_STATE_CAP.
Signed-off-by: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 8 +++-
drivers/gpu/drm/i915/gt/intel_rps.c | 17
From: Lucas De Marchi
Like DG1, XeHP SDV doesn't have LLC/eDRAM control values due to being a
dgfx card. XeHP SDV adds 2 more bits: L3_GLBGO to "push the Go point to
memory for L3 destined transaction" and L3_LKP to "enable Lookup for
uncacheable accesses".
Bspec: 45101
Cc: Daniele Ceraolo Spuri
From: Akeem G Abodunrin
New LRI register offsets were introduced for DG2, this patch adds
those extra registers, and create new register table for setting offsets
to compare with HW generated context image - especially for gt_lrc test.
Also updates general purpose register with scratch offset for
For tgl+, the per-context setting of MI_MODE[12] determines whether
the bits of a nested MI_BATCH_BUFFER_START instruction should be
interpreted in the traditional manner or whether they should
instead use a new tgl+ meaning that breaks backward compatibility, but
allows nesting into 3rd-level batc
Xe_HPG adds some additional INSTDONE_GEOM debug registers; the Mesa team
has indicated that having these reported in the error state would be
useful for debugging GPU hangs. These registers are replicated per-DSS
with gslice steering.
Cc: Lionel Landwerlin
Signed-off-by: Matt Roper
Acked-by: Li
Due to the removal of legacy slices and the transition to a
gslice/cslice/mslice/etc. design, we'll internally store all DSS under
"slice0."
Signed-off-by: Matt Roper
Reviewed-by: Caz Yokoyama
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 5 -
drivers/gpu/drm/i915/gt/intel_sseu.h
We no longer have traditional slices on Xe_HP platforms, but the
INSTDONE registers are replicated according to gslice representation
which is similar. We can mostly re-use the existing instdone code with
just a few modifications:
* Create an alternate instdone loop macro that will iterate over
From: Matthew Auld
Xe_HP no longer has "slices" in the same way that old platforms did.
There are new concepts (gslices, cslices, mslices) that apply in various
contexts, but for the purposes of fusing slices no longer exist and we
just have one large pool of dual-subslices (DSS) to work with.
Fu
From: Daniele Ceraolo Spurio
Xe_HP is more modular than its predecessors and as a consequence it has
more types of replicated registers. As with l3bank regions on previous
platforms, we may need to explicitly re-steer accesses to these new
types of ranges at runtime if we can't find a single def
DG2's replicated register ranges are almost the same at XeHP SDV with
the exception of one LNCF sub-range that switches to gslice steering.
We can re-use the XeHP SDV mslice steering table and just provide a
DG2-specific LNCF steering table.
Bspec: 66534
Cc: Daniele Ceraolo Spurio
Signed-off-by:
Define and initialize the MMIO ranges for which XeHP SDV requires MSLICE
and LNCF steering.
Bspec: 66534
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 19 ++-
drivers/gpu/drm/i915/gt/intel_workarounds.c
Although DG2_G10 platforms will always have all SQIDI's present and
don't need steering for registers in a SQIDI MMIO range, this isn't true
for DG2_G11 platforms; only SQIDI's 2 and 3 can be used on those.
We handle SQIDI ranges a bit differently from other types of explicit
steering. The SQIDI
This series provides some of the initial enablement patches for two
upcoming discrete GPUs:
* XeHP SDV: Xe_HP (version 12.50) graphics IP, no display IP
* DG2: Xe_HPG (version 12.55) graphics IP, Xe_LPD (version 13) display IP
Both platforms will need additional enablement patches beyond what'
The DG2 forcewake table is very similar to the one used by XeHP SDV (and
both platforms are even presented as a single table in the bspec). For
the most part DG2 starts using a few additional ranges that were
'reserved' on XeHP SDV and stops using some others. However there is a
single range (0xd
On Fri, Feb 26, 2021 at 12:15:54AM -0800, Khaled Almahallawy wrote:
> Source needs to write DPCD 103-106 after receiving a PHY request to change
> swing/pre-emphasis after reading DPCD 206-207. This is especially needed if
> there is a retimer between source and sink and the retimer implements AUX_
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
> Add param set h2g helpers to set the min and max frequencies
> for use by SLPC.
>
> v2: Address review comments (Michal W)
> v3: Check for positive error code (Michal W)
> v4: Print generic error in set_param (Michal W)
>
> Signed-off-by: Sundares
The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly.
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
v1.1: rebase
drivers/gpu/drm/i915/display/intel_ddi.c | 12 +-
.../drm/i915/display/intel_ddi_buf_trans.c| 676 ++---
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
> Cache rp0, rp1 and rpn platform limits into SLPC structure
> for range checking while setting min/max frequencies.
>
> Also add "soft" limits which keep track of frequency changes
> made from userland. These are initially set to platform min
> and
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
> Add methods for interacting with GuC for enabling SLPC. Enable
> SLPC after GuC submission has been established. GuC load will
> fail if SLPC cannot be successfully initialized. Add various
> helper methods to set/unset the parameters for SLPC. They
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
> Add constants and params that are needed to configure SLPC.
>
> v2: Add a new abi header for SLPC. Replace bitfields with
> genmasks. Address other comments from Michal W.
>
> v3: Add slpc H2G format in abi, other review commments (Michal W)
>
> v
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
> Add macros to check for SLPC support. This feature is currently supported
> for Gen12+ and enabled whenever GuC submission is enabled/selected.
>
> Include templates for SLPC init/fini and enable.
>
> v2: Move SLPC helper functions to intel_guc_slp
Rather than defining our shadow tables as a list of individual
registers, provide them as a list of register ranges; we'll have some
ranges of multiple registers being added soon (and we already have a
couple adjacent registers that we can squash into a single range now).
This change also defines
On 7/29/2021 4:10 AM, Rodrigo Vivi wrote:
On Wed, Jul 28, 2021 at 07:01:01PM -0700, Daniele Ceraolo Spurio wrote:
This api allow user mode to create protected buffers and to mark
contexts as making use of such objects. Only when using contexts
marked in such a way is the execution guaranteed
On Fri, Jul 23, 2021 at 10:42:31AM -0700, Matt Roper wrote:
> Bspec: 45101, 45427
> Cc: Ramalingam C (v5)
> Signed-off-by: Matt Roper
Reviewed-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/gt/intel_mocs.c | 35 +++-
> 1 file changed, 34 insertions(+), 1 deletion(-)
>
> di
On Fri, Jul 23, 2021 at 10:42:30AM -0700, Matt Roper wrote:
> Xe_HPG adds some additional INSTDONE_GEOM debug registers; the Mesa team
> has indicated that having these reported in the error state would be
> useful for debugging GPU hangs. These registers are replicated per-DSS
> with gslice steer
On Fri, Jul 23, 2021 at 10:42:32AM -0700, Matt Roper wrote:
> DG2's SNPS PHYs incorporate a dedicated port PLL called MPLLB which
> takes the place of the shared DPLLs we've used on past platforms. Let's
> add the MPLLB programming sequences; they'll be plugged into the rest of
> the code in futur
On 29/7/21 3:00 pm, Daniel Vetter wrote:
On Tue, Jul 27, 2021 at 04:37:22PM +0200, Peter Zijlstra wrote:
On Thu, Jul 22, 2021 at 12:38:10PM +0200, Daniel Vetter wrote:
On Thu, Jul 22, 2021 at 05:29:27PM +0800, Desmond Cheong Zhi Xi wrote:
Inside drm_is_current_master, using the outer drm_devic
On Thu, Jul 29, 2021 at 10:32:13PM +0800, Desmond Cheong Zhi Xi wrote:
> Sounds good, will do. Thanks for the patch, Peter.
>
> Just going to make a small edit:
> s/LOCK_STAT_NOT_HELD/LOCK_STATE_NOT_HELD/
Bah, I knew I should've compile tested it :-), Thanks!
_
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: fixup igt_shrink_thp
URL : https://patchwork.freedesktop.org/series/93182/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10418 -> Patchwork_20741
S
Reviewed-by: Caz Yokoyama
-caz
On Wed, 2021-07-28 at 22:41 -0700, Matt Roper wrote:
> For historical reasons, the GT forcewake domain used to be referred
> to
> as the "blitter" domain; that name is no longer accurate since the GT
> domain contains a lot of additional registers and functionality
On Thu, Jul 29, 2021 at 3:34 PM Tvrtko Ursulin
wrote:
>
> From: Tvrtko Ursulin
>
> Usage of Transparent Hugepages was disabled in 9987da4b5dcf
> ("drm/i915: Disable THP until we have a GPU read BW W/A"), but since it
> appears majority of performance regressions reported with an enabled IOMMU
> c
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: fixup igt_shrink_thp
URL : https://patchwork.freedesktop.org/series/93182/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1cac26e2f95f drm/i915/selftests: fixup igt_shrink_thp
054c89f72f0f drm/i915: Use
From: Tvrtko Ursulin
Usage of Transparent Hugepages was disabled in 9987da4b5dcf
("drm/i915: Disable THP until we have a GPU read BW W/A"), but since it
appears majority of performance regressions reported with an enabled IOMMU
can be almost eliminated by turning them on, lets just do that.
To e
From: Matthew Auld
Since the object might still be active here, the shrink_all will simply
ignore it, which blows up in the test, since the pages will still be
there. Currently THP is disabled which should result in the test being
skipped, but if we ever re-enable THP we might start seeing the fa
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