== Series Details ==
Series: Alder Lake-P Support (rev2)
URL : https://patchwork.freedesktop.org/series/89899/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10060_full -> Patchwork_20091_full
Summary
---
**FAILURE**
== Series Details ==
Series: Alder Lake-P Support (rev2)
URL : https://patchwork.freedesktop.org/series/89899/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10060 -> Patchwork_20091
Summary
---
**SUCCESS**
No regr
== Series Details ==
Series: Alder Lake-P Support (rev2)
URL : https://patchwork.freedesktop.org/series/89899/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/display/intel_di
== Series Details ==
Series: Alder Lake-P Support (rev2)
URL : https://patchwork.freedesktop.org/series/89899/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a5348dda9410 drm/i915/xelpd: Handle proper AUX interrupt bits
3ecdad37cbcd drm/i915/xelpd: Enhanced pipe underrun reporti
From: Vandita Kulkarni
Add the qp table for 444 formats, for 8bpc, 10bpc and 12bpc, as given by
the VESA C model for DSC 1.1
v2:
- Add include guard to header (Jani)
- Move the big tables to a .c file (Chris, Jani, Lucas)
v3:
- Make tables 'static const' and add lookup functions to index into
== Series Details ==
Series: Alder Lake-P Support
URL : https://patchwork.freedesktop.org/series/89899/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i9
From: Umesh Nerlige Ramappa
Enable relevant OA formats for ADL_P.
Cc: Ashutosh Dixit
Signed-off-by: Umesh Nerlige Ramappa
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 1 +
1 file changed, 1 insertion(+)
diff --g
From: José Roberto de Souza
Implementation details are in the HSD 22011320316, requiring CD clock
to be at least 307MHz to make DC states to work.
Cc: Matt Roper
Cc: Anusha Srivatsa
Signed-off-by: José Roberto de Souza
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu
From: José Roberto de Souza
Adding a new hook to ADL-P just to avoid another platform check in
gen12lp_init_clock_gating() but also open to it.
BSpec: 54369
Cc: Matt Roper
Cc: Anusha Srivatsa
Signed-off-by: José Roberto de Souza
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
d
From: José Roberto de Souza
Buffer compression is not usable in A stepping.
Cc: Matt Roper
Cc: Anusha Srivatsa
Cc: Clinton A Taylor
Cc: Juha-Pekka Heikkilä
Signed-off-by: José Roberto de Souza
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
---
.../d
From: José Roberto de Souza
This will allow us to better implement workarounds.
Cc: Matt Roper
Signed-off-by: José Roberto de Souza
Signed-off-by: Jani Nikula
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.h | 8
drivers/gpu/drm/i915/intel_step.c | 12 +++-
From: Animesh Manna
Respective bit for master or slave to be set for uncompressed
bigjoiner in dss_ctl1 register.
Cc: Manasi Navare
Signed-off-by: Animesh Manna
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++
drivers/gpu/drm
From: Vandita Kulkarni
Move the platform specific max bpc calculation into
intel_dp_dsc_compute_bpp function
Cc: Manasi Navare
Signed-off-by: Vandita Kulkarni
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 ++--
1 file changed, 10 insertions(+), 10
From: Vandita Kulkarni
Add the qp table for 444 formats, for 8bpc, 10bpc and 12bpc, as given by
the VESA C model for DSC 1.1
v2:
- Add include guard to header (Jani)
- Move the big tables to a .c file (Chris, Jani, Lucas)
v3:
- Make tables 'static const' and add lookup functions to index into
From: Manasi Navare
On XE_LPD, VRR CTL register adds a new VRR Guardband bitfield
replacing the pipeline full and deprecating the pipeline override
bit.
This patch adds this corresponding bitfield in the register defs,
crtc state vrr structure and populates this in vrr compute
config and vrr ena
From: Gwan-gyeong Mun
This introduces the following function that can enable and disable psr
without intel_crtc_state/drm_connector_state when intel_psr is already
enabled with current intel_crtc_state and drm_connector_state information.
- intel_psr_pause(): Pause current PSR. it deactivates cu
From: Gwan-gyeong Mun
In order to reuse code of PSR interrupt error check on other PSR functions,
it adds psr_interrupt_error_check() function.
Cc: José Roberto de Souza
Signed-off-by: Gwan-gyeong Mun
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_psr.c | 47 +++
From: Ville Syrjälä
The dbuf slices are going to be split across several MBUS units.
The actual dbuf programming will use offsets relative to the
MBUS unit. To accommodate that we shall store the MBUS relative
offsets into the dbuf_state->ddb[] and crtc_state->plane_ddb*[].
For crtc_state->wm.sk
From: Gwan-gyeong Mun
It replaces dc3co_enabled with dc3co_exitline on intel_psr struct. And
it saves dc3co_exitline, not dc3co_enabled, so we can use dc3co_exitline
without intel_crtc_state on other psr internal function like as
intel_psr_enable_source().
Cc: Ville Syrjälä
Cc: José Roberto de
From: Anusha Srivatsa
ADL_P has same memory characteristics as ADL_S platform.
Bspec: 64631
Cc: José Roberto de Souza
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed,
From: Anusha Srivatsa
ADL-P has 3 possible refclk frequencies: 19.2MHz,
24MHz and 38.4MHz
While we're at it, remove the drm_WARNs. They've never actually helped
us catch any problems, but it's very easy to forget to update them
properly for new platforms.
BSpec: 55409, 49208
Cc: Matt Roper
Cc
From: Anusha Srivatsa
The SoC has 6 DDI ports(DDI A,DDI B and DDI TC1-4.
The first two are connected to combo phys while
the rest are connected to TC phys.
Cc: Matt Roper
Cc: Clinton Taylor
Cc: Lucas De Marchi
Cc: Swathi Dhanavanthri
Signed-off-by: Anusha Srivatsa
Signed-off-by: Clinton Tay
The DDI naming template for display version 12 went A-C, TC1-TC6. With
XE_LPD, that naming scheme for DDI's has now changed to A-E, TC1-TC4.
The XE_LPD design keeps the register offsets and bitfields relating to
the TC outputs in the same location they were previously. The new "D"
and "E" output
From: Animesh Manna
No need for checking dsc flag for uncompressed pipe joiner mode
validation.
Cc: Manasi Navare
Signed-off-by: Animesh Manna
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 +--
1 file changed, 5 insertions(+), 2
From: José Roberto de Souza
This will allow proper DDI initialization based on vbt information.
Cc: Uma Shankar
Signed-off-by: José Roberto de Souza
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bios.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-
From: Mika Kahola
Disable loadgen sharing for DP link rate 1.62 GHz and HDMI 5.94 GHz.
For all other modes, we can enable loadgen sharing feature.
BSpec: 55359
Cc: Imre Deak
Signed-off-by: Mika Kahola
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/
From: José Roberto de Souza
Alderlake P have modular FIA like TGL but it is always modular in all
skus, not like TGL that we had to read a register to check if it is
monolithic or modular.
BSpec: 55480
BSpec: 50572
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
Signed-off-by: Clinton Taylo
From: Vandita Kulkarni
On adlp the two mbuses have two display pipes and
two DBUFS, Pipe A and D on Mbus1 and Pipe B and C on
Mbus2. The Mbus can be joined and all the DBUFS can be
used on Pipe A or B.
Bspec: 49255
Cc: Anusha Srivatsa
Signed-off-by: Vandita Kulkarni
Signed-off-by: Clinton Tayl
Cc: Aditya Swarup
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4
drivers/gpu/drm/i915/i915_reg.h| 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_po
From: Mika Kahola
Define and use DP voltage swing and pre-emphasis translation tables
for ADL-P.
BSpec: 54956
Cc: Imre Deak
Signed-off-by: Mika Kahola
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++-
.../drm/i915/display/i
From: Anusha Srivatsa
The clocks in ALD_P is similar to that of TGL.
The combo PLLs use the same DPLL0, DPLL1 and TBT_PLL.
This patch adds the helper function intel_mg_pll_enable_reg()
which is similar to intel_combo_pll_enable_reg() for being lookup
place for PLL_ENABLE register in combo phy c
ADL-P further extends the bits in PLANE_WM that represent blocks and
lines; we need to extend our masks accordingly. Since these bits are
reserved and MBZ on earlier platforms, it's safe to use the larger
bitmask on all platforms.
Bspec: 50419
Cc: Matt Atwood
Signed-off-by: Matt Roper
Signed-of
From: José Roberto de Souza
ADL-P have basically the same TC connection and disconnection
sequences as ICL and TGL, the major difference is the new registers.
So here adding functions without the icl prefix in the name and
making the new functions call the platform specific function to access
th
From: Anusha Srivatsa
When scalers are enabled, we need to program underrun
bubble counter to 0x50 to avoid Soft Pipe A underruns.
Make sure other bits dont get overwritten.
Cc: Matt Roper
Cc: Clint Taylor
Cc: José Roberto de Souza
Signed-off-by: Anusha Srivatsa
Signed-off-by: Clinton Taylor
From: Imre Deak
On ADL_P besides programming the PLL accordingly the DP/HDMI link rate
should be also programmed to the DDI_BUF_CTL register, do that.
Cc: José Roberto de Souza
Signed-off-by: Imre Deak
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_ddi.c | 36 ++
From: Ville Syrjälä
Move intel_modeset_all_pipes() to a central place so that we can
use it elsewhere as well. No functional changes.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c
XE_LPD reduces the number of regular watermark latency levels from 8
to 6 on non-dgfx platforms. However the hardware also adds a special
purpose SAGV wateramrk (and an accompanying transition watermark) that
will be used by the hardware in place of the level 0 values during SAGV
transitions.
Bsp
From: Vandita Kulkarni
Support compression BPPs from bpc to uncompressed BPP -1.
So far we have 8,10,12 as valid compressed BPPS now the
support is extended.
Cc: Manasi Navare
Signed-off-by: Vandita Kulkarni
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 32 +
From: Animesh Manna
For uncompressed big joiner DSC engine will not be used so will avoid
compute config of DSC.
Cc: Manasi Navare
Signed-off-by: Animesh Manna
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
1 file changed, 6
If VT-d is active, the memory bandwidth usage of the display is 5%
higher. Take this into account when determining whether we can support
a display configuration.
Bspec: 64631
Cc: Matt Atwood
Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_bw.c |
From: Mika Kahola
Today when the DSI controller is paired with the Combo-PHY it
uses the high-speed (HS) Word clock for its low power (LP)
transmit PPI communication to the DPHY. The interface signaling
only changes state at an Escape clock frequency (i.e. its
effectively running on a virtual Tx
From: Clinton Taylor
Add ADP-P PCH device ID and assign as ADL PCH if found. Previously we
would assign the DDC pin map based on the PCH, but it can also change
based on the CPU. From Bspec 20124: "The physical port to pin pair
mapping are defined in the Bspec per PCH. Mapping can further change
From: Gwan-gyeong Mun
It removes intel_crtc_state from function argument of
intel_psr_enable_source() in order to use intel_psr_enable_source()
without intel_crtc_state on other psr internal functions.
And we can get cpu_trancoder from intel_psr, therefore we don't need to
pass intel_crtc_state t
Aside from the hardware-managed PG0, XE_LPD has power wells 1-2 and
A-D. These power wells should be enabled/disabled according to the
following dependency tree (enable top to bottom, disable bottom to top):
PG0
|
--PG1--
/ \
From: José Roberto de Souza
On ADL-P TC cold is exited and blocked when legacy aux is powered,
that is exacly the same of what ICL need for static TC ports.
TODO: When a TBT hub or monitor is connected it will cause TBT and
legacy aux to be powered at the same time, hopefully this will not
cause
XE_LPD brings enhanced underrun recovery: the hardware can somewhat
mitigate underruns by using an interpolated replacement pixel (soft
underrun) or the previous pixel (hard underrun). Furthermore, underruns
can now be caused downstream by the port, even if the pipe itself is
operating properly.
From: Vandita Kulkarni
We need slice height to calculate few RC parameters
hence assign slice height first.
Cc: Manasi Navare
Signed-off-by: Vandita Kulkarni
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
d
From: José Roberto de Souza
When DP_PHY_MODE_STATUS_NOT_SAFE is set, it means that display
has the control over the TC phy.
The "not safe" naming is confusing using ownership make it easier
to read also future platforms will have a new register that does the
same job as DP_PHY_MODE_STATUS_NOT_SAF
From: Vandita Kulkarni
Update MBUS_CTL register if the 2 mbus can be joined as per the current
DDB allocation and active pipes, also update hashing mode and pipe
select bits as per the sequence mentioned in the bspec.
Cc: Stanislav Lisovskiy
Cc: José Roberto de Souza
Signed-off-by: Vandita Ku
From: Vandita Kulkarni
Add methods to calculate rc parameters for all bpps, against the fixed
arrays that we already have for 8,10,12 valid o/p bpps, to cover RGB 444
formats. Our hw doesn't support YUV compression yet. The calculations
used here are from VESA C model for DSC 1.1
v2:
- Checkp
XE_LPD continues to use the same "skylake-style" watermark
programming as other recent platforms. The only change to the watermark
calculations compared to Display12 is that XE_LPD now allows a
maximum of 255 lines vs the old limit of 31.
Due to the larger possible lines value, the corresponding
From: José Roberto de Souza
Alderlake-P don't have programing sequences for MBUS or DBUF during
display initializaiton, instead it requires programing to those
registers during modeset because it to depend on the pipes left
enabled.
Bspec: 49213
Cc: Matt Roper
Signed-off-by: José Roberto de Sou
The previous version of this series was here:
https://patchwork.freedesktop.org/series/87897/#rev2
https://lists.freedesktop.org/archives/intel-gfx/2021-March/263029.html
Aside from general rebasing, the main changes in this version are
improvements to the Type-C, PSR, and DSC code
XE_LPD's plane support is identical to RKL and ADL-S --- 5 universal + 1
cursor with NV12 UV support on planes 1-3 and NV12 Y support on planes
4-5.
v2:
- Drop the extra 90/270 rotation check in skl_plane_check_fb(); the DRM
property code will already prevent userspace from passing us values
XE_LPD has new AUX interrupt bits for DDI-D and DDI-E that take the
spots that were used by TC5/TC6 on Display12 platforms.
While we're at it, let's convert the bit definitions for all TGL+ aux
bits over to the modern REG_BIT() notation.
v2:
- Maintain bit order rather than logical order. (Luca
== Series Details ==
Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau
(rev7)
URL : https://patchwork.freedesktop.org/series/84754/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10060_full -> Patchwork_20089_full
===
== Series Details ==
Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau
(rev7)
URL : https://patchwork.freedesktop.org/series/84754/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10060 -> Patchwork_20089
=
== Series Details ==
Series: drm/i915/gt: Do release kernel context if breadcrumb measure fails
URL : https://patchwork.freedesktop.org/series/89879/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10059_full -> Patchwork_20088_full
==
== Series Details ==
Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau
(rev7)
URL : https://patchwork.freedesktop.org/series/84754/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
== Series Details ==
Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau
(rev7)
URL : https://patchwork.freedesktop.org/series/84754/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3fc15843fb4a drm/i915/dpcd_bl: Remove redundant AUX backlight frequency
This adds support for controlling panel backlights over eDP using VESA's
standard backlight control interface. Luckily, Nvidia was cool enough to
never come up with their own proprietary backlight control interface (at
least, not any that I or the laptop manufacturers I've talked to are aware
of),
Since we're about to implement eDP backlight support in nouveau using the
standard protocol from VESA, we might as well just take the code that's
already written for this and move it into a set of shared DRM helpers.
Note that these helpers are intended to handle DPCD related backlight
control bit
If we can't read DP_EDP_PWMGEN_BIT_COUNT in
intel_dp_aux_vesa_calc_max_backlight() but do have a valid PWM frequency
defined in the VBT, we'll keep going in the function until we inevitably
fail on reading DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN. There's not much point in
doing this, so just return early.
Also, stop printing the DPCD register that failed, and just describe it
instead. Saves us from having to look up each register offset when reading
through kernel logs (plus, DPCD dumping with drm.debug |= 0x100 will give
us that anyway).
Signed-off-by: Lyude Paul
---
.../drm/i915/display/intel_d
No functional changes, just move set_vesa_backlight_enable() closer to it's
only caller: intel_dp_aux_vesa_enable_backlight().
Signed-off-by: Lyude Paul
Reviewed-by: Rodrigo Vivi
---
.../drm/i915/display/intel_dp_aux_backlight.c | 54 +--
1 file changed, 27 insertions(+), 27 del
Since we're about to be moving this code into shared DRM helpers, we might
as well start to cache certain backlight capabilities that can be
determined from the EDP DPCD, and are likely to be relevant to the majority
of drivers using said helpers. The main purpose of this is just to prevent
every d
Get rid of the extraneous switch case in here, and just open code
edp_backlight_mode as we only ever use it once.
v4:
* Check that backlight mode is DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD, not
DP_EDP_BACKLIGHT_CONTROL_MODE_MASK - imirkin
Signed-off-by: Lyude Paul
---
.../gpu/drm/i915/display/inte
This is kind of an annoying aspect of DRM's DP helpers:
drm_dp_dpcd_readb/writeb() return the size of bytes read/written on
success, thus we want to check against that instead of checking if the
return value is less than 0.
I'll probably be fixing this in the near future once I start doing DP work
This series:
* Cleans up i915's DPCD backlight code a little bit
* Extracts i915's DPCD backlight code into a set of shared DRM helpers
* Starts using those helpers in nouveau to add support to nouveau for
DPCD backlight control
v2 series-wide changes:
* Rebase
v3 series-wide changes:
* Split up
Noticed this while moving all of the VESA backlight code in i915 over to
DRM helpers: it would appear that we calculate the frequency value we want
to write to DP_EDP_BACKLIGHT_FREQ_SET twice even though this value never
actually changes during runtime. So, let's simplify things by just caching
thi
== Series Details ==
Series: series starting with [v1,1/1] drm/dp_mst: Use kHz as link rate units
when settig source max link caps at init (rev2)
URL : https://patchwork.freedesktop.org/series/89753/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10059_full -> Patchwork_20087_
On Mon, 2021-05-03 at 06:06 +0300, Ville Syrjälä wrote:
> On Fri, Apr 30, 2021 at 06:34:28PM -0400, Lyude Paul wrote:
> > Noticed this while fixing another issue in drm_dp_read_downstream_info(),
> > the open coded DP_DOWNSTREAMPORT_PRESENT check here just duplicates what
> > we
> > already do in d
Am 07.05.21 um 19:52 schrieb Ville Syrjälä:
> On Fri, May 07, 2021 at 10:49:02AM +0200, Werner Sembach wrote:
>> Couples the decission between RGB and YCbCr420 mode and the check if the
>> port clock can archive the required frequency. Other checks and
>> configuration steps that where previously d
Am 07.05.21 um 19:47 schrieb Ville Syrjälä:
> On Fri, May 07, 2021 at 10:49:01AM +0200, Werner Sembach wrote:
>> Moves some checks that later will be performed 2 times to an own function.
>> This avoids duplicate code later on.
>>
>> Signed-off-by: Werner Sembach
>> ---
>> drivers/gpu/drm/i915/d
== Series Details ==
Series: drm/i915/display: New Property Creation for HDMI
URL : https://patchwork.freedesktop.org/series/89872/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10057_full -> Patchwork_20086_full
Summary
--
On Fri, Apr 30, 2021 at 03:55:28PM +0300, Ville Syrjälä wrote:
> On Fri, Apr 30, 2021 at 07:12:53AM +, Gupta, Anshuman wrote:
> >
> >
> > > -Original Message-
> > > From: Ville Syrjälä
> > > Sent: Wednesday, April 28, 2021 12:26 AM
> > > To: Gupta, Anshuman
> > > Cc: intel-gfx@lists
== Series Details ==
Series: drm/i915/gt: Do release kernel context if breadcrumb measure fails
URL : https://patchwork.freedesktop.org/series/89879/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10059 -> Patchwork_20088
Su
== Series Details ==
Series: drm/i915/stolen: shuffle around init_memory_region
URL : https://patchwork.freedesktop.org/series/89867/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10057_full -> Patchwork_20085_full
Summary
Hi!
Dne petek, 30. april 2021 ob 11:44:50 CEST je Maxime Ripard napisal(a):
> The intel driver uses the same logic to attach the Colorspace property
> in multiple places and we'll need it in vc4 too. Let's move that common
> code in a helper.
>
> Signed-off-by: Maxime Ripard
> ---
>
> Changes f
From: Daniel Vetter
Date: 2021-05-01 01:42:20
To: kernel test robot
Cc: Bernard Zhao ,Jani Nikula
,Joonas Lahtinen
,Rodrigo Vivi ,David
Airlie ,Daniel Vetter
,intel-gfx@lists.freedesktop.org,dri-de...@lists.freedesktop.org,linux-ker...@vger.kernel.org,kbuild-...@lists.01.org
Subject: Re:
Hi!
Dne petek, 30. april 2021 ob 11:44:51 CEST je Maxime Ripard napisal(a):
> Our driver while supporting HDR didn't send the proper colorimetry info
> in the AVI infoframe.
>
> Let's add the property needed so that the userspace can let us know what
> the colorspace is supposed to be.
>
> Signe
== Series Details ==
Series: series starting with [v1,1/1] drm/dp_mst: Use kHz as link rate units
when settig source max link caps at init (rev2)
URL : https://patchwork.freedesktop.org/series/89753/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10059 -> Patchwork_20087
=
On 5/7/21 10:52 AM, Ville Syrjälä wrote:
> On Fri, May 07, 2021 at 10:49:02AM +0200, Werner Sembach wrote:
>> Couples the decission between RGB and YCbCr420 mode and the check if the
>> port clock can archive the required frequency. Other checks and
>> configuration steps that where previously done
On Fri, May 07, 2021 at 10:49:02AM +0200, Werner Sembach wrote:
> Couples the decission between RGB and YCbCr420 mode and the check if the
> port clock can archive the required frequency. Other checks and
> configuration steps that where previously done in between can also be done
> before or after
On Fri, May 07, 2021 at 10:49:01AM +0200, Werner Sembach wrote:
> Moves some checks that later will be performed 2 times to an own function.
> This avoids duplicate code later on.
>
> Signed-off-by: Werner Sembach
> ---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 41 ++-
>
== Series Details ==
Series: drm/modifiers: Enforce consistency between the cap an IN_FORMATS
URL : https://patchwork.freedesktop.org/series/89864/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10057_full -> Patchwork_20084_full
== Series Details ==
Series: series starting with [v1,1/1] drm/dp_mst: Use kHz as link rate units
when settig source max link caps at init (rev2)
URL : https://patchwork.freedesktop.org/series/89753/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bc995082bc94 drm/dp_mst: Use kH
== Series Details ==
Series: drm/i915/display: relax 2big checking around initial fb
URL : https://patchwork.freedesktop.org/series/89863/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10057_full -> Patchwork_20083_full
Sum
== Series Details ==
Series: drm/i915/display: New Property Creation for HDMI
URL : https://patchwork.freedesktop.org/series/89872/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10057 -> Patchwork_20086
Summary
---
*
== Series Details ==
Series: drm/i915: Drop duplicate WaDisable4x2SubspanOptimization:hsw
URL : https://patchwork.freedesktop.org/series/89862/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10057_full -> Patchwork_20082_full
== Series Details ==
Series: drm/i915/display: New Property Creation for HDMI
URL : https://patchwork.freedesktop.org/series/89872/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1ebc8dae44b2 drm/i915/display: New Property Creation for HDMI
-:51: CHECK:COMPARISON_TO_NULL: Compar
== Series Details ==
Series: drm/i915/stolen: shuffle around init_memory_region
URL : https://patchwork.freedesktop.org/series/89867/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10057 -> Patchwork_20085
Summary
---
spec@ext_transform_feedback@builtin-varyings gl_clipvertex (NEW):
This test is not available in CI bug log. So, I cannot re-report.
Lakshmi.
-Original Message-
From: Deak, Imre
Sent: Friday, May 7, 2021 2:36 AM
To: intel-gfx@lists.freedesktop.org; Roper, Matthew D
; Taylor, Clinton A ;
Commit fb5970da1b42 ("drm/i915/gt: Use the kernel_context to measure the
breadcrumb size") reordered some operations inside engine_init_common()
and added an error unwind path to that function. In that path, a
reference to a kernel context candidate supposed to be released on error
was put, but th
== Series Details ==
Series: drm/modifiers: Enforce consistency between the cap an IN_FORMATS
URL : https://patchwork.freedesktop.org/series/89864/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10057 -> Patchwork_20084
Summ
== Series Details ==
Series: drm/modifiers: Enforce consistency between the cap an IN_FORMATS
URL : https://patchwork.freedesktop.org/series/89864/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
55b04e272163 drm/modifiers: Enforce consistency between the cap an IN_FORMATS
-:8: W
Right now the HDMI properties like vendor and product ids are hardcoded
in the function "intel_hdmi_compute_spd_infoframe()".
ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx").
This patch enables the possibility of setting vendor and product id fields
of the Infoframe structure in t
Right now the HDMI properties like vendor and product ids are hardcoded
in the function "intel_hdmi_compute_spd_infoframe()".
ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx").
This patch enables the possibility of setting vendor and product id fields
of the Infoframe structure in
== Series Details ==
Series: drm/i915/display: relax 2big checking around initial fb
URL : https://patchwork.freedesktop.org/series/89863/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10057 -> Patchwork_20083
Summary
-
== Series Details ==
Series: drm/i915: Drop duplicate WaDisable4x2SubspanOptimization:hsw
URL : https://patchwork.freedesktop.org/series/89862/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10057 -> Patchwork_20082
Summary
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