From: Mika Kahola <mika.kah...@intel.com>
Disable loadgen sharing for DP link rate 1.62 GHz and HDMI 5.94 GHz.
For all other modes, we can enable loadgen sharing feature.
BSpec: 55359
Cc: Imre Deak <imre.d...@intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
Signed-off-by: Clinton Taylor <clinton.a.tay...@intel.com>
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index bbfa5bcd4c63..6889be6b9e81 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1470,6 +1470,14 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder
*encoder,
val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
val &= ~DKL_TX_DP20BITMODE;
intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
+
+ if ((intel_crtc_has_dp_encoder(crtc_state) &&
+ crtc_state->port_clock == 162000) ||
+ (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
+ crtc_state->port_clock == 594000))
+ val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
+ else
+ val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9a52711e3920..3afbea20bdd3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10893,6 +10893,7 @@ enum skl_power_gate {
_DKL_TX_DPCNTL1)
#define _DKL_TX_DPCNTL2 0x2C8
+#define DKL_TX_LOADGEN_SHARING_PMD_DISABLE REG_BIT(12)
#define DKL_TX_DP20BITMODE (1 << 2)
#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
_DKL_PHY1_BASE, \
--
2.25.4
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