Variations in OA formats in the different gens has led to creation of
several sparse arrays to store the formats.
Move oa formats into a single array and use format_mask to check for
platform specific oa formats.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 19 ++-
Validity of an OA format is checked by using a sparse array of formats
per gen. Instead maintain a mask of supported formats for a platform in
the perf object.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 64 +-
drivers/gpu/drm/i915/i9
Gen12 supports additional OA formats as compared to what was added
earlier. Include the additional OA formats.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b
On Mon, 18 Jan 2021, Jani Nikula wrote:
> The following commits have been marked as Cc: stable or fixing something
> in v5.11-rc4 or earlier, but failed to cherry-pick to
> drm-intel-fixes. Please see if they are worth backporting, and please do
> so if they are.
>
> Conflicts:
> dbe13ae1d6ab ("dr
On Tue, Feb 02, 2021 at 08:31:48AM +0200, Ville Syrjälä wrote:
> On Tue, Feb 02, 2021 at 05:52:28AM +, Surendrakumar Upadhyay, TejaskumarX
> wrote:
> >
> >
> > > -Original Message-
> > > From: Ville Syrjälä
> > > Sent: 28 January 2021 04:46
> > > To: Surendrakumar Upadhyay, Tejaskum
On Tue, Feb 02, 2021 at 12:09:47PM +0530, Nautiyal, Ankit K wrote:
> Hi Ville,
>
> Please find my responses inline.
>
> On 2/2/2021 2:08 AM, Ville Syrjälä wrote:
> > On Fri, Dec 18, 2020 at 04:07:17PM +0530, Ankit Nautiyal wrote:
> >> This patch adds functions to start FRL training for an HDMI2.1
Hi Ville,
Please find my responses inline.
On 2/2/2021 2:08 AM, Ville Syrjälä wrote:
On Fri, Dec 18, 2020 at 04:07:17PM +0530, Ankit Nautiyal wrote:
This patch adds functions to start FRL training for an HDMI2.1 sink,
connected via a PCON as a DP branch device.
This patch also adds a new struc
On Tue, Feb 02, 2021 at 05:52:28AM +, Surendrakumar Upadhyay, TejaskumarX
wrote:
>
>
> > -Original Message-
> > From: Ville Syrjälä
> > Sent: 28 January 2021 04:46
> > To: Surendrakumar Upadhyay, TejaskumarX
> >
> > Cc: intel-gfx@lists.freedesktop.org; Pandey, Hariom
> > ; Roper, M
On 2/2/2021 2:04 AM, Ville Syrjälä wrote:
On Mon, Feb 01, 2021 at 08:12:11PM -, Patchwork wrote:
== Series Details ==
Series: drm/i915: Clean up the DDI clock routing mess
URL : https://patchwork.freedesktop.org/series/86544/
State : failure
== Summary ==
CI Bug Log - changes from CI_D
> -Original Message-
> From: Ville Syrjälä
> Sent: 28 January 2021 04:46
> To: Surendrakumar Upadhyay, TejaskumarX
>
> Cc: intel-gfx@lists.freedesktop.org; Pandey, Hariom
> ; Roper, Matthew D
>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during
> suspend/resume
On 2021.01.21 13:33:18 -0700, Alex Williamson wrote:
> On Mon, 18 Jan 2021 20:38:34 +0800
> Fred Gao wrote:
>
> > Before opregion version 2.0 VBT data is stored in opregion mailbox #4,
> > However, When VBT data exceeds 6KB size and cannot be within mailbox #4
> > starting from opregion v2.0+, Ex
Hi Joonas,
Here are the changes to add basic Alder Lake S support in the driver, with
patches touching both generic parts, gt and display. Remaining changes don't
need a topic branch anymore and can be applied individually to each branch.
thanks
Lucas De Marchi
***
topic/adl-s-enabling-2021-02-
Hi Rodrigo/Jani,
Here are the changes to add basic Alder Lake S support in the driver, with
patches touching both generic parts, gt and display. Remaining changes don't
need a topic branch anymore and can be applied individually to each branch.
thanks
Lucas De Marchi
***
topic/adl-s-enabling-20
== Series Details ==
Series: drm/i915: Clean up the DDI clock routing mess
URL : https://patchwork.freedesktop.org/series/86544/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9713_full -> Patchwork_19556_full
Summary
--
> -Original Message-
> From: Chris Wilson
> Sent: Monday, February 1, 2021 3:22 PM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg1: Add GuC and HuC support
>
> Quoting Srivatsa, Anusha (2021-02-01 23:19:40)
> >
> >
> > >
== Series Details ==
Series: drm/i915/gt: Retire unexpected starting state error dumping
URL : https://patchwork.freedesktop.org/series/86542/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9713_full -> Patchwork_19555_full
== Series Details ==
Series: drm/i915/dg1: Add GuC and HuC support (rev2)
URL : https://patchwork.freedesktop.org/series/86482/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9713 -> Patchwork_19557
Summary
---
**FAIL
== Series Details ==
Series: drm/i915/vbt: update DP max link rate table
URL : https://patchwork.freedesktop.org/series/86539/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9713_full -> Patchwork_19554_full
Summary
---
Quoting Srivatsa, Anusha (2021-02-01 23:19:40)
>
>
> > -Original Message-
> > From: Chris Wilson
> > Sent: Monday, February 1, 2021 3:05 PM
> > To: Srivatsa, Anusha ; intel-
> > g...@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg1: Add GuC and HuC support
> >
> >
On 1/28/2021 7:00 PM, Xingyou Chen wrote:
> On 2021/1/27 上午5:46, Brian Welty wrote:
>
>> We'd like to revisit the proposal of a GPU cgroup controller for managing
>> GPU devices but with just a basic set of controls. This series is based on
>> the prior patch series from Kenny Ho [1]. We take
> -Original Message-
> From: Chris Wilson
> Sent: Monday, February 1, 2021 3:05 PM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg1: Add GuC and HuC support
>
> Quoting Anusha Srivatsa (2021-02-01 23:01:33)
> > Add support to
Quoting Anusha Srivatsa (2021-02-01 23:01:33)
> Add support to load GuC and HuC firmware for Dg1.
Do you have the corresponding link for the linux-firmware.git? That is
useful for cross referencing that the target version does exist in the
public repository.
-Chris
Add support to load GuC and HuC firmware for Dg1.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 984fa79e0fa7..0e63881674a4
For the whole series:
Reviewed-by: Lyude Paul
On Mon, 2021-02-01 at 14:01 +0200, Imre Deak wrote:
> Reporting a port as connected if nothing is attached to them leads to
> any i2c transactions on this port trying to use an uninitialized i2c
> adapter, fix this.
>
> Let's account for this case e
Re-reported.
-Original Message-
From: Ville Syrjälä
Sent: Monday, February 1, 2021 12:34 PM
To: intel-gfx@lists.freedesktop.org
Cc: Vudum, Lakshminarayana
Subject: Re: ✗ Fi.CI.BAT: failure for drm/i915: Clean up the DDI clock routing
mess
On Mon, Feb 01, 2021 at 08:12:11PM -, Patc
== Series Details ==
Series: drm/i915: Clean up the DDI clock routing mess
URL : https://patchwork.freedesktop.org/series/86544/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9713 -> Patchwork_19556
Summary
---
**SUC
On Fri, Dec 18, 2020 at 04:07:17PM +0530, Ankit Nautiyal wrote:
> This patch adds functions to start FRL training for an HDMI2.1 sink,
> connected via a PCON as a DP branch device.
> This patch also adds a new structure for storing frl training related
> data, when FRL training is completed.
>
> v
On Mon, Feb 01, 2021 at 08:12:11PM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Clean up the DDI clock routing mess
> URL : https://patchwork.freedesktop.org/series/86544/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_9713 -> Patchwork_19556
>
== Series Details ==
Series: drm/i915: Clean up the DDI clock routing mess
URL : https://patchwork.freedesktop.org/series/86544/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9713 -> Patchwork_19556
Summary
---
**FAI
== Series Details ==
Series: drm/i915: Clean up the DDI clock routing mess
URL : https://patchwork.freedesktop.org/series/86544/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i
== Series Details ==
Series: drm/i915: Clean up the DDI clock routing mess
URL : https://patchwork.freedesktop.org/series/86544/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
83a4bb6e6220 drm/i915: Extract icl_dpclka_cfgcr0_reg()
55c608204619 drm/i915: Extract icl_dpclka_cfgcr0
On Mon, Feb 01, 2021 at 09:31:49PM +0200, Ville Syrjälä wrote:
> On Mon, Feb 01, 2021 at 11:22:39AM -0800, Lucas De Marchi wrote:
> > On Mon, Feb 01, 2021 at 08:33:41PM +0200, Ville Syrjälä wrote:
> > >From: Ville Syrjälä
> > >
> > >Since .{enable,disable}_clock() are already vfuncs it's a bit sil
== Series Details ==
Series: series starting with [01/57] drm/i915/gt: Restrict the GT clock
override to just Icelake
URL : https://patchwork.freedesktop.org/series/86521/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9712_full -> Patchwork_19551_full
On Mon, Feb 01, 2021 at 11:22:39AM -0800, Lucas De Marchi wrote:
> On Mon, Feb 01, 2021 at 08:33:41PM +0200, Ville Syrjälä wrote:
> >From: Ville Syrjälä
> >
> >Since .{enable,disable}_clock() are already vfuncs it's a bit silly to
> >have if-ladders inside them. Just provide specialized version fo
On Mon, Feb 01, 2021 at 08:33:28PM +0200, Ville Syrjälä wrote:
From: Ville Syrjälä
The DDI clock routing code has turned into proper spaghetti.
Attempt to clean it up by introducing some new vfuncs.
A few minors I replied in the series. The move back and forth from one
approach to the other I
On Mon, Feb 01, 2021 at 08:33:41PM +0200, Ville Syrjälä wrote:
From: Ville Syrjälä
Since .{enable,disable}_clock() are already vfuncs it's a bit silly to
have if-ladders inside them. Just provide specialized version for adlp
and rkl so we don't need any of that.
s/alds/adl-s/
s/adlp/adl-s/
On Mon, Feb 01, 2021 at 11:15:01AM -0800, Lucas De Marchi wrote:
> On Mon, Feb 01, 2021 at 08:33:38PM +0200, Ville Syrjälä wrote:
> >From: Ville Syrjälä
> >
> >The current code attempts to protect the RMWs into global
> >clock routing registers with a mutex, but forgets to do so
> >in a few places
On Mon, Feb 01, 2021 at 11:07:20AM -0800, Lucas De Marchi wrote:
> On Mon, Feb 01, 2021 at 08:33:32PM +0200, Ville Syrjälä wrote:
> >From: Ville Syrjälä
> >
> >Yank out the HSW/BDW code from intel_ddi_clk_{select,disable}()
> >and put it into the new encoder .{enable,disable}_clock() vfuncs.
> >
>
On Mon, Feb 01, 2021 at 08:33:39PM +0200, Ville Syrjälä wrote:
From: Ville Syrjälä
The other DDI .enable_clock() functions are trying to protect us
against pll==NULL. A bit tempted to throw out all the WARNs as
just unnecessary noise, but I guess they might have some use
when poking around the
On Mon, Feb 01, 2021 at 08:33:38PM +0200, Ville Syrjälä wrote:
From: Ville Syrjälä
The current code attempts to protect the RMWs into global
clock routing registers with a mutex, but forgets to do so
in a few places. Let's remedy that.
Forgets or doesn't do on purpose? In the first patches in
On January 29, 2021 05:42:47 Maarten Lankhorst
wrote:
Op 28-01-2021 om 17:47 schreef Jason Ekstrand:
On Thu, Jan 28, 2021 at 10:26 AM Maarten Lankhorst
wrote:
There are a couple of ioctl's related to tiling and cache placement,
that make no sense for userptr, reject those:
- i915_gem_set_ti
On Mon, Feb 01, 2021 at 11:04:40AM -0800, Lucas De Marchi wrote:
> On Mon, Feb 01, 2021 at 08:33:31PM +0200, Ville Syrjälä wrote:
> >From: Ville Syrjälä
> >
> >The current code dealing with the clock routing for DDI encoders
> >is a maintenance nightmare. Let's start cleaning it up by allowing
> >
On Mon, Feb 01, 2021 at 08:33:32PM +0200, Ville Syrjälä wrote:
From: Ville Syrjälä
Yank out the HSW/BDW code from intel_ddi_clk_{select,disable}()
and put it into the new encoder .{enable,disable}_clock() vfuncs.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 32 +
== Series Details ==
Series: drm/i915/gt: Retire unexpected starting state error dumping
URL : https://patchwork.freedesktop.org/series/86542/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9713 -> Patchwork_19555
Summary
--
On Mon, Feb 01, 2021 at 08:33:31PM +0200, Ville Syrjälä wrote:
From: Ville Syrjälä
The current code dealing with the clock routing for DDI encoders
is a maintenance nightmare. Let's start cleaning it up by allowing
the encoder to provide vfuncs for enablign/disabling the clock.
We leave them i
On Mon, Feb 01, 2021 at 08:33:30PM +0200, Ville Syrjälä wrote:
From: Ville Syrjälä
Extract some helpers to calculate the correct CLK_SEL values
for DPCLKA_CFGCR.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 39 +++-
1 file changed, 25 insertio
On Mon, Feb 01, 2021 at 08:33:29PM +0200, Ville Syrjälä wrote:
From: Ville Syrjälä
Extract the code to determine the DPCLK_CFGCR register
to use.
Signed-off-by: Ville Syrjälä
Reviewed-by: Lucas De Marchi
Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 28 ++--
From: Ville Syrjälä
Move icl_sanitize_encoder_pll_mapping() out from the middle
of the .{enable,disable}_clock() functions.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 112 +++
1 file changed, 56 insertions(+), 56 deletions(-)
diff --git a/d
From: Ville Syrjälä
Instead of every new platform having yet another masive
copy of the whole PLL sanitation code, let's just reuse the
.disable_clock() hook for this purpose. We do need to plug
this into the ICL+ DSI code for that, but fortunately it
already has a suitable function we can use.
From: Ville Syrjälä
Since .{enable,disable}_clock() are already vfuncs it's a bit silly to
have if-ladders inside them. Just provide specialized version for adlp
and rkl so we don't need any of that.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 93 +++
From: Ville Syrjälä
All the DPCLKA_CFGCR handling follows a common pattern. Let's
extract that to a small helper that just takes a few parameters
each caller can customize.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 112 ++-
1 file changed,
From: Ville Syrjälä
The other DDI .enable_clock() functions are trying to protect us
against pll==NULL. A bit tempted to throw out all the WARNs as
just unnecessary noise, but I guess they might have some use
when poking around the shared_dpll code (not sure it wouldn't
oops elsewhere though). So
From: Ville Syrjälä
The current code attempts to protect the RMWs into global
clock routing registers with a mutex, but forgets to do so
in a few places. Let's remedy that.
Note that at the moment we serialize all modesets onto single
wq, so this shouldn't actually matter. But maybe one day we
w
From: Ville Syrjälä
The DDI clock routing programming is riddled with shared
registers, forcing us to do a lot of RMW. Switch over to
intel_de_rmw() to make that a bit less obnoxious.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 78 +---
1 fil
From: Ville Syrjälä
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just ne
From: Ville Syrjälä
Replace dg1_{map,unmap}_plls_to_ports() with the appropriate
encoder vfuncs. And let's relocate the disable function next to
the enable function while at it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 43
1 file chan
From: Ville Syrjälä
Extract the DDI clock routing for CNL into the new vfuncs.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 62
1 file changed, 42 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/dr
From: Ville Syrjälä
Extract the DDI clock routing clode for skl/derivatives
into the new encoder vfuncs.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 53 +---
1 file changed, 38 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915
From: Ville Syrjälä
Yank out the HSW/BDW code from intel_ddi_clk_{select,disable}()
and put it into the new encoder .{enable,disable}_clock() vfuncs.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 32 +++-
1 file changed, 26 insertions(+), 6 del
From: Ville Syrjälä
The current code dealing with the clock routing for DDI encoders
is a maintenance nightmare. Let's start cleaning it up by allowing
the encoder to provide vfuncs for enablign/disabling the clock.
We leave them initially unimplemented, falling back to the old
if-else approach.
From: Ville Syrjälä
Extract some helpers to calculate the correct CLK_SEL values
for DPCLKA_CFGCR.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 39 +++-
1 file changed, 25 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/displ
From: Ville Syrjälä
Extract the code to determine the DPCLK_CFGCR register
to use.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 28 ++--
1 file changed, 12 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
From: Ville Syrjälä
The DDI clock routing code has turned into proper spaghetti.
Attempt to clean it up by introducing some new vfuncs.
Ville Syrjälä (15):
drm/i915: Extract icl_dpclka_cfgcr0_reg()
drm/i915: Extract icl_dpclka_cfgcr0_clk_sel*()
drm/i915: Introduce .{enable,disable}_clock()
== Series Details ==
Series: drm/i915/vbt: update DP max link rate table
URL : https://patchwork.freedesktop.org/series/86539/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9713 -> Patchwork_19554
Summary
---
**SUCCE
On 2/1/21 1:14 AM, Stephen Rothwell wrote:
> Hi all,
>
> Changes since 20210129:
>
still seeing this one:
on x86_64:
../drivers/gpu/drm/i915/i915_gem.c: In function ‘i915_gem_freeze_late’:
../drivers/gpu/drm/i915/i915_gem.c:1182:2: error: implicit declaration of
function ‘wbinvd_on_all_cpus’;
== Series Details ==
Series: drm/i915: Remove obj->mm.lock! (rev15)
URL : https://patchwork.freedesktop.org/series/82337/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9712 -> Patchwork_19553
Summary
---
**FAILURE**
We have not seen an occurrence of the false restart state recenty, and if
we did such an event from inside engine-reset, it would deadlock on
trying to suspend the tasklet to read the register state. Instead, we
inspect the context state before submission which will alert us to any
issues prior to
Chris Wilson writes:
> Verify that one context running on engine A cannot manipulate another
> client's context concurrently running on engine B using unprivileged
> access.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 275 +
> 1 file
On Thu, 2021-01-28 at 08:05 +, Patchwork wrote:
Patch Details
Series: Final set of patches for ADLS enabling (rev2)
URL:https://patchwork.freedesktop.org/series/86322/
State: success
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19525/index.html
CI Bug Log - changes f
== Series Details ==
Series: drm/i915: Remove obj->mm.lock! (rev15)
URL : https://patchwork.freedesktop.org/series/82337/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter
or member 'ww' n
== Series Details ==
Series: drm/i915: Remove obj->mm.lock! (rev15)
URL : https://patchwork.freedesktop.org/series/82337/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/gt/in
== Series Details ==
Series: drm/i915: Remove obj->mm.lock! (rev15)
URL : https://patchwork.freedesktop.org/series/82337/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7875c5f4807c drm/i915: Do not share hwsp across contexts any more, v7.
-:562: WARNING:CONSTANT_COMPARISON: Com
== Series Details ==
Series: drm/i915/selftests: Use a single copy of the mocs table
URL : https://patchwork.freedesktop.org/series/86525/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9712 -> Patchwork_19552
Summary
--
According to Bspec #20124, max link rate table for DP was updated
at BDB version 230. Max link rate can support upto UHBR.
After migrate to BDB v230, the definition for LBR, HBR2 and HBR3
were changed. For backward compatibility. If BDB version was
from 216 to 229. Driver have to follow original r
== Series Details ==
Series: series starting with [01/57] drm/i915/gt: Restrict the GT clock
override to just Icelake
URL : https://patchwork.freedesktop.org/series/86521/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9712 -> Patchwork_19551
==
Chris Wilson writes:
> Verify that context isolation is also preserved when accessing
> context-local registers with relative-mmio commands.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 88 --
> 1 file cha
Chris Wilson writes:
> It appears that Elkhart Lake uses the same clock for CTX_TIMESTAMP as
> CS_TIMESTAMP, leaving Icelake as the odd one out.
I am repeating myself: weird.
...but true.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3024
> Signed-off-by: Chris Wilson
Reviewed
== Series Details ==
Series: series starting with [01/57] drm/i915/gt: Restrict the GT clock
override to just Icelake
URL : https://patchwork.freedesktop.org/series/86521/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't
== Series Details ==
Series: series starting with [01/57] drm/i915/gt: Restrict the GT clock
override to just Icelake
URL : https://patchwork.freedesktop.org/series/86521/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
02ff187efe58 drm/i915/gt: Restrict the GT clock override to
Quoting Maarten Lankhorst (2021-02-01 12:50:37)
> Make creation separate from pinning, in order to take the lock only
> once, and pin the mapping with the lock held.
>
> Changes since v1:
> - Rebase on top of upstream changes.
> Changes since v2:
> - Fully clear wa_ctx on error.
>
> Signed-off-by
On 2/1/21 1:50 PM, Maarten Lankhorst wrote:
Make creation separate from pinning, in order to take the lock only
once, and pin the mapping with the lock held.
Changes since v1:
- Rebase on top of upstream changes.
Changes since v2:
- Fully clear wa_ctx on error.
Signed-off-by: Maarten Lankhorst
On 1/29/21 2:11 PM, Maarten Lankhorst wrote:
In reloc_iomap we swallow the -EDEADLK error, but this needs to
be returned for -EDEADLK handling. Add the missing check to
make bsw pass again.
Testcase: gem_exec_fence.basic-await
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i9
On Sat, Jan 30, 2021 at 9:45 AM Chris Wilson wrote:
>
> Quoting Vinicius Tinti (2021-01-30 12:34:11)
> > On Fri, Jan 29, 2021 at 08:55:54PM +, Chris Wilson wrote:
> > > Quoting Vinicius Tinti (2021-01-29 18:15:19)
> > > > By enabling -Wunreachable-code-aggressive on Clang the following code
>
Make creation separate from pinning, in order to take the lock only
once, and pin the mapping with the lock held.
Changes since v1:
- Rebase on top of upstream changes.
Changes since v2:
- Fully clear wa_ctx on error.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/g
Quoting Tvrtko Ursulin (2021-02-01 11:57:56)
> From: Tvrtko Ursulin
>
> Slight improvement with regards to wrapping header components to fit
> console width. If a single element is wider than max it can still
> overflow but it should now work better for practical console widths.
<
intel-gpu-
Reporting a port as connected if nothing is attached to them leads to
any i2c transactions on this port trying to use an uninitialized i2c
adapter, fix this.
Let's account for this case even if branch devices have no good reason
to report a port as unplugged with their peer device type set to 'non
From: Tvrtko Ursulin
Slight improvement with regards to wrapping header components to fit
console width. If a single element is wider than max it can still
overflow but it should now work better for practical console widths.
Signed-off-by: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 84
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Monday, February 1, 2021 4:25 PM
> To: Gupta, Anshuman ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/debugfs: HDCP capability enc NULL
> check
>
>
> On 1/29/2021 1:30 PM, Anshuman Gupta wrote:
>
Quoting Tvrtko Ursulin (2021-02-01 10:45:23)
> From: Tvrtko Ursulin
>
> Allow hiding inactive clients (used no GPU time ever) in interactive mode
> by pressing 'i'.
>
> Signed-off-by: Tvrtko Ursulin
Ok, that's where you meant. Coffee not winning the battle today.
Reviewed-by: Chris Wilson
-C
Quoting Tvrtko Ursulin (2021-02-01 10:45:22)
> From: Tvrtko Ursulin
>
> Document numeric busyness overlay and sort selection.
I looked for a 'h' or '?' screen.
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.or
On 1/29/2021 1:30 PM, Anshuman Gupta wrote:
DP-MST connector encoder initializes at modeset
Adding a connector->encoder NULL check in order to
avoid any NULL pointer dereference.
intel_hdcp_enable() already handle this but debugfs
can also invoke the intel_{hdcp,hdcp2_capable}.
Handling it grac
Quoting Tvrtko Ursulin (2021-02-01 10:45:24)
> From: Tvrtko Ursulin
>
> Client stats refactoring broke the header layout with an extra newline.
Argh; keep the newline, or at least check the terminal width and make
the newline conditional.
-Chris
___
In
From: Tvrtko Ursulin
Client stats refactoring broke the header layout with an extra newline.
Signed-off-by: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index dffc6ebecc57..9b8302de54d
From: Tvrtko Ursulin
Allow hiding inactive clients (used no GPU time ever) in interactive mode
by pressing 'i'.
Signed-off-by: Tvrtko Ursulin
---
man/intel_gpu_top.rst | 1 +
tools/intel_gpu_top.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/man/intel_gpu_top.rst b/man/intel_gpu
From: Tvrtko Ursulin
Document numeric busyness overlay and sort selection.
Signed-off-by: Tvrtko Ursulin
---
man/intel_gpu_top.rst | 2 ++
1 file changed, 2 insertions(+)
diff --git a/man/intel_gpu_top.rst b/man/intel_gpu_top.rst
index 35ab10da9bb4..b18fd9675bb7 100644
--- a/man/intel_gpu_top
On Fri, 29 Jan 2021, Ville Syrjälä wrote:
> On Wed, Jan 27, 2021 at 10:45:34AM +0200, Jani Nikula wrote:
>> Make the child device details easier to read by turning this:
>>
>> [drm:parse_ddi_port [i915]] Port B VBT info: CRT:0 DVI:1 HDMI:1 DP:0 eDP:0
>> LSPCON:0 USB-Type-C:0 TBT:0 DSC:0
>> [drm:
On 01/02/2021 09:57, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2021-02-01 09:53:20)
On 01/02/2021 09:31, Chris Wilson wrote:
Hide inactive clients by pressing 'i' (toggle in interactive mode).
v2: Fix location of filter_idle.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by:
Instead of copying the whole table to each category (mocs, l3cc), use a
single table with a pointer to it if the category is enabled.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_mocs.c | 32 +
1 file changed, 22 insertions(+), 10 deletions(-)
diff --
Quoting Tvrtko Ursulin (2021-02-01 09:53:20)
>
> On 01/02/2021 09:31, Chris Wilson wrote:
> > Hide inactive clients by pressing 'i' (toggle in interactive mode).
> >
> > v2: Fix location of filter_idle.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Tvrtko Ursulin
> > Reviewed-by: Tvrtko Ursulin
On 01/02/2021 09:31, Chris Wilson wrote:
Hide inactive clients by pressing 'i' (toggle in interactive mode).
v2: Fix location of filter_idle.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 9 +
1 file changed, 9 insertions(
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