On Mon, Feb 01, 2021 at 08:33:29PM +0200, Ville Syrjälä wrote:
From: Ville Syrjälä <ville.syrj...@linux.intel.com>
Extract the code to determine the DPCLK_CFGCR register
to use.
Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Reviewed-by: Lucas De Marchi <lucas.demar...@intel.com>
Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 28 ++++++++++--------------
1 file changed, 12 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 5bc5033a2dea..a3aeb1c2821c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3127,6 +3127,15 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct
drm_i915_private *dev_priv,
return 0;
}
+static i915_reg_t icl_dpclka_cfgcr0_reg(struct drm_i915_private *i915,
+ enum phy phy)
+{
+ if (IS_ALDERLAKE_S(i915))
+ return ADLS_DPCLKA_CFGCR(phy);
+ else
+ return ICL_DPCLKA_CFGCR0;
+}
+
static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -3167,19 +3176,16 @@ static void icl_map_plls_to_ports(struct intel_encoder
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy);
u32 val, mask, sel;
- i915_reg_t reg;
if (IS_ALDERLAKE_S(dev_priv)) {
- reg = ADLS_DPCLKA_CFGCR(phy);
mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
sel = ((pll->info->id) << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
} else if (IS_ROCKETLAKE(dev_priv)) {
- reg = ICL_DPCLKA_CFGCR0;
mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
} else {
- reg = ICL_DPCLKA_CFGCR0;
mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
}
@@ -3230,16 +3236,11 @@ static void icl_unmap_plls_to_ports(struct
intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy);
u32 val;
- i915_reg_t reg;
mutex_lock(&dev_priv->dpll.lock);
- if (IS_ALDERLAKE_S(dev_priv))
- reg = ADLS_DPCLKA_CFGCR(phy);
- else
- reg = ICL_DPCLKA_CFGCR0;
-
val = intel_de_read(dev_priv, reg);
val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
@@ -3285,15 +3286,10 @@ static void icl_sanitize_port_clk_off(struct
drm_i915_private *dev_priv,
enum port port;
bool ddi_clk_off;
u32 val;
- i915_reg_t reg;
for_each_port_masked(port, port_mask) {
enum phy phy = intel_port_to_phy(dev_priv, port);
-
- if (IS_ALDERLAKE_S(dev_priv))
- reg = ADLS_DPCLKA_CFGCR(phy);
- else
- reg = ICL_DPCLKA_CFGCR0;
+ i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy);
val = intel_de_read(dev_priv, reg);
ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
--
2.26.2
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