== Series Details ==
Series: drm/i915: Do not call hsw_set_frame_start_delay for dsi (rev3)
URL : https://patchwork.freedesktop.org/series/84039/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9364_full -> Patchwork_18947_full
===
== Series Details ==
Series: drm/i915/gt: Plug IPS into intel_rps_set (rev2)
URL : https://patchwork.freedesktop.org/series/84081/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9364_full -> Patchwork_18946_full
Summary
== Series Details ==
Series: Re-enable FBC on TGL (rev3)
URL : https://patchwork.freedesktop.org/series/83510/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9364_full -> Patchwork_18945_full
Summary
---
**SUCCESS**
== Series Details ==
Series: i915/gem_flink_race.c: Use statistics over list of numbers
URL : https://patchwork.freedesktop.org/series/84084/
State : failure
== Summary ==
Applying: i915/gem_flink_race.c: Use statistics over list of numbers
error: sha1 information is lacking or useless (tests/
Print median and range instead of a list of numbers in function test_flink_name.
Signed-off-by: Steve Hampson
---
tests/i915/gem_flink_race.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/tests/i915/gem_flink_race.c b/tests/i915/gem_flink_race.c
index cf
On Thu, Nov. 19, 2020 at 11:51 PM, Matt Roper wrote:
>On Tue, Nov 17, 2020 at 10:26:29PM +0800, Lee Shawn C wrote:
>> After boot into kernel. Driver configured ddc pin mapping based on
>> predefined table in parse_ddi_port(). Now driver configure rkl ddc pin
>> mapping depends on icp_ddc_pin_map[
== Series Details ==
Series: drm/i915: Do not call hsw_set_frame_start_delay for dsi (rev3)
URL : https://patchwork.freedesktop.org/series/84039/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9364 -> Patchwork_18947
Summary
On Tue, Nov 17, 2020 at 10:50:19AM -0800, Aditya Swarup wrote:
> ADL-S requires TC pins to set up ddc for Combo PHY B, C, D and E.
> Combo PHY A still uses the old ddc pin mapping.
>
> From VBT, ddc pin info suggests the following mapping:
> VBT DRIVER
> DDI B->ddc
On Tue, Nov 17, 2020 at 10:50:18AM -0800, Aditya Swarup wrote:
> Initialize display outputs and add HTI support for ADL-S. ADL-S has 5
> display outputs -> 1 eDP, 2 HDMI and 2 DP++ outputs.
>
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Cc: Matt Roper
> Cc: Lucas De Marchi
> Signed
== Series Details ==
Series: drm/i915/gt: Plug IPS into intel_rps_set (rev2)
URL : https://patchwork.freedesktop.org/series/84081/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9364 -> Patchwork_18946
Summary
---
**S
On Tue, Nov 17, 2020 at 10:50:15AM -0800, Aditya Swarup wrote:
> From: Anusha Srivatsa
>
> Alderlake-S has 5 combo phys, add reg definitions for
> combo phys and update the port to phy helper for ADL-S.
>
> Cc: Lucas De Marchi
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Cc: Matt
On Tue, Nov 17, 2020 at 10:50:14AM -0800, Aditya Swarup wrote:
> From: Anusha Srivatsa
>
> ADLS follows ICP/TGP like interrupts.
>
> v2: Use "INTEL_PCH_TYPE(dev_priv) >= PCH_ICP" of hpd_icp (Lucas)
>
> Cc: Lucas De Marchi
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Cc: Matt Rope
On Tue, Nov 17, 2020 at 10:50:13AM -0800, Aditya Swarup wrote:
> From: Anusha Srivatsa
>
> Add support for Alderpoint(ADP) PCH used with Alderlake-S.
>
> v2:
> - Use drm_dbg_kms and drm_WARN_ON based on Jani's feedback.(aswarup)
>
This patch looks okay, so
Reviewed-by: Matt Roper
but I'll h
On Tue, Nov 17, 2020 at 10:26:29PM +0800, Lee Shawn C wrote:
> After boot into kernel. Driver configured ddc pin mapping based on
> predefined table in parse_ddi_port(). Now driver configure rkl
> ddc pin mapping depends on icp_ddc_pin_map[]. Then this table will
> give incorrect gmbus port number
== Series Details ==
Series: Re-enable FBC on TGL (rev3)
URL : https://patchwork.freedesktop.org/series/83510/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9364 -> Patchwork_18945
Summary
---
**SUCCESS**
No regre
On Thu, Nov 19, 2020 at 03:26:15PM -0800, Manasi Navare wrote:
> This should fix the boot oops for dsi
>
> v2:
> * Fix indent (Manasi)
> v3:
> * Remove redundant condition (Matt Roper)
>
> Fixes: 4e3cdb4535e7 ("drm/i915/dp: Master/Slave enable/disable sequence for
> bigjoiner")
> Signed-off-by:
This should fix the boot oops for dsi
v2:
* Fix indent (Manasi)
v3:
* Remove redundant condition (Matt Roper)
Fixes: 4e3cdb4535e7 ("drm/i915/dp: Master/Slave enable/disable sequence for
bigjoiner")
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 8 +++-
1 fi
On Thu, Nov 19, 2020 at 10:20:57AM -0800, Manasi Navare wrote:
> This should fix the boot oops for dsi
>
> v2:
> * Fix indent (Manasi)
>
> Fixes: 4e3cdb4535e7 ("drm/i915/dp: Master/Slave enable/disable sequence for
> bigjoiner")
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/displ
The old IPS interface did not match the RPS interface that we tried to
plug it into (bool vs int return). Once repaired, our minimal
selftesting is finally happy!
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_rps.c | 34 +++--
1 file changed, 22 insertions
The old IPS interface did not match the RPS interface that we tried to
plug it into (bool vs int return). Once repaired, our minimal
selftesting is finally happy!
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_rps.c | 18 ++
1 file changed, 10 insertions(+), 8 dele
== Series Details ==
Series: drm/i915: Clean up the plane data_rate stuff
URL : https://patchwork.freedesktop.org/series/84075/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9362_full -> Patchwork_18944_full
Summary
---
== Series Details ==
Series: drm/i915: Do not call hsw_set_frame_start_delay for dsi (rev2)
URL : https://patchwork.freedesktop.org/series/84039/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9362_full -> Patchwork_18943_full
===
Hi Dave and Daniel,
Here goes another round for 5.10
drm-intel-fixes-2020-11-19:
- Fix tgl power gating issue (Rodrigo)
- Memory leak fixes (Tvrtko, Chris)
- Selftest fixes (Zhang)
- Display bpc fix (Ville)
- Fix TGL MOCS for PTE tracking (Chris)
GVT Fixes: It temporarily disables VFIO edid
feat
== Series Details ==
Series: drm/i915: Clean up the plane data_rate stuff
URL : https://patchwork.freedesktop.org/series/84075/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9362 -> Patchwork_18944
Summary
---
**SUCC
Pushed to dinq
Manasi
On Thu, Nov 19, 2020 at 09:07:17AM +, Chris Wilson wrote:
> drivers/gpu/drm/i915/display/intel_display.c:3634
> intel_find_initial_plane_obj() warn: inconsistent indenting
> drivers/gpu/drm/i915/display/intel_display.c:15367 kill_bigjoiner_slave()
> warn: inconsistent
On Thu, Nov 19, 2020 at 09:07:17AM +, Chris Wilson wrote:
> drivers/gpu/drm/i915/display/intel_display.c:3634
> intel_find_initial_plane_obj() warn: inconsistent indenting
> drivers/gpu/drm/i915/display/intel_display.c:15367 kill_bigjoiner_slave()
> warn: inconsistent indenting
>
> Signed-of
== Series Details ==
Series: drm/i915: Clean up the plane data_rate stuff
URL : https://patchwork.freedesktop.org/series/84075/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c0d1ad9d577b drm/i915: Drop pointless total_data_rate argument
076ed52a6259 drm/i915: Drop pointless dev
== Series Details ==
Series: drm/i915: Do not call hsw_set_frame_start_delay for dsi (rev2)
URL : https://patchwork.freedesktop.org/series/84039/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9362 -> Patchwork_18943
Summary
There are some corner cases wrt underrun when we enable
FBC with PSR2 on TGL. Recommendation from hardware is to
keep this combination disabled.
Bspec: 50422 HSD: 14010260002
v2: Added psr2 enabled check from crtc_state (Anshuman)
Added Bspec link and HSD referneces (Jose)
v3: Moved the logic to
From: Ville Syrjälä
There's really no need to maintain these total[] arrays to
track the size of each plane's ddb allocation. We just stick
the results straight into the crtc_state ddb tracking structures.
The main annoyance with all this is the mismatch between
wm_uv vs. ddb_y on pre-icl. If on
From: Ville Syrjälä
Handle the plane relative data rate in exactly the same
way as we already handle the real data rate. Ie. pre-calculate
it during intel_plane_atomic_check_with_state(), and assign/clear
it for the Y plane as needed. This should guarantee that the
tracking is 100% consistent, an
From: Ville Syrjälä
Replace the hand rolled pfit downscale calculations with
intel_adjusted_rate().
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 6 ++---
.../gpu/drm/i915/display/intel_atomic_plane.h | 4
drivers/gpu/drm/i915/display/intel_display.c
From: Ville Syrjälä
Rename a bunch of the skl+ watermark struct members to
have sensible names. Avoids me having to think what
plane_res_b/etc. means.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 48 ++---
.../drm/i915/display/intel_display_types.h| 6
From: Ville Syrjälä
Split the currently combined plane data_rate into the proper
Y vs. CbCr components. This matches how we now track the
plane dbuf allocations, and thus will make the dbuf bandwidth
calculations actually produce the correct numbers for each
dbuf slice.
Signed-off-by: Ville Syrj
From: Ville Syrjälä
Extract a small helper to calculate the downscaling
adjusted pixel rate/data rate/etc.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 27 +--
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i91
From: Ville Syrjälä
Extract the dbuf slice data_rate calculation into a small
helper. Should make it a bit easier to handle the different
color planes of planar formats correctly.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 81 ++---
1 file ch
From: Ville Syrjälä
Let's store the plane allocation in a manner which more closely
matches how the hw operates. That is, we store the packed/CbCr
ddb in one struct, and the Y ddb in another. Currently we're
storing packed/Y in one struct, CbCr in the other.
This also works pretty well for icl+
From: Ville Syrjälä
Replace some copy-pasta with a function.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 35 -
1 file changed, 21 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.
From: Ville Syrjälä
Collect a bit of the stuff used during the plane ddb
allocation into a struct we can pass around.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 94 -
1 file changed, 47 insertions(+), 47 deletions(-)
diff --git a/drivers
From: Ville Syrjälä
Extract a small helper to populate a ddb entry.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 48 +
1 file changed, 25 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/in
From: Ville Syrjälä
skl_ddb_entry_init_from_hw() has no need for dev_priv.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 84
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, November 19, 2020 9:12 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v2 1/2] drm/i915/display/tgl: Disable FBC with PSR2
>
> On Thu, Nov 19, 2020 at 09:20:49PM +0530, Uma Shankar wrote:
> > Ther
From: Ville Syrjälä
Let's sort out the plane data_rate stuff properly by
accounting each color plane independently. And we reuse the same
code and approach for the relative data rate (which is used for
plane ddb allocation).
Currently it's not even obvious if the relative data rate is
really cor
From: Ville Syrjälä
skl_ddb_get_pipe_allocation_limits() has no need for
the total relative data rate.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a
Quoting Hampson, Steven T (2020-11-19 18:18:14)
> Chris,
>
> Is this acceptable? Can it be merged?
It is of little use to print out that many numbers, so lets not and just
show some statistics instead as this is just meant to be a guide to the
reader as to whether the threads each received a rea
== Series Details ==
Series: series starting with [CI,1/6] drm/i915/gt: Include semaphore status in
print_request()
URL : https://patchwork.freedesktop.org/series/84073/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9362 -> Patchwork_18942
This should fix the boot oops for dsi
v2:
* Fix indent (Manasi)
Fixes: 4e3cdb4535e7 ("drm/i915/dp: Master/Slave enable/disable sequence for
bigjoiner")
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --gi
Chris,
Is this acceptable? Can it be merged?
-Original Message-
From: Hampson, Steven T
Sent: Wednesday, November 18, 2020 12:41 PM
To: 'Chris Wilson'
Cc: intel-gfx@
Subject: RE: [Intel-gfx] [PATCH] i915/gem_flink_race: Fix error in buffer usage
The problem is that the machine it was
Quoting Tvrtko Ursulin (2020-11-19 18:08:49)
>
> On 19/11/2020 16:56, Chris Wilson wrote:
> > Include the active timelines for debugfs/i915_engine_info, so that we
> > can see which have unready requests inflight which are not shown
> > otherwise.
> >
> > Suggested-by: Tvrtko Ursulin
> > Signed-
On 19/11/2020 16:56, Chris Wilson wrote:
Include the active timelines for debugfs/i915_engine_info, so that we
can see which have unready requests inflight which are not shown
otherwise.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Chris Wilson
Reviewd-by: Chris Wilson
Wrong paste, I belie
== Series Details ==
Series: series starting with [CI,1/6] drm/i915/gt: Include semaphore status in
print_request()
URL : https://patchwork.freedesktop.org/series/84073/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
93a1f698eabf drm/i915/gt: Include semaphore status in print_r
== Series Details ==
Series: Re-enable FBC on TGL (rev2)
URL : https://patchwork.freedesktop.org/series/83510/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9362 -> Patchwork_18941
Summary
---
**FAILURE**
Serious
== Series Details ==
Series: drm/i915/gt: Update request status flags for debug pretty-printer (rev2)
URL : https://patchwork.freedesktop.org/series/84061/
State : failure
== Summary ==
Applying: drm/i915/gt: Update request status flags for debug pretty-printer
error: sha1 information is lacki
Include the active timelines for debugfs/i915_engine_info, so that we
can see which have unready requests inflight which are not shown
otherwise.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Chris Wilson
Reviewd-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_timeline.c | 80
We plan to expand upon the number of available statuses for when we
pretty-print the requests along the timelines, and so need a new set of
flags. We have settled upon:
Unready [U]
- initial status after being submitted, the request is not
ready for execution as it is
Extract i915_request_show for reuse in other request chain pretty
printers.
For a bonus point, quietly change the seqno format from %llx to %lld to
match everywhere else.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 47 ++--
From: Tvrtko Ursulin
Include the signalers each request in the timeline is waiting on, as a
means to try and identify the cause of a stall. This can be quite
verbose, even as for now we only show each request in the timeline and
its immediate antecedents.
This generates output like:
Timeline 88
Lift the list iteration defines for traversing the signaler/waiter lists
into i915_scheduler.h for reuse.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 10 --
drivers/gpu/drm/i915/i915_scheduler_types.h | 10 ++
2 files
When pretty-printing the requests for debug, also show the status of any
semaphore waits as part of its runnable status.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/
On 19/11/2020 14:22, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-11-19 14:06:00)
On 18/11/2020 12:10, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-11-18 11:38:43)
On 18/11/2020 11:24, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-11-18 11:05:24)
On 17/11/2020 11:30, Chris Wi
On Thu, Nov 19, 2020 at 09:20:49PM +0530, Uma Shankar wrote:
> There are some corner cases wrt underrun when we enable
> FBC with PSR2 on TGL. Recommendation from hardware is to
> keep this combination disabled.
>
> Bspec: 50422 HSD: 14010260002
>
> v2: Added psr2 enabled check from crtc_state (A
FBC can be re-enabled on TGL with WA of keeping it disabled
while PSR2 is enabled.
This reverts commit 2982ded2ff5ce0cf1a49bc39a526da182782b664.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_fbc.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915
There are some corner cases wrt underrun when we enable
FBC with PSR2 on TGL. Recommendation from hardware is to
keep this combination disabled.
Bspec: 50422 HSD: 14010260002
v2: Added psr2 enabled check from crtc_state (Anshuman)
Added Bspec link and HSD referneces (Jose)
Signed-off-by: Uma Sha
FBC was disabled on TGL due to random underruns. It has
been determined that FBC will not work reliably with PSR2.
This series re-enables fbc along with taking care of the
PSR2 limitations for TGL.
Bspec: 50422 HSD: 14010260002
v2: Addressed review comments and added bspec links
Uma Shankar (2):
Quoting Tvrtko Ursulin (2020-11-19 14:06:00)
>
> On 18/11/2020 12:10, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2020-11-18 11:38:43)
> >>
> >> On 18/11/2020 11:24, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2020-11-18 11:05:24)
>
> On 17/11/2020 11:30, Chris Wilson wrote:
>
On 18/11/2020 12:10, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-11-18 11:38:43)
On 18/11/2020 11:24, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-11-18 11:05:24)
On 17/11/2020 11:30, Chris Wilson wrote:
Since preempt-to-busy, we may unsubmit a request while it is still on
the HW
== Series Details ==
Series: drm/i915/display: Whitespace cleanups
URL : https://patchwork.freedesktop.org/series/84054/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9360 -> Patchwork_18939
Summary
---
**FAILURE**
== Series Details ==
Series: drm/i915/display: Whitespace cleanups
URL : https://patchwork.freedesktop.org/series/84054/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fa13fd9ed600 drm/i915/display: Whitespace cleanups
-:45: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments shoul
== Series Details ==
Series: drm/i915/lspcon: enter standby mode to enhance power saving (rev4)
URL : https://patchwork.freedesktop.org/series/83886/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9360 -> Patchwork_18938
Sum
Quoting Tvrtko Ursulin (2020-11-19 13:18:10)
>
> On 19/11/2020 12:24, Chris Wilson wrote:
> > We plan to expand upon the number of available statuses for when we
> > pretty-print the requests along the timelines, and so need a new set of
> > flags. We have settled upon:
> >
> > Unready [U]
On 19/11/2020 12:24, Chris Wilson wrote:
We plan to expand upon the number of available statuses for when we
pretty-print the requests along the timelines, and so need a new set of
flags. We have settled upon:
Unready [U]
- initial status after being submitted, the request is
We plan to expand upon the number of available statuses for when we
pretty-print the requests along the timelines, and so need a new set of
flags. We have settled upon:
Unready [U]
- initial status after being submitted, the request is not
ready for execution as it is
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Sunday, November 1, 2020 3:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Shankar, Uma ;
> Kulkarni, Vandita ; ville.syrj...@linux.intel.com;
> Sharma, Swati2
> Subject: [PATCH v2 11/13] drm/i915
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Sunday, November 1, 2020 3:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Shankar, Uma ;
> Kulkarni, Vandita ; ville.syrj...@linux.intel.com;
> Sharma, Swati2
> Subject: [PATCH v2 10/13] drm/i915:
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Sunday, November 1, 2020 3:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Shankar, Uma ;
> Kulkarni, Vandita ; ville.syrj...@linux.intel.com;
> Sharma, Swati2
> Subject: [PATCH v2 09/13] drm/i915
We plan to expand upon the number of available statuses for when we
pretty-print the requests along the timelines, and so need a new set of
flags. We have settled upon:
Unready [U]
- initial status after being submitted, the request is not
ready for execution as it is
Hi,
Indeed, we use i915 perf changes introduced by Umesh within Metrics Library (a
common library used to obtain performance counters from various operating
systems and graphics api).
Metrics Library repo: https://github.com/intel/metrics-library
Io controls usage:
https://github.com/intel/m
== Series Details ==
Series: drm/i915: Do not call hsw_set_frame_start_delay for dsi
URL : https://patchwork.freedesktop.org/series/84039/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/com
Quoting Tvrtko Ursulin (2020-11-18 15:51:41)
>
> On 17/11/2020 13:25, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2020-11-17 12:59:44)
> >>
> >> On 17/11/2020 11:30, Chris Wilson wrote:
> >>> + if (show_request) {
> >>> + list_for_each_entry_safe(rq, rn, &tl->re
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Sunday, November 1, 2020 3:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Shankar, Uma ;
> Kulkarni, Vandita ; ville.syrj...@linux.intel.com;
> Sharma, Swati2
> Subject: [PATCH v2 08/13] drm/i915
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Sunday, November 1, 2020 3:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Shankar, Uma ;
> Kulkarni, Vandita ; ville.syrj...@linux.intel.com;
> Sharma, Swati2
> Subject: [PATCH v2 07/13] drm/i915
Hi,
On 11/19/20 8:13 AM, Manasi Navare wrote:
> This should fix the boot oops for dsi
>
> Fixes: 4e3cdb4535e7 ("drm/i915/dp: Master/Slave enable/disable sequence for
> bigjoiner")
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> 1 file changed, 2
On Wed, 18 Nov 2020, Jani Nikula wrote:
> Now that relay_open() accepts const callbacks, make relay callbacks
> const.
>
> Cc: Kalle Valo
> Cc: ath...@lists.infradead.org
> Signed-off-by: Jani Nikula
Kalle, thanks for the acks on the other two ath patches - can I have
your ack on this one too p
drivers/gpu/drm/i915/display/intel_display.c:3634
intel_find_initial_plane_obj() warn: inconsistent indenting
drivers/gpu/drm/i915/display/intel_display.c:15367 kill_bigjoiner_slave() warn:
inconsistent indenting
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_display.c | 23
Hi Dave, Daniel,
Here's this week round of fixes for drm-misc
Maxime
drm-misc-fixes-2020-11-19:
two patches to fix dw-hdmi bind and detection code, and one fix for
sun4i shared with arm-soc
The following changes since commit a6c40b8032b845f132abfcbcbed6bddebbcc3b4a:
drm/mcde: Fix unbalanced r
On Wed, Nov 18, 2020 at 11:13:31PM -0800, Manasi Navare wrote:
> This should fix the boot oops for dsi
>
> Fixes: 4e3cdb4535e7 ("drm/i915/dp: Master/Slave enable/disable sequence for
> bigjoiner")
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> 1
Hi,
> -Original Message-
> From: Intel-gfx On Behalf Of Navare,
> Manasi
> Sent: torstai 19. marraskuuta 2020 7.58
> To: intel-gfx@lists.freedesktop.org
> Cc: Chris Wilson
> Subject: Re: [Intel-gfx] [CI 00/15] Rebased remaining big joiner series
>
> On Wed, Nov 18, 2020 at 11:49:25AM -
Quoting Navare, Manasi (2020-11-19 05:58:03)
> On Wed, Nov 18, 2020 at 11:49:25AM -0800, Navare, Manasi wrote:
> > Series pushed to dinq
> >
> > Manasi
>
> By Chris Wilson:
>
> Oops on boot:
>
> <1>[ 44.315382] BUG: unable to handle page fault for address:
> c90049e02100
> <1>[ 44.3154
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Sunday, November 1, 2020 3:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Shankar, Uma ;
> Kulkarni, Vandita ; ville.syrj...@linux.intel.com;
> Sharma, Swati2
> Subject: [PATCH v2 06/13] drm/dp_h
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