FBC can be re-enabled on TGL with WA of keeping it disabled
while PSR2 is enabled.
This reverts commit 2982ded2ff5ce0cf1a49bc39a526da182782b664.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index c64ed1cd29b1..7a5783564a0f 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1444,13 +1444,6 @@ static int intel_sanitize_fbc_option(struct
drm_i915_private *dev_priv)
if (!HAS_FBC(dev_priv))
return 0;
- /*
- * Fbc is causing random underruns in CI execution on TGL platforms.
- * Disabling the same while the problem is being debugged and analyzed.
- */
- if (IS_TIGERLAKE(dev_priv))
- return 0;
-
if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
return 1;
--
2.26.2
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