Quoting Tvrtko Ursulin (2020-10-22 18:22:10)
>
> + Joonas for maintainer class question.
>
> On 15/10/2020 19:28, john.c.harri...@intel.com wrote:
> > From: John Harrison
> >
> > Update to the latest GuC firmware
> >
> > v2: Rebase to newer tree, updated a commit message (review feedback
> > f
On Thu, Oct 22, 2020 at 04:26:15PM -0700, Aditya Swarup wrote:
On 10/21/20 10:28 AM, Lucas De Marchi wrote:
On Wed, Oct 21, 2020 at 06:31:59AM -0700, Aditya Swarup wrote:
From: Anusha Srivatsa
ADLS follows ICP/TGP like interrupts. Reuse hpd_icp and introduce
ADLS DDI and HPD masks for setting
On 10/16/20 4:40 PM, Aditya Swarup wrote:
> On 9/24/20 11:51 AM, Ville Syrjala wrote:
>> From: Ville Syrjälä
>>
>> Reduce this maintenance nightmare a bit by converting the plane
>> min/max width/height stuff into vfuncs.
>>
>> Now, if I could just think of a nice way to also use this for
>> intel
== Series Details ==
Series: drm/i915/selftests: Skip RPS tests on Ironlake (only IPS)
URL : https://patchwork.freedesktop.org/series/82965/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9186_full -> Patchwork_18768_full
Su
On Fri, Oct 23, 2020 at 02:56:21AM +0300, Ville Syrjälä wrote:
On Thu, Oct 08, 2020 at 01:52:30AM -0700, Lucas De Marchi wrote:
On Thu, Oct 08, 2020 at 11:40:28AM +0300, Ville Syrjälä wrote:
>On Wed, Oct 07, 2020 at 03:51:11PM -0700, Lucas De Marchi wrote:
>> On Tue, Oct 06, 2020 at 05:33:34PM +
On Thu, Oct 22, 2020 at 04:22:01PM -0700, Matt Roper wrote:
On Wed, Oct 21, 2020 at 01:20:31AM -0700, Lucas De Marchi wrote:
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy) \
+ val) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)) >> ((phy % 2) *
2)) + (2 * (phy / 2)))
This
On Thu, Oct 08, 2020 at 01:52:30AM -0700, Lucas De Marchi wrote:
> On Thu, Oct 08, 2020 at 11:40:28AM +0300, Ville Syrjälä wrote:
> >On Wed, Oct 07, 2020 at 03:51:11PM -0700, Lucas De Marchi wrote:
> >> On Tue, Oct 06, 2020 at 05:33:34PM +0300, Ville Syrjälä wrote:
> >> >From: Ville Syrjälä
> >> >
On Wed, Oct 21, 2020 at 01:20:34AM -0700, Lucas De Marchi wrote:
> From: Swathi Dhanavanthri
>
> Set GS Timer to 224.
> Bspec: 53508
>
> Cc: Matt Roper
> Signed-off-by: Swathi Dhanavanthri
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
> 1 fil
On Wed, Oct 21, 2020 at 01:20:33AM -0700, Lucas De Marchi wrote:
> Just like for rkl and tgl, this should be permanent as well for dg1
> instead just for A0. The commit making it permanent for those platforms
> ended up "racing" with the commit adding the DG1 WAs, so now fix that up.
>
> Cc: Swath
On 10/21/20 10:28 AM, Lucas De Marchi wrote:
> On Wed, Oct 21, 2020 at 06:31:59AM -0700, Aditya Swarup wrote:
>> From: Anusha Srivatsa
>>
>> ADLS follows ICP/TGP like interrupts. Reuse hpd_icp and introduce
>> ADLS DDI and HPD masks for setting up hpd interrupts.
>>
>> Cc: Lucas De Marchi
>> Cc:
On Wed, Oct 21, 2020 at 01:20:31AM -0700, Lucas De Marchi wrote:
> DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
> DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a
> single macro that chooses the correct register according to the phy
> being accessed,
On Wed, Oct 07, 2020 at 03:11:56PM -0700, Lucas De Marchi wrote:
On Tue, Oct 06, 2020 at 05:33:30PM +0300, Ville Syrjälä wrote:
From: Ville Syrjälä
Move the DSC stuff out from the middle of the ICP HPD register
definitions. The location seems to have been selected by a
dice roll.
SHPD_FILTER_
== Series Details ==
Series: drm/modes: Switch to 64bit maths to avoid integer overflow
URL : https://patchwork.freedesktop.org/series/82963/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9186_full -> Patchwork_18767_full
S
Quoting Ville Syrjälä (2020-10-22 23:38:16)
> On Thu, Oct 22, 2020 at 10:08:14PM +0100, Chris Wilson wrote:
> > Since Ironlake uses intel_ips.ko for its dynamic frequency adjustment,
> > we do not have direct control over the frequency management so such
> > tests are defunct.
>
> We could just ig
On Thu, Oct 22, 2020 at 03:36:43PM -0700, Matt Roper wrote:
On Wed, Oct 21, 2020 at 01:20:29AM -0700, Lucas De Marchi wrote:
DG1 has one more combo phy port, no TC and all irq handling goes through
SDE, like for MCC.
v2: Also change intel_hpd_pin_default() to include DG1 mapping
v3, v4: Rebase
On Thu, Oct 22, 2020 at 10:08:14PM +0100, Chris Wilson wrote:
> Since Ironlake uses intel_ips.ko for its dynamic frequency adjustment,
> we do not have direct control over the frequency management so such
> tests are defunct.
We could just ignore what ips is saying, but maybe we don't want to.
>
== Series Details ==
Series: VRR/Adaptive Sync enabling in i915
URL : https://patchwork.freedesktop.org/series/82966/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
HDRTEST driv
On Wed, Oct 21, 2020 at 01:20:29AM -0700, Lucas De Marchi wrote:
> DG1 has one more combo phy port, no TC and all irq handling goes through
> SDE, like for MCC.
>
> v2: Also change intel_hpd_pin_default() to include DG1 mapping
> v3, v4: Rebase on hpd refactor
>
> Cc: Ville Syrjälä
> Cc: Anshuma
This patch disables the VRR enable and VRR PUSH
bits in the HW during commit modeset disable sequence.
Thsi disable will happen when the port is disabled
or when the userspace sets VRR prop to false and
requests to disable VRR.
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm
Even though our HW supports PSR + VRR, the available panels
do not work reliably with PSR and VRR together. So if user
requested VRR and is supported by HW enable that and do not
enable PSR in that case.
Cc: Ville Syrjälä
Cc: Gwan-gyeong Mun
Cc: Imre Deak
Signed-off-by: Manasi Navare
---
driv
If VRR is enabled, the sink should ignore MSA parameters
and regenerate incoming video stream without depending
on these parameters. Hence set the MSA_TIMING_PAR_IGNORE_EN
bit if VRR is enabled.
Reset this bit on VRR disable.
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: Manasi Navare
---
d
From: Aditya Swarup
This function sets the VRR property for connector based
on the platform support, EDID monitor range and DP sink
DPCD capability of outputing video without msa
timing information.
v7:
* Move the helper to separate file (Manasi)
v6:
* Remove unset of prop
v5:
* Fix the vrr prop
This patch series adds support for DP 1.4 feature of
Adaptive Sync also called as Variable Refresh rate
which is used to match the display rate with the render rate
by stretching or shrinking the blanking time of the frame.
Aditya Swarup (1):
drm/i915/display/dp: Attach and set drm connector VR
Introduce VRR struct in intel_crtc_state and add
VRR crtc state variables Enable, Vtotalmin and Vtotalmax
to be derived from mode timings and VRR crtc property.
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display_types.h | 7 +++
1 file changed, 7 i
This patch computes the VRR parameters from VRR crtc states
and configures them in VRR registers during CRTC enable in
the modeset enable sequence.
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_ddi.c | 5
drivers/gpu/drm/i915/display/intel_vrr.c | 3
This forces a complete modeset if vrr drm crtc state goes
from enabled to disabled and vice versa.
This patch also computes vrr state variables from the mode timings
and based on the vrr property set by userspace as well as hardware's
vrr capability.
v2:
*Rebase
v3:
* Vmin = max (vtotal, vmin) (Ma
We create a new file for all VRR related helpers.
Also add a function to check vrr capability based on
platform support, DPCD bits and EDID monitor range.
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/display/intel_vrr.c
VRR achieves vblank stretching using the HW PUSH functionality.
So once the VRR is enabled during modeset then for each flip
request from userspace, in the atomic tail pipe_update_end()
we need to set the VRR push bit in HW for it to terminate
the vblank at configured flipline or anytime after flip
VRR_CTL register onloy had a GENMASK but no field prep
define for TRANS_VRR_CTL_LINE_COUNT field so add that
Cc: Aditya Swarup
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i
This functions gets the VRR config from the VRR registers
to match the crtc state variables for VRR.
Cc: Jani Nikula
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 4
drivers/gpu/drm/i915/display/intel_vrr.c | 17 +
drivers/gpu/drm/i915
== Series Details ==
Series: drm/i915/selftests: Skip RPS tests on Ironlake (only IPS)
URL : https://patchwork.freedesktop.org/series/82965/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9186 -> Patchwork_18768
Summary
Since Ironlake uses intel_ips.ko for its dynamic frequency adjustment,
we do not have direct control over the frequency management so such
tests are defunct. Similarly, we can't check the gen6+ RPS registers on
Ironlake.
Hopefully this catches all the invalid tests now that Ironlake has
rejoined t
Hi Dave and Daniel,
Here is probably the last drm-intel-next-fixes before -rc1.
This includes a few patches from dinq and a bunch from drm-intel-gt-next.
drm-intel-next-fixes-2020-10-22:
- Tweak initia DPCD backlight.enabled value (Sean)
- Initialize reserved MOCS indices (Ayaz)
- Mark initial f
== Series Details ==
Series: drm/modes: Switch to 64bit maths to avoid integer overflow
URL : https://patchwork.freedesktop.org/series/82963/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9186 -> Patchwork_18767
Summary
---
== Series Details ==
Series: series starting with [1/3] drm/atomic-helpers: remove
legacy_cursor_update hacks (rev2)
URL : https://patchwork.freedesktop.org/series/82926/
State : failure
== Summary ==
Applying: drm/atomic-helpers: remove legacy_cursor_update hacks
error: patch failed: drivers
From: Ville Syrjälä
The new >8k CEA modes have dotclocks reaching 5.94 GHz, which
means our clock*1000 will now overflow the 32bit unsigned
integer. Switch to 64bit maths to avoid it.
Cc: sta...@vger.kernel.org
Reported-by: Randy Dunlap
Signed-off-by: Ville Syrjälä
---
An interesting question
On Thu, Oct 22, 2020 at 7:22 PM Rob Clark wrote:
>
> On Thu, Oct 22, 2020 at 10:02 AM Rob Clark wrote:
> >
> > On Wed, Oct 21, 2020 at 9:32 AM Daniel Vetter
> > wrote:
> > >
> > > The stuff never really worked, and leads to lots of fun because it
> > > out-of-order frees atomic states. Which up
Quoting Ville Syrjälä (2020-10-22 18:33:43)
> On Thu, Oct 22, 2020 at 12:42:46PM +0100, Chris Wilson wrote:
> > As we disable the interrupt during suspend, also reset the irq_mask to
> > short-circuit subsystems that later try to turn off their interrupt
> > source.
> >
> > <4>[ 101.816730] i915
On Wed, Oct 21, 2020 at 12:14:54PM -0700, Daniele Ceraolo Spurio wrote:
> If we're about to sanitize the GuC, something might have gone wrong
> beforehand, so we should avoid trying to talk to it. Even if GuC is
> still running fine, the sanitize will reset its internal state and clear
> the CTB re
On Thu, Oct 22, 2020 at 12:42:46PM +0100, Chris Wilson wrote:
> As we disable the interrupt during suspend, also reset the irq_mask to
> short-circuit subsystems that later try to turn off their interrupt
> source.
>
> <4>[ 101.816730] i915 :00:02.0:
> drm_WARN_ON(!intel_irqs_enabled(dev_pri
On Thu, Oct 22, 2020 at 10:02 AM Rob Clark wrote:
>
> On Wed, Oct 21, 2020 at 9:32 AM Daniel Vetter wrote:
> >
> > The stuff never really worked, and leads to lots of fun because it
> > out-of-order frees atomic states. Which upsets KASAN, among other
> > things.
> >
> > For async updates we now
On Wed, Oct 21, 2020 at 9:32 AM Daniel Vetter wrote:
>
> The stuff never really worked, and leads to lots of fun because it
> out-of-order frees atomic states. Which upsets KASAN, among other
> things.
>
> For async updates we now have a more solid solution with the
> ->atomic_async_check and ->at
== Series Details ==
Series: drm/i915: Reset the interrupt mask on disabling interrupts (rev2)
URL : https://patchwork.freedesktop.org/series/82945/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9182_full -> Patchwork_18765_full
== Series Details ==
Series: HDCP 2.2 DP MST Support (rev5)
URL : https://patchwork.freedesktop.org/series/81538/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9182_full -> Patchwork_18764_full
Summary
---
**FAILURE*
+ Joonas for maintainer class question.
On 15/10/2020 19:28, john.c.harri...@intel.com wrote:
From: John Harrison
Update to the latest GuC firmware
v2: Rebase to newer tree, updated a commit message (review feedback
from Daniele) and dropped the patch to enable GuC/HuC loading by
default as
For verifying vm_ops.access we only need a page or two to check we both
advance across a page boundary and find the right offset within a page.
16MiB is overkill for the slow uncached reads through the slow ptrace
interface, so reduce the object size by a couple of orders of magnitude.
Signed-off-
On Thu, Oct 22, 2020 at 09:36:23AM -0400, Kazlauskas, Nicholas wrote:
> On 2020-10-21 12:32 p.m., Daniel Vetter wrote:
> > The stuff never really worked, and leads to lots of fun because it
> > out-of-order frees atomic states. Which upsets KASAN, among other
> > things.
> >
> > For async updates
On Thu, Oct. 22, 2020, 3:24 a.m, Lee Shawn C wrote:
>On Wed, Oct. 21, 2020, 5:13 p.m, Souza, Jose wrote:
>>On Wed, 2020-10-21 at 22:24 +0800, Lee Shawn C wrote:
>>> Driver should refer to commit 'b2fc2252ce41 ("drm/i915/psr:
>>> Always wait for idle state when disabling PSR")' to wait for idle
>
On 2020-10-21 12:32 p.m., Daniel Vetter wrote:
The stuff never really worked, and leads to lots of fun because it
out-of-order frees atomic states. Which upsets KASAN, among other
things.
For async updates we now have a more solid solution with the
->atomic_async_check and ->atomic_async_commit
On Wed, Oct 21, 2020 at 06:32:41PM +0200, Daniel Vetter wrote:
> With the removal of helper support it doesn't do anything anymore.
> Also, we already have async plane update code in vc4.
>
> Signed-off-by: Daniel Vetter
> Cc: Eric Anholt
> Cc: Maxime Ripard
Acked-by: Maxime Ripard
Maxime
On Thu, 2020-10-22 at 12:43 +, Mun, Gwan-gyeong wrote:
> 1. While testing the problematic scenario, it has not always shown
> the
> IOMMU DAMR related below errors on the drm-tip.
>(sometimes the error messages raised, but some times it has not
> happened on the same kernel and scenario.
>
1. While testing the problematic scenario, it has not always shown the
IOMMU DAMR related below errors on the drm-tip.
(sometimes the error messages raised, but some times it has not
happened on the same kernel and scenario.
DMAR: DRHD: handling fault status reg 2
DMAR: [DMA Read] Request de
== Series Details ==
Series: drm/i915: Reset the interrupt mask on disabling interrupts (rev2)
URL : https://patchwork.freedesktop.org/series/82945/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9182 -> Patchwork_18765
Summ
== Series Details ==
Series: drm/i915: Reset the interrupt mask on disabling interrupts (rev2)
URL : https://patchwork.freedesktop.org/series/82945/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
57c1554fa7c3 drm/i915: Reset the interrupt mask on disabling interrupts
-:13: WARNI
== Series Details ==
Series: HDCP 2.2 DP MST Support (rev5)
URL : https://patchwork.freedesktop.org/series/81538/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9182 -> Patchwork_18764
Summary
---
**SUCCESS**
No re
As we disable the interrupt during suspend, also reset the irq_mask to
short-circuit subsystems that later try to turn off their interrupt
source.
<4>[ 101.816730] i915 :00:02.0: drm_WARN_ON(!intel_irqs_enabled(dev_priv))
<4>[ 101.816853] WARNING: CPU: 3 PID: 4241 at
drivers/gpu/drm/i915/i9
Quoting Ville Syrjälä (2020-10-22 12:32:52)
> On Thu, Oct 22, 2020 at 08:16:37AM +0100, Chris Wilson wrote:
> > As we disable the interrupt during suspend, also reset the irq_mask to
> > short-circuit subsystems that later try to turn off their interrupt
> > source.
> >
> > <4>[ 101.816730] i915
On Thu, Oct 22, 2020 at 08:16:37AM +0100, Chris Wilson wrote:
> As we disable the interrupt during suspend, also reset the irq_mask to
> short-circuit subsystems that later try to turn off their interrupt
> source.
>
> <4>[ 101.816730] i915 :00:02.0:
> drm_WARN_ON(!intel_irqs_enabled(dev_pri
== Series Details ==
Series: HDCP 2.2 DP MST Support (rev5)
URL : https://patchwork.freedesktop.org/series/81538/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu/../
== Series Details ==
Series: HDCP 2.2 DP MST Support (rev5)
URL : https://patchwork.freedesktop.org/series/81538/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3c203819df03 drm/i915/hdcp: Update CP property in update_pipe
ed3fec051c2e drm/i915/hdcp: Get conn while content_type
On Wed, Oct 21, 2020 at 05:25:40PM -0400, Lyude Paul wrote:
> On Wed, 2020-10-21 at 16:26 +0300, Ville Syrjälä wrote:
> > On Tue, Oct 20, 2020 at 11:25:53PM +, Souza, Jose wrote:
> > > On Tue, 2020-10-20 at 15:41 +0300, Ville Syrjälä wrote:
> > > > On Tue, Oct 20, 2020 at 12:45:55AM -0700
== Series Details ==
Series: drm/i915: Reset the interrupt mask on disabling interrupts
URL : https://patchwork.freedesktop.org/series/82945/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9180_full -> Patchwork_18763_full
S
On Wed, Oct 21, 2020 at 08:13:43PM -0700, Randy Dunlap wrote:
> Hi,
>
> With linux-next 20201021, when booting up, I am seeing this:
>
> [0.560896] UBSAN: signed-integer-overflow in
> ../drivers/gpu/drm/drm_modes.c:765:20
> [0.560903] 2376000 * 1000 cannot be represented in type 'int'
D
== Series Details ==
Series: series starting with drm/i915/gt: Use the local HWSP offset during
submission (rev2)
URL : https://patchwork.freedesktop.org/series/82935/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9180_full -> Patchwork_18762_full
From: Tvrtko Ursulin
Test driver unbind from device with active PMU client.
v2:
* Verify successful open after rebind. (Chris)
Signed-off-by: Tvrtko Ursulin
---
tests/i915/perf_pmu.c | 113 ++
1 file changed, 113 insertions(+)
diff --git a/tests/i915/
On 20/10/2020 17:19, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-10-20 17:11:44)
From: Tvrtko Ursulin
Since we keep a driver global mask of online CPUs and base the decision
whether PMU needs to be migrated upon it, we need to make sure the
migration is done for all registered PMUs (so
Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
and HDCP2_AUTH_STREAM register in i915_reg header.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/dri
Enable HDCP 2.2 over DP MST.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 46 ++-
1 file changed, 44 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_
v3 version of this series has fixed the CI reported failures
and added below patch in this series.
[PATCH v3 02/16] drm/i915/hdcp: Get conn while content_type changed
It has also added the Ack of Tomas to merge the mei_hdcp.c patch
via drm-intel.
This series has been tested with IGT changes to d
Get DRM connector reference count while scheduling a prop work
to avoid any possible destroy of DRM connector when it is in
DRM_CONNECTOR_REGISTERED state.
Fixes: a6597faa2d59 ("drm/i915: Protect workers against disappearing
connectors")
Cc: Sean Paul
Cc: Ramalingam C
Signed-off-by: Anshuman Gu
This requires for HDCP 2.2 MST check link.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/d
hdcp_port_data is specific to a port on which HDCP
encryption is getting enabled, so encapsulate it to
intel_digital_port.
This will be required to enable HDCP 2.2 stream encryption.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +
.../drm
Add support for HDCP 2.2 DP MST shim callback.
This adds existing DP HDCP shim callback for Link Authentication
and Encryption and HDCP 2.2 stream encryption
callback.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_types.h| 4 +
drivers/gpu/drm/i915/d
Gen12 has H/W delta with respect to HDCP{1.x,2.x} display engine
instances lies in Transcoder instead of DDI as in Gen11.
This requires hdcp driver to use mst_master_transcoder for link
authentication and stream transcoder for stream encryption
separately.
This will be used for both HDCP 1.4 and
Let's define Maximum MST content streams up to four
generically which can be supported by modern display
controllers.
Cc: Sean Paul
Cc: Ramalingam C
Acked-by: Maarten Lankhorst
Signed-off-by: Anshuman Gupta
---
include/drm/drm_hdcp.h | 8
1 file changed, 4 insertions(+), 4 deletions(
Handle CP_IRQ in DEVICE_SERVICE_IRQ_VECTOR_ESI0
It requires to call intel_hdcp_handle_cp_irq() in case
of CP_IRQ is triggered by a sink in DP-MST topology.
Cc: "Ville Syrjälä"
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +-
1 file
Pass dig_port as an argument to intel_hdcp_init()
and intel_hdcp2_init().
This will be required for HDCP 2.2 stream encryption.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_hdcp.c| 12 +++---
Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
encryption over DP MST Transport Link.
HDCP 1.4 stream encryption requires to validate the stream encryption
status in HDCP_STATUS_{TRANSCODER,PORT} register driving th
Add support for multiple mst stream in hdcp port data
which will be used by RepeaterAuthStreamManage msg and
HDCP 2.2 security f/w for m' validation.
v2:
Init the hdcp port data k for HDMI/DP SST strem.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_types
When crtc state need_modeset is true it is not necessary
it is going to be a real modeset, it can turns to be a
update_pipe instead of modeset.
This turns content protection property to be DESIRED and hdcp
update_pipe left with property to be in DESIRED state but
actually hdcp->value was ENABLED.
T
DP MST stream encryption status requires time of a link frame
in order to change its status, but as there were some HDCP
encryption timeout observed earlier, it is safer to use
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS timeout for stream status too,
it requires to move the macro to a header.
It will be used
Enable HDCP 1.4 over DP MST for Gen12.
This also enable the stream encryption support for
older generations, which was missing earlier.
v2:
- Added debug print for stream encryption.
- Disable the hdcp on port after disabling last stream
encryption.
Cc: Ramalingam C
Signed-off-by: Anshuman Gup
Fix the size of WIRED_REPEATER_AUTH_STREAM_REQ cmd buffer size.
It is based upon the actual number of MST streams and size
of wired_cmd_repeater_auth_stream_req_in.
Excluding the size of hdcp_cmd_header.
v2:
hdcp_cmd_header size annotation nitpick. [Tomas]
Cc: Tomas Winkler
Cc: Ramalingam C
Ack
Op 21-10-2020 om 16:44 schreef Chris Wilson:
> Quoting Maarten Lankhorst (2020-10-21 15:39:48)
>> Instead of sharing pages with breadcrumbs, give each timeline a
>> single page. This allows unrelated timelines not to share locks
>> any more during command submission.
> This is designed to fail. No.
== Series Details ==
Series: Big joiner enabling
URL : https://patchwork.freedesktop.org/series/82944/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9180_full -> Patchwork_18761_full
Summary
---
**SUCCESS**
No reg
== Series Details ==
Series: drm/i915: Reset the interrupt mask on disabling interrupts
URL : https://patchwork.freedesktop.org/series/82945/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9180 -> Patchwork_18763
Summary
---
== Series Details ==
Series: drm/i915: Reset the interrupt mask on disabling interrupts
URL : https://patchwork.freedesktop.org/series/82945/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
34e2194f7c0a drm/i915: Reset the interrupt mask on disabling interrupts
-:13: WARNING:COMM
== Series Details ==
Series: series starting with drm/i915/gt: Use the local HWSP offset during
submission (rev2)
URL : https://patchwork.freedesktop.org/series/82935/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9180 -> Patchwork_18762
==
As we disable the interrupt during suspend, also reset the irq_mask to
short-circuit subsystems that later try to turn off their interrupt
source.
<4>[ 101.816730] i915 :00:02.0: drm_WARN_ON(!intel_irqs_enabled(dev_priv))
<4>[ 101.816853] WARNING: CPU: 3 PID: 4241 at
drivers/gpu/drm/i915/i9
== Series Details ==
Series: series starting with drm/i915/gt: Use the local HWSP offset during
submission (rev2)
URL : https://patchwork.freedesktop.org/series/82935/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be
== Series Details ==
Series: series starting with drm/i915/gt: Use the local HWSP offset during
submission (rev2)
URL : https://patchwork.freedesktop.org/series/82935/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a0a057614518 drm/i915/gt: Use the local HWSP offset during subm
91 matches
Mail list logo
