In igt_flush_test() we try to switch back to the kernel context, but we
are only able to do so when we care called with struct_mutex held.
More CI fallout from lockdep being temporarily suppressed :(
Fixes: 4cdf65ce8cc2 ("drm/i915/selftests: Return to kernel context after each
test")
Signed-off-
On Tue, May 08, 2018 at 10:30:19PM +0300, Jani Nikula wrote:
> On Wed, 09 May 2018, Feng Tang wrote:
> > >> > > > On Mon, May 07, 2018 at 11:40:45AM +0100, Chris Wilson wrote:
> >> >> > > > > Quoting Feng Tang (2018-05-07 11:36:09)
> >> >> > > > > > To fulfil the Dell 4K monitor, the dpcd max ret
Hi Christoph,
On Wed, 9 May 2018 07:08:55 +0200 Christoph Hellwig wrote:
>
> FYI, because the dma_configure change touch so much code and the author
> wants to base more work on it it actually is in a guranteed stable
> branch with just those patches:
>
> git://git.infradead.org/users/hch/dm
On Wed, May 09, 2018 at 03:02:55PM +1000, Stephen Rothwell wrote:
> > - ret = of_dma_configure(dev, NULL);
> > + ret = of_dma_configure(dev, NULL, true);
> > if (ret < 0) {
> > DRM_ERROR("Cannot setup DMA ops, ret %d", ret);
> > return ret;
> > --
> > 2.17.0
>
> Th
Hi all,
On Tue, 8 May 2018 11:07:16 +1000 Stephen Rothwell
wrote:
>
> After merging the drm-intel tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> drivers/gpu/drm/xen/xen_drm_front.c: In function 'xen_drv_probe':
> drivers/gpu/drm/xen/xen_drm_front.c:740:10: error: '
== Series Details ==
Series: drm/i915/psr: Check if VBT says PSR can be enabled.
URL : https://patchwork.freedesktop.org/series/42909/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4160_full -> Patchwork_8954_full =
== Summary - WARNING ==
Minor unknown changes coming wi
== Series Details ==
Series: drm/i915/psr: Nuke PSR support for VLV and CHV
URL : https://patchwork.freedesktop.org/series/42915/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4160 -> Patchwork_8955 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_
== Series Details ==
Series: drm/i915/gvt: fix spelling mistake: "resseting" -> "resetting"
URL : https://patchwork.freedesktop.org/series/42903/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4160_full -> Patchwork_8953_full =
== Summary - WARNING ==
Minor unknown change
1) PSR hardware and hence the driver code deviates a lot from the DDI
implementations. Retaining support for VLV and CHV is maintenance burden,
we've had to refactor to keep the code clean.
2) There is no PSR capable VLV/CHV platform in CI to ensure code is
correct.
3) There are likely no users for
== Series Details ==
Series: Workarounds for Icelake (rev3)
URL : https://patchwork.freedesktop.org/series/42055/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4160_full -> Patchwork_8952_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_8952_ful
== Series Details ==
Series: drm/i915/selftests: Create mock_engine() under struct_mutex
URL : https://patchwork.freedesktop.org/series/42898/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4160_full -> Patchwork_8951_full =
== Summary - WARNING ==
Minor unknown changes c
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/execlists: Make submission
tasklet hardirq safe
URL : https://patchwork.freedesktop.org/series/42896/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4160_full -> Patchwork_8950_full =
== Summary - WARNING =
== Series Details ==
Series: drm/i915/psr: Check if VBT says PSR can be enabled.
URL : https://patchwork.freedesktop.org/series/42909/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4160 -> Patchwork_8954 =
== Summary - SUCCESS ==
No regressions found.
External URL:
h
== Series Details ==
Series: drm/i915/psr: Check if VBT says PSR can be enabled.
URL : https://patchwork.freedesktop.org/series/42909/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/psr: Check if VBT says PSR can be enabled.
-drivers/gpu/drm/i915/selftests/../i915_d
Driver features data block has a boolean flag for PSR, use this to decide
whether PSR should be enabled on a platform. The module parameter can
still be used to override this.
Note: The feature currently remains disabled by default for all platforms
irrespective of what VBT says.
Cc: Rodrigo Vivi
On Wed, 2018-05-02 at 12:03 -0700, Oscar Mateo wrote:
> This patch adds the support to load HuC on ICL.
> Version 8.02.2678
>
> v2 (James): Rebase
>
> Signed-off-by: Oscar Mateo
> Cc: Tony Ye
> Cc: Vinay Belgaumkar
> Cc: Michel Thierry
> Cc: Joonas Lahtinen
> Cc: Michal Wajdeczko
> Cc: John
On Wed, 2018-05-02 at 12:03 -0700, Oscar Mateo wrote:
> The register to check for correct HuC authentication by the GuC
> has changed in Icelake. Look into the right register & bit.
>
> v2: rebased.
> v3: rebased.
> v4: Fix I915_PARAM_HUC_STATUS as well (Tony)
> v5: Fix duplicate Cc
>
> BSpec: 19
On Wed, 2018-05-02 at 12:03 -0700, Oscar Mateo wrote:
> A GuC firmware for Icelake is now available. Let's use it.
>
> v2: Split out the Cannonlake stuff in a separate patch (Michal)
>
> v3: Rebased
>
> v4:
> - Rebased
> - Split out MODULE_FIRMWARE so we don't accidentally push it
> befo
On Wed, 2018-05-02 at 12:03 -0700, Oscar Mateo wrote:
> Sanitize the enable_guc option so that we can enable HuC
> authentication,
> but nothing else. The firmware interface has changed quite
> dramatically
> in Gen11, so it will take a while before we can submit workloads to
> the
> GuC with guara
On Wed, 2018-05-02 at 12:03 -0700, Oscar Mateo wrote:
> Only enough to achieve HuC authentication. No GuC submission
> or any other feature for the time being.
>
> v2: Fix extra space
>
> Signed-off-by: Oscar Mateo
> Cc: Joonas Lahtinen
> Cc: Michal Wajdeczko
> Cc: John Spotswood
Reviewed-by
== Series Details ==
Series: drm/i915/gvt: fix spelling mistake: "resseting" -> "resetting"
URL : https://patchwork.freedesktop.org/series/42903/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4160 -> Patchwork_8953 =
== Summary - SUCCESS ==
No regressions found.
Exter
== Series Details ==
Series: Workarounds for Icelake (rev3)
URL : https://patchwork.freedesktop.org/series/42055/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4160 -> Patchwork_8952 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.free
Hi Ville,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.17-rc4 next-20180508]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https
== Series Details ==
Series: Workarounds for Icelake (rev3)
URL : https://patchwork.freedesktop.org/series/42055/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/icl: Introduce initial Icelake Workarounds
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3653:16: warning
== Series Details ==
Series: drm/i915: per context slice/subslice powergating (rev2)
URL : https://patchwork.freedesktop.org/series/42285/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4158_full -> Patchwork_8949_full =
== Summary - FAILURE ==
Serious unknown changes com
== Series Details ==
Series: Workarounds for Icelake (rev3)
URL : https://patchwork.freedesktop.org/series/42055/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e15ebaa57f79 drm/i915/icl: Introduce initial Icelake Workarounds
-:54: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p'
== Series Details ==
Series: drm/i915/selftests: Create mock_engine() under struct_mutex
URL : https://patchwork.freedesktop.org/series/42898/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4160 -> Patchwork_8951 =
== Summary - WARNING ==
Minor unknown changes coming with
From: Colin Ian King
Trivial fix to spelling mistake in gvt_dbg_core debug message
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 2e0a0
== Series Details ==
Series: series starting with [1/2] drm/i915/execlists: Use rmb() to order CSB
reads
URL : https://patchwork.freedesktop.org/series/42884/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4158_full -> Patchwork_8948_full =
== Summary - WARNING ==
Minor
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/execlists: Make submission
tasklet hardirq safe
URL : https://patchwork.freedesktop.org/series/42896/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4160 -> Patchwork_8950 =
== Summary - WARNING ==
Minor
On Mon, 2018-04-30 at 23:28 +, Souza, Jose wrote:
> On Thu, 2018-04-26 at 15:37 -0700, Dhinakaran Pandiyan wrote:
> >
> >
> >
> > On Wed, 2018-04-18 at 15:43 -0700, José Roberto de Souza wrote:
> > >
> > > Sink will interrupt source when it have any problem saving or
> > > reading
> > > the
On Wed, 2018-04-18 at 15:43 -0700, José Roberto de Souza wrote:
> - Doing earlier return when not busy
> - using u32 instead of uint32_t
> - counting from 3 to 0 as it is is the most common in the driver
Hmm. I see more instances that increment the loop variable than the
opposite.
> - using DRM_WA
On 05/04/2018 03:26 PM, John Spotswood wrote:
On Wed, 2018-05-02 at 12:03 -0700, Oscar Mateo wrote:
The register to check for correct HuC authentication by the GuC
has changed in Icelake. Look into the right register & bit.
v2: rebased.
v3: rebased.
v4: Fix I915_PARAM_HUC_STATUS as well (Tony
Revert to the legacy implementation.
v2: GEN7_ROW_CHICKEN2 is masked
v3:
- Rebased
- Renamed to Wa_2006611047
- A0 and B0 only
v4:
- Add spaces around '<<' (and fix the surrounding code as well)
- Mark the WA as pre-prod
v5: Rebased on top of the WA refactoring
v6: Added References (Mika
This workarounds an issue with insufficient storage for the
CL2 and SF units.
v2: Renamed to Wa_1405766107
v3: Wrapped the commit message
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)
v6:
- Rebased
- s/MACALLOC/MAXALLOC (Mika)
- C, not lisp (Chris)
References: HSDES#1
Allows UMDs to set 'Disable Gather at Set Shader Common Slice'.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it...
v2: Rebased
v3: Rebased on top of the WA refactoring
v4: Rebased on top of t
Required for TR-TT (Tiled Resource Translation Table) support.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the
Revert to an L3 non-hash model, for performance reasons.
v2:
- Place the WA name above the actual change
- Improve the register naming
v3:
- Rebased
- Renamed to Wa_1604223664
v4: Rebased on top of the WA refactoring
v5:
- Added References (Mika)
- Fixed wrong mask and value (Mika)
-
Disable GWL clock gating to prevent an issue that might
cause hangs.
v2: Rebased on top of the WA refactoring
v3: Wa_2201832410 officially merged with Wa_1406680159
v4: Added References (Mika)
v5:
- Rebased
- C, not lisp (Chris)
- Add reference where WA is better explained (Rodrigo)
- Add
Disable MSC clock gating to prevent data corruption.
BSpec: 19257
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
- Rebased
- C, not lisp (Chris)
- A0 only (Mika)
References: HSDES#1405779004
Signed-off-by: Oscar Mateo
Reviewed-by: Mika Kuoppala
---
drivers/gpu/
On Mon, 2018-04-30 at 23:39 +, Souza, Jose wrote:
> On Thu, 2018-04-26 at 15:51 -0700, Dhinakaran Pandiyan wrote:
> >
> >
> >
> > On Wed, 2018-04-18 at 15:43 -0700, José Roberto de Souza wrote:
> > >
> > > This reduces the spaghetti that intel_dp_aux_xfer().
> > >
> > > Moved doing less ch
Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynamically changing its clock frequency in low-throughput
conditions. This patches enables it by default on Gen11.
v2: Wrong operation to clear the bit (Praveen)
v3: Rebased on top of the WA refactoring
v4: Move to icl_in
Revert to the legacy implementation to avoid a system hang.
v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG
v3: Renamed to Wa_220166154
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)
v6:
- Rebased
- C, not lisp (Chris)
References: HSDES#220166154
Signed-off-by: Oscar
Disable blend embellishment in RCC.
Also, some other registers style fixed in passing.
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
- Fixed in B0
- Mentioned style fixes in commit message
References: HSDES#2006665173
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
Disable CGPSF unit clock gating to prevent an issue.
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
- Rebased
- C, not lisp (Chris)
- Remove unintentional whitespaces (Mika)
- Fixed in C0 (Mika)
References: HSDES#1406838659
Signed-off-by: Oscar Mateo
Reviewed-by
Required to dinamically set 'Trilinear Filter Quality Mode'
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA
Enables blend optimization for floating point RTs
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#1406393558
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 3 ++
Avoids an undefined LLC behavior.
BSpec: 9613
v2: Renamed to Wa_1405733216
v3: Spaces around '<<' and fix surrounding code
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)
v6:
- Rebased
- C, not lisp (Chris)
References: HSDES#1405733216
Signed-off-by: Oscar Mateo
Reviewe
Adjust default GAM TLB partitioning for performance reasons.
v2: Only touch the bits that we really need
v3: Rebased on top of the WA refactoring
v4:
- Added References (Mika)
- Rebased
v5:
- Rebased
- C, not lisp (Chris)
- Correct reference number (Mika)
References: HSDES#220160670
Sig
Disable I2M Write for performance reasons.
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
- Rebased
- C, not lisp (Chris)
- GEN7 chicken bit in the wrong side of the fence (Mika)
- Use two spaces to align bit macros
References: HSDES#1604302699
Signed-off-by: Osc
Avoids a hang during soft reset.
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
- Rebased
- C, not lisp (Chris)
- Which steppings affected by this are not clear.
For the moment, apply unconditionally as per the
BSpec (Mika)
- Add reference to another HSD a
List of GT workarounds for Icelake that we have been carrying in internal.
Applied lots of review comments from Mika and stamped rv-b's from him and
Rodrigo.
Oscar Mateo (22):
drm/i915/icl: Introduce initial Icelake Workarounds
drm/i915/icl: Enable Sampler DFR
drm/i915/icl: WaGAPZPrioritySch
Redirects the state cache to the CS Command buffer section for
performance reasons.
v2: Rebased
v3: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#1604325460
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
dri
Required to dinamically set 'Small PL Lossless Fix Enable'
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA r
Required for Bindless samplers.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: Rebased on top of the WA refactoring (Michel)
v3: Added References (Mika)
References: HSDES#1404695891
Cc
Inherit workarounds from previous platforms that are still valid for
Icelake.
v2: GEN7_ROW_CHICKEN2 is masked
v3:
- Since it has been fixed already in upstream, removed the TODO
comment about WA_SET_BIT for WaInPlaceDecompressionHang.
- Squashed with this patch:
drm/i915/icl: add ice
The default GAPZ arbitrer priority value at power-on has been found
to be incorrect.
v2: Now renamed to Wa_1405543622
v3: Rebased on top of the WA refactoring
v4: Added HSDES reference number (Mika)
v5:
- Rebased
- C, not lisp (Chris)
References: HSDES#1405543622
Signed-off-by: Oscar Mateo
R
On 05/08/2018 02:10 PM, Chris Wilson wrote:
Calling mock_engine() calls i915_timeline_init() and that requires
struct_mutex to be held as it adds itself to the global list of
timelines. This error was introduced by commit a89d1f921c15 ("drm/i915:
Split i915_gem_timeline into individual timelines"
Hi Ville,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.17-rc4 next-20180508]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com
Quoting Patchwork (2018-05-08 21:58:09)
> == Series Details ==
>
> Series: drm/i915: Annotate timeline lock nesting
> URL : https://patchwork.freedesktop.org/series/42881/
> State : failure
>
> == Summary ==
>
> = CI Bug Log - changes from CI_DRM_4158_full -> Patchwork_8946_full =
>
> == Summ
Calling mock_engine() calls i915_timeline_init() and that requires
struct_mutex to be held as it adds itself to the global list of
timelines. This error was introduced by commit a89d1f921c15 ("drm/i915:
Split i915_gem_timeline into individual timelines") but the issue was
masked in CI by the earlie
Prepare to allow the GuC submission to be run from underneath a
hardirq timer context (and not just the current softirq context) as is
required for fast preemption resets and context switches.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_guc_submission.
Prepare to allow the execlists submission to be run from underneath a
hardirq timer context (and not just the current softirq context) as is
required for fast preemption resets and context switches.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 4
Quoting Tvrtko Ursulin (2018-05-08 18:45:44)
>
> On 07/05/2018 14:57, Chris Wilson wrote:
> > Prepare to allow the execlists submission to be run from underneath a
> > hardirq timer context (and not just the current softirq context) as is
> > required for fast preemption resets and context switche
== Series Details ==
Series: drm/i915: Annotate timeline lock nesting
URL : https://patchwork.freedesktop.org/series/42881/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4158_full -> Patchwork_8946_full =
== Summary - FAILURE ==
Serious unknown changes coming with Patchw
Quoting Tvrtko Ursulin (2018-05-03 18:18:43)
>
> On 25/04/2018 12:45, Lionel Landwerlin wrote:
> > From: Chris Wilson
> >
> > We want to allow userspace to reconfigure the subslice configuration for
> > its own use case. To do so, we expose a context parameter to allow
> > adjustment of the RPCS
Quoting Ville Syrjälä (2018-05-08 16:35:18)
> On Tue, May 08, 2018 at 04:15:52PM +0100, Chris Wilson wrote:
> > The i915_flip* tracepoints are no longer in use since the removal of CS
> > flip in commit 8b5d27b911d7 ("drm/i915: Remove intel_flip_work
> > infrastructure")
> >
> > References: 8b5d27
Quoting Michel Thierry (2018-05-08 18:30:22)
> On 05/08/2018 08:35 AM, Chris Wilson wrote:
> > CI noticed
> >
> > <4>[ 23.430701]
> > <4>[ 23.430706] WARNING: possible recursive locking detected
> > <4>[ 23.430713] 4.17.0-rc4-CI-CI_DRM_4156+ #1 No
== Series Details ==
Series: drm/i915: Remove unused i915_flip tracepoints
URL : https://patchwork.freedesktop.org/series/42879/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4158_full -> Patchwork_8945_full =
== Summary - FAILURE ==
Serious unknown changes coming with P
Quoting Tvrtko Ursulin (2018-05-08 18:47:42)
>
> On 08/05/2018 16:35, Chris Wilson wrote:
> > CI noticed
> >
> > <4>[ 23.430701]
> > <4>[ 23.430706] WARNING: possible recursive locking detected
> > <4>[ 23.430713] 4.17.0-rc4-CI-CI_DRM_4156+ #1 No
== Series Details ==
Series: series starting with [v2,1/3] drm/i915: Replace vbt edp.support with
int_lvds_support (rev3)
URL : https://patchwork.freedesktop.org/series/42874/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4158_full -> Patchwork_8944_full =
== Summary - WAR
On Wed, 09 May 2018, Feng Tang wrote:
> >> > > > On Mon, May 07, 2018 at 11:40:45AM +0100, Chris Wilson wrote:
>> >> > > > > Quoting Feng Tang (2018-05-07 11:36:09)
>> >> > > > > > To fulfil the Dell 4K monitor, the dpcd max retries has been
>> >> > > > > > bumped
>> >> > > > > > from 7 to 32, w
On Fri, May 04, 2018 at 03:18:00PM -0700, matthew.s.atw...@intel.com wrote:
> From: Matt Atwood
>
> DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8
> bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended
> receiver capabilities. For panels that use this new fe
== Series Details ==
Series: drm/i915: per context slice/subslice powergating (rev2)
URL : https://patchwork.freedesktop.org/series/42285/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4158 -> Patchwork_8949 =
== Summary - SUCCESS ==
No regressions found.
External URL
== Series Details ==
Series: drm/i915/execlists: Use rmb() to order CSB reads (rev2)
URL : https://patchwork.freedesktop.org/series/42867/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4158_full -> Patchwork_8943_full =
== Summary - WARNING ==
Minor unknown changes comin
== Series Details ==
Series: drm/i915: per context slice/subslice powergating (rev2)
URL : https://patchwork.freedesktop.org/series/42285/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Program RPCS for Broadwell
Okay!
Commit: drm/i915: Record the sseu configurati
== Series Details ==
Series: drm/i915: per context slice/subslice powergating (rev2)
URL : https://patchwork.freedesktop.org/series/42285/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
adb11ec2e377 drm/i915: Program RPCS for Broadwell
48dc54799480 drm/i915: Record the sseu conf
== Series Details ==
Series: series starting with [1/2] drm/i915/execlists: Use rmb() to order CSB
reads
URL : https://patchwork.freedesktop.org/series/42884/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4158 -> Patchwork_8948 =
== Summary - SUCCESS ==
No regressions f
== Series Details ==
Series: series starting with [1/2] drm/i915/execlists: Use rmb() to order CSB
reads
URL : https://patchwork.freedesktop.org/series/42884/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1bab7a77636f drm/i915/execlists: Use rmb() to order CSB reads
-:32: WARN
== Series Details ==
Series: RFT agp/intel: Hit Grantsdale with a sledgehammer
URL : https://patchwork.freedesktop.org/series/42882/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4158 -> Patchwork_8947 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwo
If some of the contexts submitting workloads to the GPU have been
configured to shutdown slices/subslices, we might loose the NOA
configurations written in the NOA muxes. We need to reprogram them
when we detect a powergating configuration change.
In this change i915/perf is responsible for settin
From: Chris Wilson
Currently we only configure the power gating for Skylake and above, but
the configuration should equally apply to Broadwell and Braswell. Even
though, there is not as much variation as for later generations, we want
to expose control over the configuration to userspace and may
Hi all,
Another update, trying to minimize the number of reprogramming issued
due to powergating configuration changes. This is achieved by tracking
the last submitted powergating configuration in the engine submission
mechanism and reprogramming only on configuration changes.
Another improvement
From: Chris Wilson
We want to allow userspace to reconfigure the subslice configuration for
its own use case. To do so, we expose a context parameter to allow
adjustment of the RPCS register stored within the context image (and
currently not accessible via LRI). If the context is adjusted before
This can be used to monitor the number of powergating transition
changes for a particular workload.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/intel_engine_cs.c | 2 ++
drivers/gpu/drm/i915/intel_lrc.c| 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
drivers/gpu/drm/i
From: Chris Wilson
We want to expose the ability to reconfigure the slices, subslice and
eu per context and per engine. To facilitate that, store the current
configuration on the context for each engine, which is initially set
to the device default upon creation.
v2: record sseu configuration pe
We don't need any special treatment on error so just return as soon as
possible.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf
== Series Details ==
Series: RFT agp/intel: Hit Grantsdale with a sledgehammer
URL : https://patchwork.freedesktop.org/series/42882/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e6af4f2b7d53 RFT agp/intel: Hit Grantsdale with a sledgehammer
-:20: ERROR:MISSING_SIGN_OFF: Missin
On 08/05/2018 16:35, Chris Wilson wrote:
CI noticed
<4>[ 23.430701]
<4>[ 23.430706] WARNING: possible recursive locking detected
<4>[ 23.430713] 4.17.0-rc4-CI-CI_DRM_4156+ #1 Not tainted
<4>[ 23.430720] ---
On 07/05/2018 14:57, Chris Wilson wrote:
Prepare to allow the execlists submission to be run from underneath a
hardirq timer context (and not just the current softirq context) as is
required for fast preemption resets and context switches.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915
On 07/05/2018 14:57, Chris Wilson wrote:
Prepare to allow the GuC submission to be run from underneath a
hardirq timer context (and not just the current softirq context) as is
required for fast preemption resets and context switches.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel
On 07/05/2018 14:57, Chris Wilson wrote:
Prepare to allow the execlists submission to be run from underneath a
hardirq timer context (and not just the current softirq context) as is
required for fast preemption resets and context switches.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915
== Series Details ==
Series: drm/i915/gtt: Trust the uncached store to flush wcb (rev2)
URL : https://patchwork.freedesktop.org/series/42873/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4157_full -> Patchwork_8942_full =
== Summary - SUCCESS ==
No regressions found.
From: Tvrtko Ursulin
Request split mode had several bugs, both in the original version and also
after the recent refactorings.
One big one was that it wasn't considering different submit ports as a
reason to split execution, and also that it was too time based instead of
looking at relevant time
From: Tvrtko Ursulin
In split mode all requests have to be added up since they were previously
re-arranged so there is no overlap.
Signed-off-by: Tvrtko Ursulin
Cc: John Harrison
---
scripts/trace.pl | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/scripts/trace.pl b/scri
From: Tvrtko Ursulin
Add the command line switch which uses different colours for different
context execution boxes.
v2:
* Use HSL to simplify color generation. (Lionel)
* Colour other boxes in the same colour but different shade so it is
easier to follow the timeline.
Signed-off-by: Tvrtk
From: Tvrtko Ursulin
Timeline id allocation order is not tied with engine ids any more.
Remove the option which assumed that was the case in attempt to provide
more readable timeline.
Signed-off-by: Tvrtko Ursulin
---
scripts/media-bench.pl | 2 +-
scripts/trace.pl | 18 ---
From: Tvrtko Ursulin
We add stripes for different stages of request execution so it is easier
to follow one context in the multi-colour mode.
Vertical stripe pattern indicates pipeline "blockages" - requests waiting
for dependencies before they are runnable.
Diagonal stripes indicate runnable r
From: Tvrtko Ursulin
Incomplete requests (no notify, no context complete) have to be corrected
by looking at the engine timeline, and not the sorted-by-start-time view
as was previously used.
Per-engine timelines are generated on demand and cached for later use.
v2: Find end of current context
From: Tvrtko Ursulin
Just forget about earlier request_in events.
Signed-off-by: Tvrtko Ursulin
---
scripts/trace.pl | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/scripts/trace.pl b/scripts/trace.pl
index 0ec33cd37e4a..935f57117a37 100755
--- a/scripts/trace.pl
+++ b/s
1 - 100 of 248 matches
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