Disable MSC clock gating to prevent data corruption.

BSpec: 19257

v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
  - Rebased
  - C, not lisp (Chris)
  - A0 only (Mika)

References: HSDES#1405779004
Signed-off-by: Oscar Mateo <oscar.ma...@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuopp...@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 1 +
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dd23af3..950ec8e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3840,6 +3840,7 @@ enum {
 #define SLICE_UNIT_LEVEL_CLKGATE       _MMIO(0x94d4)
 #define  SARBUNIT_CLKGATE_DIS          (1 << 5)
 #define  RCCUNIT_CLKGATE_DIS           (1 << 7)
+#define  MSCUNIT_CLKGATE_DIS           (1 << 10)
 
 #define SUBSLICE_UNIT_LEVEL_CLKGATE    _MMIO(0x9524)
 #define  GWUNIT_CLKGATE_DIS            (1 << 16)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 3547403..469a83d 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -739,6 +739,12 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
         */
        I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, I915_READ(GAMW_ECO_DEV_RW_IA_REG) |
                                           GAMW_ECO_DEV_CTX_RELOAD_DISABLE);
+
+       /* Wa_1405779004:icl (pre-prod) */
+       if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_A0))
+               I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
+                          I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
+                          MSCUNIT_CLKGATE_DIS);
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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