i915 expects GuC log level to be specified as:
0: disabled
1: enabled (verbosity level 0 = min)
2: enabled (verbosity level 1)
3: enabled (verbosity level 2)
4: enabled (verbosity level 3 = max)
Remove the earlier internal layout based logging control from
g
On Fri, Jan 12, 2018 at 11:32:30AM +0530, Sagar Arun Kamble wrote:
> Is skl-gvtdvm not having vGPU active?
>
> It has flag X86_FEATURE_HYPERVISOR set however it might be set on host too
> so relying intel_vgpu_active().
>
Do you mean flag X86_FEATURE_HYPERVISOR is set on host, too? This is weird
Is skl-gvtdvm not having vGPU active?
It has flag X86_FEATURE_HYPERVISOR set however it might be set on host
too so relying intel_vgpu_active().
On 1/11/2018 10:27 PM, Patchwork wrote:
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: Don't enable GuC when vGPU is
activ
On 1/11/2018 8:54 PM, Michal Wajdeczko wrote:
Today we have format mismatch between read/write operations
of i915_guc_log_control entry. For read we return (0, 1..4)
that represents disable/verbosity levels, but for write we
force user to follow internal structure format (0,1,9,11,13).
0x0, 0x
On 1/11/2018 8:54 PM, Michal Wajdeczko wrote:
We used value -1 to indicate "disabled" and values 0..3 to
indicate "enabled", but most of our other modparams are using
-1 for "auto" mode and 0 for "disable". For consistency let's
change our log level values to:
-1: auto (depends on platform and
On Wed, Jan 10, 2018 at 9:48 AM, Ville Syrjälä <
ville.syrj...@linux.intel.com> wrote:
> On Wed, Jan 10, 2018 at 09:03:14AM -0800, Jason Ekstrand wrote:
> > On Fri, Dec 22, 2017 at 11:22 AM, Ville Syrjala <
> > ville.syrj...@linux.intel.com> wrote:
> >
> > > From: Ville Syrjälä
> > >
> > > Let's
On 11/01/18 14:55, Oscar Mateo wrote:
From: Tvrtko Ursulin
Gen11 removes the Resource Streamer, which frees up a big chunk of
the context image. BSpec indicates 12538 DWORDs (13 pages), plus
one page for PPHWSP.
This is actually 12544 dwords according to the specs (I've already
confirmed
On Thu, Jan 11, 2018 at 09:48:57PM +, James Ausmus wrote:
> On Thu, Jan 11, 2018 at 04:00:08PM -0200, Paulo Zanoni wrote:
> > From: Anusha Srivatsa
> >
> > ICP has two backlight controllers - similar to previous platforms like
> > BXT.
> >
> > v2: Remove the usage of ICP_SECOND_PPS_BACKLIGHT r
On 11/01/18 14:37, Oscar Mateo wrote:
On 01/11/2018 01:10 PM, Daniele Ceraolo Spurio wrote:
This could potentially be squashed with patch 15, as it doesn't make
much sense to add a TODO there and solve it here. We might also want
to update the comment above intel_lr_context_descriptor_updat
On 11/01/18 14:55, Oscar Mateo wrote:
Instead of returning whatever size the latest GEN used. This is because
context sizes for new GENs can go up or down, but the only safe thing to
do for missing cases is to use the largest known one, whatever that is.
Suggested-by: Rodrigo Vivi
Signed-off-
Instead of returning whatever size the latest GEN used. This is because
context sizes for new GENs can go up or down, but the only safe thing to
do for missing cases is to use the largest known one, whatever that is.
Suggested-by: Rodrigo Vivi
Signed-off-by: Oscar Mateo
Cc: Daniele Ceraolo Spuri
From: Tvrtko Ursulin
Gen11 removes the Resource Streamer, which frees up a big chunk of
the context image. BSpec indicates 12538 DWORDs (13 pages), plus
one page for PPHWSP.
Please notice that, when looking at the BSpec context image table,
the right filter has to be applied as some rows are exc
On 01/11/2018 11:40 AM, Rodrigo Vivi wrote:
On Thu, Jan 11, 2018 at 06:23:20PM +, Oscar Mateo wrote:
From: Tvrtko Ursulin
Gen11 removes the Resource Streamer, which frees up a big chunk of
the context image. BSpec indicates 12538 DWORDs (13 pages), plus
one page for PPHWSP.
Please notic
On 01/11/2018 01:10 PM, Daniele Ceraolo Spurio wrote:
This could potentially be squashed with patch 15, as it doesn't make
much sense to add a TODO there and solve it here. We might also want
to update the comment above intel_lr_context_descriptor_update to
remove the implication that SW cont
Hi,
On 11-01-18 22:42, Hans de Goede wrote:
Hi,
On 11-01-18 22:17, Ville Syrjälä wrote:
On Thu, Jan 11, 2018 at 08:53:42PM +, Chris Wilson wrote:
Quoting Ville Syrjälä (2018-01-11 20:10:45)
On Wed, Jan 10, 2018 at 12:55:05PM +, Chris Wilson wrote:
While we talk to the punit over its
On Thu, Jan 11, 2018 at 04:00:08PM -0200, Paulo Zanoni wrote:
> From: Anusha Srivatsa
>
> ICP has two backlight controllers - similar to previous platforms like
> BXT.
>
> v2: Remove the usage of ICP_SECOND_PPS_BACKLIGHT register.(Jani)
> Reuse BXT code since it is very similar.(Ville)
>
> v3 (
Hi,
On 11-01-18 22:17, Ville Syrjälä wrote:
On Thu, Jan 11, 2018 at 08:53:42PM +, Chris Wilson wrote:
Quoting Ville Syrjälä (2018-01-11 20:10:45)
On Wed, Jan 10, 2018 at 12:55:05PM +, Chris Wilson wrote:
While we talk to the punit over its sideband, we need to prevent the cpu
from sle
On 09/01/18 15:28, Paulo Zanoni wrote:
From: kgardine
This patch clears a single bit. The bit is 0 by default but expected not to be
set. Explicitly clearing the bit in this patch is intended to indicate some
thinking has occurred, and that we want this bit cleared and we are not just
excepti
On Thu, Jan 11, 2018 at 08:53:42PM +, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-01-11 20:10:45)
> > On Wed, Jan 10, 2018 at 12:55:05PM +, Chris Wilson wrote:
> > > While we talk to the punit over its sideband, we need to prevent the cpu
> > > from sleeping in order to prevent a pote
This could potentially be squashed with patch 15, as it doesn't make
much sense to add a TODO there and solve it here. We might also want to
update the comment above intel_lr_context_descriptor_update to remove
the implication that SW context ID == ctx->hw_id (which is still
technically true af
The review from Chris had ended up in my spam folder and I missed it,
apologies for duplicating some of the comments.
Daniele
On 11/01/18 11:55, Daniele Ceraolo Spurio wrote:
On 09/01/18 15:28, Paulo Zanoni wrote:
From: Thomas Daniel
Supports two-element submission using the new enhanced
Quoting Ville Syrjälä (2018-01-11 20:10:45)
> On Wed, Jan 10, 2018 at 12:55:05PM +, Chris Wilson wrote:
> > While we talk to the punit over its sideband, we need to prevent the cpu
> > from sleeping in order to prevent a potential machine hang.
> >
> > Note that by itself, it appears that pm_q
On Thu, Jan 11, 2018 at 06:00:03PM +, Paulo Zanoni wrote:
> From: Rodrigo Vivi
>
> Some Cannonlake SKUs will come with a full split between
> port A and port E. This will be called port F although it
> is not a 6th port, but only a split.
>
> Note this patch alone is not sufficient for port
Hi all,
Tvrtko found a few bugs in the previous iteration of this series and
also made quite a few recommendations on the stored internal state as
well uapi, so here is an update. Details in the patches.
Thanks a lot,
Lionel Landwerlin (6):
drm/i915: store all subslice masks
drm/i915/debugfs
On Thu, Jan 11, 2018 at 05:27:52AM +, Ramalingam C wrote:
>
>
> On Wednesday 10 January 2018 11:45 PM, Rodrigo Vivi wrote:
>
> On Wed, Jan 10, 2018 at 02:47:00PM +, Lohith BS wrote:
>
> Dynamic Refresh Rate Switch(DRRS) is used to switch the panel's
> refresh rate to
On Wed, Jan 10, 2018 at 12:55:05PM +, Chris Wilson wrote:
> While we talk to the punit over its sideband, we need to prevent the cpu
> from sleeping in order to prevent a potential machine hang.
>
> Note that by itself, it appears that pm_qos_update_request (via
> intel_idle) doesn't provide a
Hi,
On 10-01-18 14:18, Hans de Goede wrote:
Hi,
On 10-01-18 13:55, Chris Wilson wrote:
While we talk to the punit over its sideband, we need to prevent the cpu
from sleeping in order to prevent a potential machine hang.
Note that by itself, it appears that pm_qos_update_request (via
intel_idl
Now that we have that information in topology fields, let's just reused it.
v2: Style tweaks (Tvrtko)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 27 +++
1 file changed, 11 insertions(+), 16 deletions(-)
diff -
This might be useful information for developers looking at an error
state.
v2: Place topology towards the end of the error state (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_gpu_error.c | 40 +++
1 file changed, 40 insertions(+)
diff --
Up to now, subslice mask was assumed to be uniform across slices. But
starting with Cannonlake, slices can be asymmetric (for example slice0
has different number of subslices as slice1+). This change stores all
subslices masks for all slices rather than having a single mask that
applies to all slic
On Thu, Jan 11, 2018 at 06:23:20PM +, Oscar Mateo wrote:
> From: Tvrtko Ursulin
>
> Gen11 removes the Resource Streamer, which frees up a big chunk of
> the context image. BSpec indicates 12538 DWORDs (13 pages), plus
> one page for PPHWSP.
>
> Please notice that, when looking at the BSpec c
On 09/01/18 15:28, Paulo Zanoni wrote:
From: Thomas Daniel
Supports two-element submission using the new enhanced execlist mechanism
This could use a few lines to describe enhanced execlist. Something like:
"Enhanced Execlists is an upgraded version of execlists which supports
up to 8 po
With the introduction of asymmetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam to tell userspace what subslices
are available. Here we introduce a more detailed way of querying the
Gen's GPU topology that doesn't aggregate numbers.
This is essential for monitoring parts o
There are a number of information that are readable from hardware
registers and that we would like to make accessible to userspace. One
particular example is the topology of the execution units (how are
execution units grouped in subslices and slices and also which ones
have been fused off for die
While the end goal is to make this information available to userspace
through a new ioctl, there is no reason we can't display it in a human
readable fashion through debugfs.
slice0: 3 subslice(s) (0x7):
subslice0: 8 EUs (0xff)
subslice1: 8 EUs (0xff)
subslice2: 8 EUs (0xff
On 10/01/18 02:12, Chris Wilson wrote:
Quoting Paulo Zanoni (2018-01-09 23:23:17)
From: Tvrtko Ursulin
Since it is not possible to mask individual engine instances
and they are all permanently unmasked we do not need to do
anything for engine interrupt management.
This scares me as we will
== Series Details ==
Series: ICP initial support
URL : https://patchwork.freedesktop.org/series/36350/
State : success
== Summary ==
Test kms_atomic_transition:
Subgroup plane-all-modeset-transition-fencing:
dmesg-warn -> PASS (shard-hsw) fdo#102614 +1
Test gem_ti
On Thu, Jan 11, 2018 at 10:31 AM, Rodrigo Vivi wrote:
> On Thu, Jan 11, 2018 at 06:20:53PM +, Anuj Phogat wrote:
>> Rodrigo, Can you push it upstream for me?
>
> I just pushed the libdrm.
>
> Do I also need to push the mesa one?
>
No, I've pushed the mesa patch. Thanks.
> Thanks,
> Rodrigo.
>
On 11/01/18 12:45, Tvrtko Ursulin wrote:
On 18/12/2017 15:35, Lionel Landwerlin wrote:
With the introduction of asymetric slices in CNL, we cannot rely on
asymmetric
Check ;)
the previous SUBSLICE_MASK getparam to tell userspace what subslices
are available. Here we introduce a more det
On Thu, Jan 11, 2018 at 06:20:53PM +, Anuj Phogat wrote:
> Rodrigo, Can you push it upstream for me?
I just pushed the libdrm.
Do I also need to push the mesa one?
Thanks,
Rodrigo.
>
> Thanks
> Anuj
>
> On Wed, Jan 10, 2018 at 4:50 PM, Rodrigo Vivi wrote:
> > On Wed, Jan 10, 2018 at 11:5
From: Kelvin Gardiner
ICL 11 has a greater number of maximum subslices. This patch
reflects this.
v2: GEN11 updates to MCR_SELECTOR (Oscar)
Bspec: 21139
BSpec: 21108
Reviewed-by: Daniele Ceraolo Spurio (v1)
Signed-off-by: Kelvin Gardiner
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/
== Series Details ==
Series: ICP initial support
URL : https://patchwork.freedesktop.org/series/36350/
State : success
== Summary ==
Series 36350v1 ICP initial support
https://patchwork.freedesktop.org/api/1.0/series/36350/revisions/1/mbox/
Test debugfs_test:
Subgroup read_all_entries
From: Tvrtko Ursulin
Gen11 removes the Resource Streamer, which frees up a big chunk of
the context image. BSpec indicates 12538 DWORDs (13 pages), plus
one page for PPHWSP.
Please notice that, when looking at the BSpec context image table,
the right filter has to be applied (e.g. "IcelakeLP") a
Rodrigo, Can you push it upstream for me?
Thanks
Anuj
On Wed, Jan 10, 2018 at 4:50 PM, Rodrigo Vivi wrote:
> On Wed, Jan 10, 2018 at 11:51:02PM +, Anuj Phogat wrote:
>> Cc: Rodrigo Vivi
>> Cc: Anusha Srivatsa
>> Signed-off-by: Anuj Phogat
>
> Reviewed-by: Rodrigo Vivi
>
>> ---
>> intel/
On 01/10/2018 05:21 PM, Rodrigo Vivi wrote:
On Tue, Jan 09, 2018 at 11:28:19PM +, Paulo Zanoni wrote:
From: Tvrtko Ursulin
The current size may be bigger than the correct one, this needs to be
revisited later.
I don't believe this is true anymore. When this was written initially CNL had
From: Anusha Srivatsa
Add register definitions for setting the rawclock.
Set the numerator,denominator and divider values.
v2: Simplify the commit message. Simplify the math.
Add register bits for numerator. (Paulo)
v3 (from Paulo): coding style bikesheds.
Reviewed-by: Paulo Zanoni
Signed-off
From: Anusha Srivatsa
ICP, like BXT, has has two panel power sequencers.
v2: Simplify the code. Remove unwanted register definitions.
Make code as close to BXT style as possible. (Ville)
Also, remove the use of ICP_SECOND_PPS_BACKLIGHT for now.
Moving forward, if we are sure we need to set this
From: Anusha Srivatsa
In ICP, there are three TC ports and 3 DDI ports.
v2:
- Correct Pin mapping.
v3:
- Update pin mapping into per platform implementation
rather than previous approach of port wise mapping.
v4:
- Update GMBUS_NUM_PINS (Paulo)
v5:
- rebase.
v6:
- Update function name, G
From: Anusha Srivatsa
ICP has two backlight controllers - similar to previous platforms like
BXT.
v2: Remove the usage of ICP_SECOND_PPS_BACKLIGHT register.(Jani)
Reuse BXT code since it is very similar.(Ville)
v3 (from Paulo): Rebase.
Cc: Jani Nikula
Cc: Ville Syrjala
Reviewed-by: Paulo Zan
From: Anusha Srivatsa
Add the PCI ID for the ICL PCH - ICP.
v2: rebased.
v3: rebased.
v4: fix ICP name.
v5: fix the ID mask (Fei Li).
v6 (from Paulo): bikesheds.
Cc: Li, Fei
Reviewed-by: Paulo Zanoni
Signed-off-by: Anusha Srivatsa
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_d
From: Rodrigo Vivi
Some Cannonlake SKUs will come with a full split between
port A and port E. This will be called port F although it
is not a 6th port, but only a split.
Note this patch alone is not sufficient for port F enabling,
it's just the first step.
v2: Fix size of dvo_ports found by An
From: Anusha Srivatsa
Add the enum additions to ICP PCH.
v2 (from Paulo): don't set any platforms to it yet since ICP support is
incomplete.
v3 (from Rodrigo): Fix ICP name.
Reviewed-by: Paulo Zanoni
Signed-off-by: Anusha Srivatsa
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_dr
From: Rodrigo Vivi
Icelake is an Intel® Processor containing an Intel® Graphics
Controller.
This is just an initial Icelake definition. PCI IDs, Icelake support
and new features coming in following patches.
v2: Add .ddb_size and .has_guc (Michal Wajdeczko).
v3: Add the ICL_FEATURES macro (Kelvi
Hi
This series adds the initial support for ICP. No conflicts with the other
series. Patches 1 and 2 are parts of other series that we've already been
discussing on this mailing list, but I put them here so CI can do the right
thing.
I have just re-reviewed all of Anusha's patches and my reviewed
Applied all of your comments here.
On 11/01/18 12:19, Tvrtko Ursulin wrote:
On 18/12/2017 15:35, Lionel Landwerlin wrote:
There are a number of information that are readable from hardware
registers and that we would like to make accessible to userspace. One
particular example is the topology o
On 11/01/18 11:31, Tvrtko Ursulin wrote:
On 18/12/2017 15:35, Lionel Landwerlin wrote:
While the end goal is to make this information available to userspace
through a new ioctl, there is no reason we can't display it in a human
readable fashion through debugfs.
slice0 (subslice_mask=0x7):
I'
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: Don't enable GuC when vGPU is
active
URL : https://patchwork.freedesktop.org/series/36343/
State : failure
== Summary ==
Series 36343v1 series starting with [1/2] drm/i915/guc: Don't enable GuC when
vGPU is active
https://
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_params.c | 2 +-
drivers/gpu/drm/i915/i915_params.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index b5f3eb4..a9cc03a 100644
--- a/dr
In GVT-g, if GuC is to be used it is to be loaded by Host and not by
VM/vGPU. Currently, GVT-g host is not supported with GuC submission.
Also currently vGPU is to be not supported with GuC submission AFAIK.
CI BAT highlighted GuC init issue on skl-gvtdvm due to lack of movntdqa
needed for logging
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/guc: Redefine guc_log_level
modparam values
URL : https://patchwork.freedesktop.org/series/36341/
State : success
== Summary ==
Series 36341v1 series starting with [v2,1/2] drm/i915/guc: Redefine
guc_log_level modparam value
== Series Details ==
Series: drm/i915/pmu: Initialise our dynamic sysfs attributes for use with
lockdep
URL : https://patchwork.freedesktop.org/series/36337/
State : failure
== Summary ==
Test kms_plane_multiple:
Subgroup atomic-pipe-a-tiling-none:
pass -> SKIP
On 11/01/18 11:12, Tvrtko Ursulin wrote:
*/
+ eu_en = ~I915_READ(GEN8_EU_DISABLE0);
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ sseu->eu_mask[ss] = (eu_en >> (8 * ss)) & eu_mask;
+ /* Slice1 */
+ sseu->eu_mask[sseu->max_subslices] = (eu_en >> 24) &
eu_mask;
+
On 11/01/2018 15:48, Lionel Landwerlin wrote:
On 11/01/18 11:12, Tvrtko Ursulin wrote:
On 18/12/2017 15:35, Lionel Landwerlin wrote:
Up to now, subslice mask was assumed to be uniform across slices. But
starting with Cannonlake, slices can be asymetric (for example slice0
asymmetric, thanks
Today we have format mismatch between read/write operations
of i915_guc_log_control entry. For read we return (0, 1..4)
that represents disable/verbosity levels, but for write we
force user to follow internal structure format (0,1,9,11,13).
Let's hide internals from the user and accept same values
We used value -1 to indicate "disabled" and values 0..3 to
indicate "enabled", but most of our other modparams are using
-1 for "auto" mode and 0 for "disable". For consistency let's
change our log level values to:
-1: auto (depends on platform and Kconfig.debug settings)
0: disabled
1: enabled
On 11/01/18 11:21, Tvrtko Ursulin wrote:
On 18/12/2017 15:35, Lionel Landwerlin wrote:
Now that we have that information in topology fields, let's just
reused it.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 ++
1 file changed, 10 i
On 11/01/18 11:12, Tvrtko Ursulin wrote:
On 18/12/2017 15:35, Lionel Landwerlin wrote:
Up to now, subslice mask was assumed to be uniform across slices. But
starting with Cannonlake, slices can be asymetric (for example slice0
asymmetric, thanks auto spell checker. :)
Done, thanks.
has
Hi Dave -
Hopefully final drm/i915 fixes for v4.15:
- Fix a KASAN reported use after free
- Whitelist a register to avoid hangs
- GVT fixes
BR,
Jani.
The following changes since commit b2cd1df66037e7c4697c7e40496bf7e4a5e16a2d:
Linux 4.15-rc7 (2018-01-07 14:22:41 -0800)
are available in the
Quoting Tvrtko Ursulin (2018-01-11 14:12:38)
> You beat me to it, after I noticed the report on IRC and started
> digging, just to find sysfs_attr_init, your fix arrived. Thanks!
>
> It looks like a standard way of silencing lockdep for this case,
> although I am not sure what exactly is the pur
Quoting Patchwork (2018-01-11 14:39:43)
> == Series Details ==
>
> Series: drm/i915/pmu: Initialise our dynamic sysfs attributes for use with
> lockdep
> URL : https://patchwork.freedesktop.org/series/36337/
> State : success
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01
Hello,
I have an old Lenovo Thinkpad X60 laptop with a Core 2 Duo T7200 CPU and
i945GM integrated graphics whose graphics broke when I tried to update the
kernel to get the Meltdown fixes.
GRUB2 shows a graphical boot menu, and Linux displays the Tux boot logos
correctly at first. However, alm
HI,
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Petri Latvala
> Sent: torstai 11. tammikuuta 2018 12.02
> To: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Ignore TMDS clock
> limit f
== Series Details ==
Series: drm/i915/pmu: Initialise our dynamic sysfs attributes for use with
lockdep
URL : https://patchwork.freedesktop.org/series/36337/
State : success
== Summary ==
Series 36337v1 drm/i915/pmu: Initialise our dynamic sysfs attributes for use
with lockdep
https://patchw
Em Sex, 2017-12-22 às 15:18 -0800, Rodrigo Vivi escreveu:
> Some Cannonlake SKUs will come with a full split between
> port A and port E. This will be called port F although it
> is not a 6th port, but only a split.
I think that a small comment explaining that port F support is still
not complete
Em Sex, 2017-12-22 às 15:18 -0800, Rodrigo Vivi escreveu:
> On CNP Pin 3 is for misc of Port F usage depending on the
> configuration. For CNL that uses Port F, pin 3 is the one.
>
> v2: Make it more generic and update commit message.
Reviewed-by: Paulo Zanoni
>
> Cc: Anusha Srivatsa
> Cc: Lu
On 11/01/2018 14:04, Chris Wilson wrote:
As we kmalloc our dynamic sysfs attributes, we have to give them an
external static lock_class_key for them to use with lockdep.
Fixes: 109ec558370f ("drm/i915/pmu: Only enumerate available counters in sysfs")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursu
Den 11.01.2018 08.45, skrev Daniel Vetter:
On Wed, Jan 10, 2018 at 06:02:38PM +0100, Noralf Trønnes wrote:
Den 09.01.2018 11.38, skrev Daniel Vetter:
On Wed, Jan 03, 2018 at 11:21:08PM +0100, Noralf Trønnes wrote:
Prepare for generic fbdev emulation by letting DRM core work directly
with the
As we kmalloc our dynamic sysfs attributes, we have to give them an
external static lock_class_key for them to use with lockdep.
Fixes: 109ec558370f ("drm/i915/pmu: Only enumerate available counters in sysfs")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_pmu.c |
== Series Details ==
Series: series starting with [1/1] tools: Update .gitignore
URL : https://patchwork.freedesktop.org/series/36322/
State : failure
== Summary ==
IGT patchset tested on top of latest successful build
d37369c7146a2ceb332592297d311d501c1c748e Revert "build: make meson more
of
== Series Details ==
Series: build: make meson more official
URL : https://patchwork.freedesktop.org/series/36320/
State : failure
== Summary ==
Applying: build: make meson more official
Using index info to reconstruct a base tree...
M CONTRIBUTING
M NEWS
M README
M mes
== Series Details ==
Series: series starting with [v2,1/2] tests/perf_pmu: Verify busyness when PMU
is enabled after engine got busy (rev3)
URL : https://patchwork.freedesktop.org/series/36201/
State : failure
== Summary ==
IGT patchset tested on top of latest successful build
d37369c7146a2ce
Regards
Shashank
On 1/10/2018 9:53 PM, Ville Syrjälä wrote:
On Wed, Jan 10, 2018 at 10:07:43AM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 1/9/2018 11:31 PM, Ville Syrjälä wrote:
On Thu, Dec 28, 2017 at 08:32:05PM +0530, Sharma, Shashank wrote:
On 12/22/2017 11:58 PM, Ville Syrjal
On 15.12.2017 23:19, Rodrigo Vivi wrote:
> On Fri, Dec 15, 2017 at 04:39:25PM +, Ingo Molnar wrote:
>>
>> * Lucas De Marchi wrote:
>>
>>> CFL was missing from intel_early_ids[]. The PCI ID needs to be there to
>>> allow the memory region to be stolen, otherwise we could have RAM being
>>> arbi
On 18/12/2017 15:35, Lionel Landwerlin wrote:
With the introduction of asymetric slices in CNL, we cannot rely on
asymmetric
the previous SUBSLICE_MASK getparam to tell userspace what subslices
are available. Here we introduce a more detailed way of querying the
Gen's GPU topology that doesn
On 18/12/2017 15:35, Lionel Landwerlin wrote:
There are a number of information that are readable from hardware
registers and that we would like to make accessible to userspace. One
particular example is the topology of the execution units (how are
execution units grouped in subslices and slices
> -Original Message-
> From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com]
> Sent: Thursday, January 11, 2018 1:46 PM
> To: Lofstedt, Marta ; intel-
> g...@lists.freedesktop.org
> Cc: Chris Wilson
> Subject: Re: [Intel-gfx] [PATCH i-g-t 1/2] test/gem_ctx_param - Use the last
> I
On 11/01/2018 11:38, Marta Lofstedt wrote:
The invalid-param-[get|set] exploits the last I915_CONTEXT_PARAM + 1,
to check for ABI extentsions. However, the last param was set to
I915_CONTEXT_PARAM_BANNABLE, so when I915_CONTEXT_PARAM_PRIORITY was
added to the next enum, the test started failing.
The invalid-param-[get|set] exploits the last I915_CONTEXT_PARAM + 1,
to check for ABI extentsions. However, the last param was set to
I915_CONTEXT_PARAM_BANNABLE, so when I915_CONTEXT_PARAM_PRIORITY was
added to the next enum, the test started failing.
Bugzilla: https://bugs.freedesktop.org/show_
On 18/12/2017 15:35, Lionel Landwerlin wrote:
While the end goal is to make this information available to userspace
through a new ioctl, there is no reason we can't display it in a human
readable fashion through debugfs.
slice0 (subslice_mask=0x7):
I'd add a subslice count while at it, since
On 18/12/2017 15:35, Lionel Landwerlin wrote:
Now that we have that information in topology fields, let's just reused it.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 ++
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a
On 18/12/2017 15:35, Lionel Landwerlin wrote:
Up to now, subslice mask was assumed to be uniform across slices. But
starting with Cannonlake, slices can be asymetric (for example slice0
asymmetric, thanks auto spell checker. :)
has different number of subslices as slice1+). This change store
On Thu, Jan 11, 2018 at 9:58 AM, Petri Latvala wrote:
> On Thu, Jan 11, 2018 at 09:51:40AM +0100, Daniel Vetter wrote:
>> I also noticed that meson.sh doesn't set the prefix for patch
>> submission. Fix that (even thought hopefully real soon igt will move
>> to its own list).
>>
>> Cc: Petri Latva
On 11/01/2018 09:09, Patchwork wrote:
== Series Details ==
Series: drm/i915/pmu: Only enumerate available counters in sysfs (rev3)
URL : https://patchwork.freedesktop.org/series/35689/
State : success
== Summary ==
Series 35689v3 drm/i915/pmu: Only enumerate available counters in sysfs
http
On 11/01/2018 08:45, Patchwork wrote:
== Series Details ==
Series: drm/i915: Apply headless DMC workaround for CNL
URL : https://patchwork.freedesktop.org/series/36317/
State : success
== Summary ==
Series 36317v1 drm/i915: Apply headless DMC workaround for CNL
https://patchwork.freedesktop
On Thu, Jan 11, 2018 at 09:54:02AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Ignore TMDS clock limit for DP++ when EDID override is set
> (rev2)
> URL : https://patchwork.freedesktop.org/series/35338/
> State : failure
>
> == Summary ==
>
> Warning: bzip CI_DRM_3609
> -Original Message-
> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
> Sent: Tuesday, January 9, 2018 3:32 PM
> To: Srinivas, Vidya ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 14/15] drm/i915: Add NV12 as supported
> format for sprite plane
== Series Details ==
Series: drm/i915: Ignore TMDS clock limit for DP++ when EDID override is set
(rev2)
URL : https://patchwork.freedesktop.org/series/35338/
State : failure
== Summary ==
Warning: bzip CI_DRM_3609/shard-glkb6/results32.json.bz2 wasn't in correct JSON
format
Test kms_cursor_
On Fri, Jan 05, 2018 at 02:13:22PM +, Chris Wilson wrote:
> When reprioritising a request, we build a list of its dependencies in
> topological order. This should leave our origin request as the first
> element in our list, if it moves we have a dependency cycle and severe
> breakage. Assert th
On 1/11/2018 2:54 PM, Michal Wajdeczko wrote:
On Thu, 11 Jan 2018 06:52:18 +0100, Sagar Arun Kamble
wrote:
On 1/10/2018 9:35 PM, Michal Wajdeczko wrote:
We used value -1 to indicate "disabled" and values 0..3 to
indicate "enabled", but most of our other modparams are using
-1 for "auto"
On Thu, 2018-01-11 at 11:27 +0200, Petri Latvala wrote:
> Fixes: 834321a5d76a ("tools: Cannonlake port clock programming")
Reviewed-by: Mika Kahola
> Signed-off-by: Petri Latvala
> Cc: Mika Kahola
> ---
> tools/.gitignore | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/tools/.gitign
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