From: Ankitprasad Sharma
Propagating correct error codes to userspace by using ERR_PTR and
PTR_ERR macros for stolen memory based object allocation. We generally
return -ENOMEM to the user whenever there is a failure in object
allocation. This patch helps user to identify the correct reason for t
From: Ankitprasad Sharma
Extend the drm_i915_gem_create structure to add support for
creating Stolen memory backed objects. Added a new flag through
which user can specify the preference to allocate the object from
stolen memory, which if set, an attempt will be made to allocate
the object from s
From: Ankitprasad Sharma
This patch adds support for clearing buffer objects via CPU/GTT. This
is particularly useful for clearing out the non shmem backed objects.
Currently intend to use this only for buffers allocated from stolen
region.
v2: Added kernel doc for i915_gem_clear_object(), corre
From: Chris Wilson
If we run out of stolen memory when trying to allocate an object, see if
we can reap enough purgeable objects to free up enough contiguous free
space for the allocation. This is in principle very much like evicting
objects to free up enough contiguous space in the vma when bind
From: Chris Wilson
Ville reminded us that stolen memory is not preserved across
hibernation, and a result of this was that context objects now being
allocated from stolen were being corrupted on S4 and promptly hanging
the GPU on resume.
We want to utilise stolen for as much as possible (nothing
From: Ankitprasad Sharma
This patch series adds support for creating/using Stolen memory backed
objects.
Despite being a unified memory architecture (UMA) some bits of memory
are more equal than others. In particular we have the thorny issue of
stolen memory, memory stolen from the system by the
From: Ankitprasad Sharma
This patch adds support for extending the pread/pwrite functionality
for objects not backed by shmem. The access will be made through
gtt interface.
This will cover prime objects as well as stolen memory backed objects
but for userptr objects it is still forbidden.
v2: D
Reuse what is programmed by pre-os, but in case there is no pre-os
initialization, init the cdclk with the max value by default untill
dynamic cdclk support comes.
v2: Check if BIOS programmed correctly rather than always calling init
- Do validation of programmed cdctl and what it is expected
Hi Daniel,
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of
> Daniel Vetter
> Sent: Wednesday, October 07, 2015 9:39 PM
> To: Yang, Libin
> Cc: intel-gfx@lists.freedesktop.org; daniel.vet...@ffwll.ch;
> jani.nik...@linux.intel.com; ville.syrj...@linux
Hi all, I recently purchased one of these NUCs to use as a general purpose
server and stream some Steam games to my living room and need some help
getting setup. I heard Ubuntu was what they developed Steam for Linux on,
so I started by installing Ubuntu 15.04 and then tried the Intel Graphics
Inst
From: Clint Taylor
The TMDS_296M define was computing as 296704 but the mode->clock is
296700 as defined by EDID. Adjusted define to allow correct detection
of the need to program the correct N value for 29.97 and 23.98 refresh
rate.
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_a
Hi Tvrtko,
On Wed, 7 Oct 2015 15:07:30 +0100
Tvrtko Ursulin wrote:
>
> Hi,
>
> On 07/10/15 03:35, Vivek Kasireddy wrote:
> > This new subtest will validate a Y-tiled object's tiling mode
> > against its associated fb modifier.
> >
> > Cc: Tvrtko Ursulin
> > Signed-off-by: Vivek Kasireddy
>
From: Ville Syrjälä
Apparently writing the DPLL register P1/P2 divider fields won't trigger
an actual change in the DPLL output unless VGA mode is enabled for
prior to the register write that changes the P1/P2 dividers. The write
with the new P1/P2 divider can itself disable VGA mode again withou
From: Ville Syrjälä
We accidentally lost the initial DPLL register write in
1c4e02746147 drm/i915: Fix DVO 2x clock enable on 830M
The "three times for luck" hack probably saved us from a total
disaster. But anyway, bring the initial write back so that the
code actually makes some sense.
Cc: st
On Wed, Oct 07, 2015 at 02:50:34PM -0400, Nick Bowler wrote:
> On 10/7/15, Ville Syrjälä wrote:
> > On Wed, Oct 07, 2015 at 10:29:22AM -0400, Nick Bowler wrote:
> >> On 10/7/15, Ville Syrjälä wrote:
> >> > On Tue, Oct 06, 2015 at 11:42:33AM -0400, Nick Bowler wrote:
> >> >> On 9/24/15, Nick Bowle
On 10/7/15, Ville Syrjälä wrote:
> On Wed, Oct 07, 2015 at 10:29:22AM -0400, Nick Bowler wrote:
>> On 10/7/15, Ville Syrjälä wrote:
>> > On Tue, Oct 06, 2015 at 11:42:33AM -0400, Nick Bowler wrote:
>> >> On 9/24/15, Nick Bowler wrote:
>> >> > Testing out 4.3-rc2, first thing I notice is that the
From: Chris Wilson
A long time ago (before 3.14) we relied on a permanent pinning of the
ifbdev to lock the fb in place inside the GGTT. However, the
introduction of stealing the BIOS framebuffer and reusing its address in
the GGTT for the fbdev has muddied waters and we use an inherited fb.
Howe
On 10/07/2015 10:17 AM, David Woodhouse wrote:
> On Wed, 2015-10-07 at 09:28 -0700, Jesse Barnes wrote:
>> On 10/07/2015 09:14 AM, Daniel Vetter wrote:
>>> On Wed, Oct 07, 2015 at 08:16:42AM -0700, Jesse Barnes wrote:
On 10/07/2015 06:00 AM, David Woodhouse wrote:
> On Fri, 2015-09-04 at 0
On Wed, 2015-10-07 at 09:28 -0700, Jesse Barnes wrote:
> On 10/07/2015 09:14 AM, Daniel Vetter wrote:
> > On Wed, Oct 07, 2015 at 08:16:42AM -0700, Jesse Barnes wrote:
> > > On 10/07/2015 06:00 AM, David Woodhouse wrote:
> > > > On Fri, 2015-09-04 at 09:59 -0700, Jesse Barnes wrote:
> > > > > +
> >
On 10/07/2015 09:14 AM, Daniel Vetter wrote:
> On Wed, Oct 07, 2015 at 08:16:42AM -0700, Jesse Barnes wrote:
>> On 10/07/2015 06:00 AM, David Woodhouse wrote:
>>> On Fri, 2015-09-04 at 09:59 -0700, Jesse Barnes wrote:
+
+ ret = handle_mm_fault(mm, vma, address,
+
On Wed, Oct 07, 2015 at 04:52:46PM +0100, Daniel Stone wrote:
> Hi,
>
> On 2 October 2015 at 11:56, Daniel Vetter wrote:
> > Logical negation is hard.
> >
> > Cc: "Morton, Derek J"
> > Signed-off-by: Daniel Vetter
>
> Almost identical to what I had locally.
>
> s/second integers/second intege
On Wed, Oct 07, 2015 at 04:57:25PM +0100, Tvrtko Ursulin wrote:
>
> Hi,
>
> On 06/10/15 11:39, Chris Wilson wrote:
> >Since the remove of the pin-ioctl, we only care about not changing the
> >cache level on buffers pinned to the hardware as indicated by
> >obj->pin_display. So we can safely repla
On Tue, Oct 06, 2015 at 11:04:53PM -0400, Alex Deucher wrote:
> On Tue, Oct 6, 2015 at 11:10 AM, Johannes Stezenbach wrote:
> >
> > I have a NEC EA244WMi monitor connected to an Asus P8H77-V
> > mainboard with Ivy Bridge Core i5-3550 via DVI.
> > If DPMS suspend is enabled (by xscreensaver, or for
On 10/7/15, Nick Bowler wrote:
> On 10/7/15, Ville Syrjälä wrote:
>> On Wed, Oct 07, 2015 at 10:29:22AM -0400, Nick Bowler wrote:
>>> On 10/7/15, Ville Syrjälä wrote:
>>> > On Tue, Oct 06, 2015 at 11:42:33AM -0400, Nick Bowler wrote:
>>> >> On 9/24/15, Nick Bowler wrote:
>>> >> > Testing out 4.
On 10/7/15, Ville Syrjälä wrote:
> On Wed, Oct 07, 2015 at 10:29:22AM -0400, Nick Bowler wrote:
>> On 10/7/15, Ville Syrjälä wrote:
>> > On Tue, Oct 06, 2015 at 11:42:33AM -0400, Nick Bowler wrote:
>> >> On 9/24/15, Nick Bowler wrote:
>> >> > Testing out 4.3-rc2, first thing I notice is that the
On 10/7/15, Ville Syrjälä wrote:
> On Tue, Oct 06, 2015 at 11:42:33AM -0400, Nick Bowler wrote:
>> On 9/24/15, Nick Bowler wrote:
>> > Testing out 4.3-rc2, first thing I notice is that the VGA output is
>> > not working. Specifically, the display is continuously powering on
>> > and off -- at no
Hi,
I have a NEC EA244WMi monitor connected to an Asus P8H77-V
mainboard with Ivy Bridge Core i5-3550 via DVI.
If DPMS suspend is enabled (by xscreensaver, or for testing by
"xset dpms force off/suspend/standby"), the monitor
enters standby mode but wakes up every 10...30 seconds for
6 seconds to
Hi Dave,
drm-intel-next-2015-09-28:
- fastboot by default for some systems (Maarten Lankhorts)
- piles of workarounds for bxt and skl
- more fbc work from Paulo
- fix hdmi hotplug detection (Sonika)
- first few patches from Ville to parametrize register macros, prep work for
typesafe mmio functi
On Wed, Oct 07, 2015 at 08:16:42AM -0700, Jesse Barnes wrote:
> On 10/07/2015 06:00 AM, David Woodhouse wrote:
> > On Fri, 2015-09-04 at 09:59 -0700, Jesse Barnes wrote:
> >> +
> >> + ret = handle_mm_fault(mm, vma, address,
> >> + desc.wr_req ? FAULT_FLAG_WRITE : 0
On Tue, Oct 06, 2015 at 03:52:03PM +0100, Nick Hoath wrote:
> Pin the hw ctx mapping so that it is not mapped/unmapped per bb
> when doing GuC submission.
>
> Issue: VIZ-4277
> Cc: David Gordon
> Signed-off-by: Nick Hoath
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 14 --
> drivers/gp
On Wed, Oct 07, 2015 at 06:03:48PM +0200, Daniel Vetter wrote:
> On Tue, Oct 06, 2015 at 03:52:01PM +0100, Nick Hoath wrote:
> > There is a desire to simplify the i915 driver by reducing the number of
> > different code paths introduced by the LRC / execlists support. As the
> > execlists request
On Tue, Oct 06, 2015 at 03:52:02PM +0100, Nick Hoath wrote:
> Shovel all context related objects through the active queue and obj
> management.
>
> - Added callback in vma_(un)bind to add CPU (un)mapping at same time
> if desired
> - Inserted LRC hw context & ringbuf to vma active list
>
> Issu
On Tue, Oct 06, 2015 at 03:52:01PM +0100, Nick Hoath wrote:
> There is a desire to simplify the i915 driver by reducing the number of
> different code paths introduced by the LRC / execlists support. As the
> execlists request is now part of the gem request it is possible and
> desirable to unify
Hi,
On 06/10/15 11:39, Chris Wilson wrote:
Since the remove of the pin-ioctl, we only care about not changing the
cache level on buffers pinned to the hardware as indicated by
obj->pin_display. So we can safely replace i915_gem_object_is_pinned()
i915_gem_obj_is_pinned
here with a plain obj
Hi,
On 2 October 2015 at 11:56, Daniel Vetter wrote:
> Logical negation is hard.
>
> Cc: "Morton, Derek J"
> Signed-off-by: Daniel Vetter
Almost identical to what I had locally.
s/second integers/second integer/ and:
Reviewed-by: Daniel Stone
Cheers,
Daniel
_
On Wed, Oct 07, 2015 at 04:30:06PM +0200, Daniel Vetter wrote:
> On Wed, Oct 07, 2015 at 04:27:24PM +0300, Ville Syrjälä wrote:
> > On Wed, Oct 07, 2015 at 11:17:45AM +0300, Jani Nikula wrote:
> > > Signed-off-by: Jani Nikula
> > > ---
> > > drivers/gpu/drm/i915/i915_gem_gtt.c | 7 ---
> > >
On Wed, Oct 07, 2015 at 10:29:22AM -0400, Nick Bowler wrote:
> On 10/7/15, Ville Syrjälä wrote:
> > On Tue, Oct 06, 2015 at 11:42:33AM -0400, Nick Bowler wrote:
> >> On 9/24/15, Nick Bowler wrote:
> >> > Testing out 4.3-rc2, first thing I notice is that the VGA output is
> >> > not working. Spec
On 10/07/2015 06:00 AM, David Woodhouse wrote:
> On Fri, 2015-09-04 at 09:59 -0700, Jesse Barnes wrote:
>> +
>> + ret = handle_mm_fault(mm, vma, address,
>> + desc.wr_req ? FAULT_FLAG_WRITE : 0);
>> + if (ret & VM_FAULT_ERROR) {
>> + gpu_mm_segv
On Wed, Oct 07, 2015 at 02:44:02PM +0300, Francisco Jerez wrote:
> intel_rcs_ctx_init() emits all workaround register writes on the list
> to the ring, in addition to calling i915_gem_render_state_init(). The
> workaround list is currently empty on Gen6-7 so this shouldn't cause
> any functional c
On Wed, Oct 07, 2015 at 02:44:01PM +0300, Francisco Jerez wrote:
> It's not an error for the workaround list to be empty if no
> workarounds are needed. This will avoid spamming the logs
> unnecessarily on Gen6 after the workaround list is hooked up on
> pre-Gen8 hardware by the following commits.
On Wed, Oct 07, 2015 at 03:55:31PM +0200, Daniel Vetter wrote:
> On Tue, Oct 06, 2015 at 05:31:30PM +, Vivi, Rodrigo wrote:
> > On Tue, 2015-10-06 at 12:09 +0300, Jani Nikula wrote:
> > > On Tue, 06 Oct 2015, Rodrigo Vivi wrote:
> > > > From: Deepak S
> > > >
> > > > v2: separate out device
On Thu, Oct 01, 2015 at 07:13:11PM +0300, Francisco Jerez wrote:
> Daniel Vetter writes:
>
> > In
> >
> > commit 8f0e2b9d95a88ca5d8349deef2375644faf184ae
> > Author: Daniel Vetter
> > Date: Tue Dec 2 16:19:07 2014 +0100
> >
> > drm/i915: Move golden context init into ->init_context
> >
> >
On Wed, Oct 07, 2015 at 04:26:03PM +0200, Daniel Vetter wrote:
> On Tue, Oct 06, 2015 at 09:26:31AM -0700, Matt Roper wrote:
> > intel_mode_from_pipe_config() fills in a mode structure from the CRTC
> > state that was read out of the hardware, but does not set the
> > .crtc_clock field (it only set
On Wed, Oct 07, 2015 at 04:28:48PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 07, 2015 at 11:17:46AM +0300, Jani Nikula wrote:
> > Signed-off-by: Jani Nikula
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 55
> > +
> > 1 file changed, 22 insertions(+), 33 de
On Wed, Oct 07, 2015 at 04:27:24PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 07, 2015 at 11:17:45AM +0300, Jani Nikula wrote:
> > Signed-off-by: Jani Nikula
> > ---
> > drivers/gpu/drm/i915/i915_gem_gtt.c | 7 ---
> > 1 file changed, 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i
On Tue, Oct 06, 2015 at 09:26:31AM -0700, Matt Roper wrote:
> intel_mode_from_pipe_config() fills in a mode structure from the CRTC
> state that was read out of the hardware, but does not set the
> .crtc_clock field (it only sets the .clock). This causes the subsequent
> call to drm_calc_timestamp
On Tue, Oct 06, 2015 at 05:26:48PM +0300, Mika Kuoppala wrote:
> From: Mika Kuoppala
>
> Rewrite everything in mmio workaround list right after
> gpu reset. This ensures that we start the reinitialization
> with proper mmio workarounds in place, before we
> start the rings.
>
> This commit just
On Wed, Oct 07, 2015 at 04:52:54PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 07, 2015 at 09:43:07AM +0100, Chris Wilson wrote:
> > On Tue, Oct 06, 2015 at 05:26:48PM +0300, Mika Kuoppala wrote:
> > > @@ -6973,8 +6989,12 @@ void intel_init_clock_gating(struct drm_device
> > > *dev)
> > > {
> > >
On Tue, Oct 06, 2015 at 07:28:10PM +0300, Ville Syrjälä wrote:
> On Tue, Oct 06, 2015 at 08:16:19AM -0700, Matt Roper wrote:
> > On Tue, Oct 06, 2015 at 05:42:42PM +0300, Ville Syrjälä wrote:
> > > On Tue, Oct 06, 2015 at 07:29:54AM -0700, Matt Roper wrote:
> > > > On Tue, Oct 06, 2015 at 02:32:47P
Hi,
On 07/10/15 03:35, Vivek Kasireddy wrote:
This new subtest will validate a Y-tiled object's tiling mode against
its associated fb modifier.
Cc: Tvrtko Ursulin
Signed-off-by: Vivek Kasireddy
---
tests/kms_addfb_basic.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/tests/
On Wed, Oct 07, 2015 at 04:35:51PM +0300, Imre Deak wrote:
> On ke, 2015-10-07 at 15:29 +0200, Daniel Vetter wrote:
> > On Tue, Oct 06, 2015 at 09:16:28PM +0300, Imre Deak wrote:
> > > On pe, 2015-09-18 at 23:39 +0530, Sagar Arun Kamble wrote:
> > > > From: Akash Goel
> > > >
> > > > Signed-off-b
On Tue, Oct 06, 2015 at 04:37:13PM +0100, Chris Wilson wrote:
> On Tue, Oct 06, 2015 at 03:19:36PM +0100, Tvrtko Ursulin wrote:
> >
> > On 06/10/15 11:39, Chris Wilson wrote:
> > >Passing cliprects into the kernel for it to re-execute the batch buffer
> > >with different CMD_DRAWRECT died out long
On Tue, Oct 06, 2015 at 05:31:30PM +, Vivi, Rodrigo wrote:
> On Tue, 2015-10-06 at 12:09 +0300, Jani Nikula wrote:
> > On Tue, 06 Oct 2015, Rodrigo Vivi wrote:
> > > From: Deepak S
> > >
> > > v2: separate out device info into different GT (Damien)
> > > v3: Add is_kabylake to the KBL gt3 st
On Wed, Oct 07, 2015 at 09:43:07AM +0100, Chris Wilson wrote:
> On Tue, Oct 06, 2015 at 05:26:48PM +0300, Mika Kuoppala wrote:
> > @@ -6973,8 +6989,12 @@ void intel_init_clock_gating(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> >
> > + intel_wa_
On Tue, Oct 06, 2015 at 02:18:34PM +0100, Chris Wilson wrote:
> On Tue, Oct 06, 2015 at 03:01:45PM +0200, Daniel Vetter wrote:
> > On Thu, Oct 01, 2015 at 12:18:29PM +0100, Chris Wilson wrote:
> > > Exclude active GPU pages from the purview of the background shrinker
> > > (kswapd), as these cause
On Tue, Oct 06, 2015 at 02:16:56PM +0100, Chris Wilson wrote:
> On Tue, Oct 06, 2015 at 02:54:25PM +0200, Daniel Vetter wrote:
> > On Thu, Oct 01, 2015 at 12:18:26PM +0100, Chris Wilson wrote:
> > > Often it is very useful to know why we suddenly purge vast tracts of
> > > memory and surprisingly u
On Wed, Oct 07, 2015 at 07:47:09AM +, Yang, Libin wrote:
> Hi all,
>
> Any comments? Thanks.
Was simply held up with some merge ordering troubles, I had to wait for
Takashi to apply the last patch so I could do a backmerge. And then I
forget about your patch series, thanks a lot for the remin
On ke, 2015-10-07 at 15:29 +0200, Daniel Vetter wrote:
> On Tue, Oct 06, 2015 at 09:16:28PM +0300, Imre Deak wrote:
> > On pe, 2015-09-18 at 23:39 +0530, Sagar Arun Kamble wrote:
> > > From: Akash Goel
> > >
> > > Signed-off-by: Ankitprasad Sharma
> > > Signed-off-by: Akash Goel
> > > Signed-of
On Fri, Sep 25, 2015 at 10:11 AM, Takashi Iwai wrote:
> On Fri, 25 Sep 2015 10:01:48 +0200,
> Jani Nikula wrote:
>>
>> On Fri, 25 Sep 2015, libin.y...@intel.com wrote:
>> > From: Libin Yang
>> >
>> > When modeset occurs and the TMDS frequency is set to some
>> > speical values, the N/CTS need to
Chris Wilson writes:
> On Wed, Oct 07, 2015 at 02:44:00PM +0300, Francisco Jerez wrote:
>> This programs the L3 configuration based on the sizes given for each
>> partition as arguments. The relevant register writes are added to the
>> workaround list so that they are re-applied to each context
On Wed, Oct 07, 2015 at 11:17:46AM +0300, Jani Nikula wrote:
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_pm.c | 55
> +
> 1 file changed, 22 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/
On Wed, Oct 07, 2015 at 11:17:45AM +0300, Jani Nikula wrote:
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 7 ---
> 1 file changed, 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 620d57e2526b..
On Tue, Oct 06, 2015 at 09:16:28PM +0300, Imre Deak wrote:
> On pe, 2015-09-18 at 23:39 +0530, Sagar Arun Kamble wrote:
> > From: Akash Goel
> >
> > Signed-off-by: Ankitprasad Sharma
> > Signed-off-by: Akash Goel
> > Signed-off-by: Sagar Arun Kamble
>
> The comment about units in gen6_set_rps
On Wed, Oct 07, 2015 at 11:17:44AM +0300, Jani Nikula wrote:
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_gem.c | 18 +-
> 1 file changed, 1 insertion(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index
On Fri, 2015-09-04 at 09:59 -0700, Jesse Barnes wrote:
> +
> + ret = handle_mm_fault(mm, vma, address,
> + desc.wr_req ? FAULT_FLAG_WRITE : 0);
> + if (ret & VM_FAULT_ERROR) {
> + gpu_mm_segv(tsk, address, SEGV_ACCERR); /* ? */
> +
On Wed, Oct 07, 2015 at 02:44:00PM +0300, Francisco Jerez wrote:
> This programs the L3 configuration based on the sizes given for each
> partition as arguments. The relevant register writes are added to the
> workaround list so that they are re-applied to each context while it's
> initialized, pr
On 07/10/15 13:10, Jindal, Sonika wrote:
On 10/7/2015 3:31 PM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Previously rotation was ignored and wrong stride programmed
into the plane registers resulting in a corrupt image on screen.
Signed-off-by: Tvrtko Ursulin
Cc: Sonika Jindal
---
dri
On 10/7/2015 3:31 PM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Previously rotation was ignored and wrong stride programmed
into the plane registers resulting in a corrupt image on screen.
Signed-off-by: Tvrtko Ursulin
Cc: Sonika Jindal
---
drivers/gpu/drm/i915/intel_display.c | 16
On Tue, Oct 06, 2015 at 05:02:47PM -0700, Matt Roper wrote:
> The legacy pageflip ioctl calls drm_crtc_check_viewport() to determine
> whether the framebuffer being flipped is big enough to fill the display
> it is being flipped to. However some drivers support "windowing" of
> their primary plane
On Tue, Oct 06, 2015 at 11:42:33AM -0400, Nick Bowler wrote:
> Hi,
>
> This issue is still present in 4.3-rc4.
>
> On 9/24/15, Nick Bowler wrote:
> > Testing out 4.3-rc2, first thing I notice is that the VGA output is
> > not working. Specifically, the display is continuously powering on
> > an
Use init_l3_partitioning_workarounds() to set up the L3 partitioning
on context creation according to the hardware boot-up defaults for
each device.
Signed-off-by: Francisco Jerez
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 53 +++--
1 file changed, 51 insertions(+)
This programs the L3 configuration based on the sizes given for each
partition as arguments. The relevant register writes are added to the
workaround list so that they are re-applied to each context while it's
initialized, preventing state leaks from other userspace processes
which may have modifi
This makes sure that the workaround is not accidentally undone by some
process (which is possible because the HSW_SCRATCH1 and
HSW_ROW_CHICKEN3 registers are partially whitelisted), what could
cause the next context to be created to hang if it wasn't expecting L3
atomics to be enabled.
Signed-off-
The same work-arond is applied per-context in
init_l3_partitioning_workarounds(), so the direct MMIO write of
GEN7_L3SQCREG1 should be redundant now. Applying the work-around at
context creation time also makes sure that the MMIO writes are not
accidentally undone by userspace.
Signed-off-by: Fra
intel_rcs_ctx_init() emits all workaround register writes on the list
to the ring, in addition to calling i915_gem_render_state_init(). The
workaround list is currently empty on Gen6-7 so this shouldn't cause
any functional changes.
Signed-off-by: Francisco Jerez
---
This is based on top of Dani
It's not an error for the workaround list to be empty if no
workarounds are needed. This will avoid spamming the logs
unnecessarily on Gen6 after the workaround list is hooked up on
pre-Gen8 hardware by the following commits.
Signed-off-by: Francisco Jerez
---
drivers/gpu/drm/i915/intel_ringbuf
From: Tvrtko Ursulin
Do some page flipping on the rotated plane just to exercise
that code path.
v2: Actually render to flip fb and fixed flip counter.
Signed-off-by: Tvrtko Ursulin
Cc: Sonika Jindal
Cc: Arun R Murthy
---
tests/kms_rotation_crc.c | 90 +++
Hi Tvrtko,
[auto build test ERROR on v4.3-rc4 -- if it's inappropriate base, please ignore]
config: x86_64-randconfig-x013-201540 (attached as .config)
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones prefixed by >>):
drivers/g
Hi
On Tue, Oct 6, 2015 at 1:19 PM, Chris Wilson wrote:
> On Tue, Oct 06, 2015 at 01:11:56PM +0200, Daniel Vetter wrote:
>> On Tue, Oct 06, 2015 at 11:53:09AM +0100, Chris Wilson wrote:
>> > In addition to the last-in/first-out stack for accessing drm_mm nodes,
>> > we occasionally and in the futu
From: Tvrtko Ursulin
Previously rotation was ignored and wrong stride programmed
into the plane registers resulting in a corrupt image on screen.
Signed-off-by: Tvrtko Ursulin
Cc: Sonika Jindal
---
drivers/gpu/drm/i915/intel_display.c | 16
1 file changed, 12 insertions(+), 4
On Tue, Oct 06, 2015 at 05:26:48PM +0300, Mika Kuoppala wrote:
> @@ -6973,8 +6989,12 @@ void intel_init_clock_gating(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> + intel_wa_init(&dev_priv->mmio_workarounds);
> +
> if (dev_priv->display.i
Hi Jani,
[auto build test WARNING on v4.3-rc4 -- if it's inappropriate base, please
ignore]
config: x86_64-randconfig-x006-201540 (attached as .config)
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All warnings (new ones prefixed by >>):
driver
On Tue, 06 Oct 2015, Ville Syrjälä wrote:
> On Tue, Oct 06, 2015 at 04:43:11PM +0300, Jani Nikula wrote:
>> On Tue, 06 Oct 2015, Ville Syrjälä wrote:
>> > On Tue, Oct 06, 2015 at 02:41:15PM +0300, Jani Nikula wrote:
>> >> Prefer inclusive ranges for revision checks rather than "below B0". Per
>>
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_gem.c | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 52642aff1dab..1e67484fd5dc 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 620d57e2526b..4e328f71a454 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/g
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_pm.c | 55 +
1 file changed, 22 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 60d120c472ab..598ee4c8d86e 100644
--- a/drivers/gp
On Tue, Oct 06, 2015 at 12:38:00PM -0700, Marc Herbert wrote:
> On 30/09/15 07:28, Imre Deak wrote:
> >On ke, 2015-08-26 at 16:58 +0530, Animesh Manna wrote:
> >>
> >>-void i915_firmware_load_error_print(const char *fw_path, int err)
> >>-{
> >>- DRM_ERROR("failed to load firmware %s (%d)\n", fw_
On Wed, 07 Oct 2015, Ben Widawsky wrote:
> On Tue, Oct 06, 2015 at 08:51:13PM +, Rodrigo Vivi wrote:
>> cc'ing Ben to get his opinion...
>>
>
> Of course anything is possible wrt the delta of KBL features vs SKL. With the
> knowledge we have, we can make a pretty educated guess that there wil
Hi all,
Any comments? Thanks.
Regards,
Libin
> -Original Message-
> From: Yang, Libin
> Sent: Thursday, October 01, 2015 5:01 PM
> To: intel-gfx@lists.freedesktop.org; daniel.vet...@ffwll.ch;
> jani.nik...@linux.intel.com; ville.syrj...@linux.intel.com
> Cc: Yang, Libin
> Subject: [PATCH
89 matches
Mail list logo
