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Task id: 6300
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Platform Delta drm-intel-nightly Series Applied
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From: chandra konduru
This patch adds necessary prep work for nv12 testcase:
- updated fb allocation functions to handle NV12 format
- igt helper function to return png image size
- igt helper function to calculate start of uv in a given NV12 buffer
- igt helper function to map buffer for
From: chandra konduru
This patch adds kms_nv12 test case. It covers testing NV12 in
all supported linear/tile-X/tile-Y/tile-Yf tile formats in
0 and 180 orientations. For each tiling format, it tests
various combinations of planes and scaling.
It has some very preliminary crc support and it is b
From: chandra konduru
This patch series adds necessary prep work for NV12 support to
igt lib and actual testcase to test NV12 feature. Refer to
individual patch header and comments in code for details.
chandra konduru (2):
i-g-t: Prep work for adding NV12 testcase
i-g-t: Adding display NV12
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
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Task id: 6299
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Platform Delta drm-intel-nightly Series Applied
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Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
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Task id: 6298
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Platform Delta drm-intel-nightly Series Applied
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I've now done some testing (on an i5-3230M, in Debian 8), and this patch
doesn't *appear* to break anything: both with and without it (starting
from linux-next 20150430 (fa94df1) + commit 245054a drm/i915: Enable cmd
parser to do secure batch promotion for aliasing ppgtt),
-libva (said in earl
On Friday, May 01, 2015 03:53:40 PM Chris Wilson wrote:
> Start trimming the fat from intel_batchbuffer.c. First by moving the set
> of routines for emitting PIPE_CONTROLS (along with the lore concerning
> hardware workarounds) to a separate brw_pipe_control.c
>
> Signed-off-by: Chris Wilson
> --
On 29/04/15 23:13, yu@intel.com wrote:
> From: Alex Dai
>
> Allocate a gem obj to hold GuC log data. Also a debugfs interface
> (i915_guc_log_dump) is provided to print out the log content.
>
> Issue: VIZ-4884
> Signed-off-by: Alex Dai
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 41 +
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
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Task id: 6297
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Platform Delta drm-intel-nightly Series Applied
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On Wed, Apr 29, 2015 at 03:12:58PM +0300, Jani Nikula wrote:
> On Mon, 27 Apr 2015, Chandra Konduru wrote:
> > This patch enables skylake primary plane scaling using shared
> > scalers atomic desgin.
> >
> > v2:
> > -use single copy of scaler limits (Matt)
> >
> > v3:
> > -move detach_scalers to c
On 27 April 2015 at 16:17, wrote:
> From: Tim Gore
>
> The call to low_mem_killer_disable(true) was being done
> from within function oom_adjust_for_doom. However,
> oom_adjust_for_doom gets called from 3 places. We only
> want the call to low_mem_killer_disable(true) to happen
> during common_i
On 28 April 2015 at 11:57, Tvrtko Ursulin
wrote:
> From: Tvrtko Ursulin
>
> I think;
>
>commit a26f9f9ad0e679c7ce413a25d34f6914e1174151
>Author: chandra konduru
>Date: Mon Mar 30 13:52:04 2015 -0700
>
>i-g-t: Adding plane scaling test case
>
> introduced a condition where i
On 30 April 2015 at 12:27, Tvrtko Ursulin
wrote:
> From: Tvrtko Ursulin
>
> As it stands running the test like "sudo tests/kms_plane_scaling"
> does not work.
>
> Fix it by using the same method igt_paint_image uses.
Adding a new function to igt_kms would avoid duplicating
stdio_read_func and ma
Start trimming the fat from intel_batchbuffer.c. First by moving the set
of routines for emitting PIPE_CONTROLS (along with the lore concerning
hardware workarounds) to a separate brw_pipe_control.c
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 +
src/mesa/d
With the exception of gen8, the sole user of the workaround bo are for
emitting pipe controls. More it out of the purview of the batchbuffer
and into the pipecontrol.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_context.c | 7 +
src/mesa/drivers/dri/i965/brw_context.h
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_clear.c | 4 ++--
src/mesa/drivers/dri/i965/brw_context.h | 6 +++---
src/mesa/drivers/dri/i965/brw_draw.c| 4 ++--
src/mesa/driver
Relocation processing is a significant overhead of heavy batches. The
kernel tries to make this as cheap as possible by avoiding as much work
as possible, but to be truly lazy requires userspace to construct its
batches and relocation trees in a convenient manner for processing.
Kristian made an a
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6296
-Summary-
Platform Delta drm-intel-nightly Series Applied
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Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6295
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
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