Re: [Intel-gfx] [PATCH v2] drm/i915/skl: Make sure to allocate mininum sizes in the DDB

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5732 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 282/283

[Intel-gfx] [PATCH 4/6] drm/i915: Add debugfs knobs for wbinvd threshold

Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_debugfs.c | 34 ++ 1 file changed, 34 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index b315f01..e0fd3ba 100644 --- a/drivers/gpu/drm/i915/i915_debu

[Intel-gfx] [PATCH 0/6] Prefer wbinvd() where appropriate

A while back we had a workload which severely suffered from excessive clflushing. I sent out a patch series which solved this generically in DRM core, but that had the unfortunate side effect of possibly regressing non-intel platforms. I've re-spun the series to only take this shortcut when on an

[Intel-gfx] [PATCH 2/6] drm/i915: Pass eb_vmas to execbuffer implementations

The role of eb_vmas continues to grow here as it becomes the proper encapsulation for the data passed to the various execution function. Next patch makes use of it... This patch was initially part of the next patch, but got split out after I had found a bug that convinced me the two should be sepa

[Intel-gfx] [PATCH 3/6] drm/i915: Opportunistically reduce flushing at execbuf

If we're moving a bunch of buffers from the CPU domain to the GPU domain, and we've already blown out the entire cache via a wbinvd, there is nothing more to do. With this and the previous patches, I am seeing a 3x FPS increase on a certain benchmark which uses a giant 2d array texture. Unless I m

[Intel-gfx] [PATCH 5/6] drm/i915: Extract checking the necessity of flush

Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem.c | 53 +++-- 1 file changed, 30 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 5bfb332..4d5a69d 100644 --- a/drivers/gpu/drm/i91

[Intel-gfx] [PATCH 6/6] drm/i915: obey wbinvd threshold in more places

Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_drv.h | 4 drivers/gpu/drm/i915/i915_gem.c | 32 drivers/gpu/drm/i915/i915_gem_gtt.c | 13 ++--- 3 files changed, 42 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i9

[Intel-gfx] [PATCH 1/6] drm/i915: Remove the useless flush_chipset

flush_chipset makes no sense with execlists because the former is for strictly prior to gen6, while the latter is for gen >= 8 Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/intel_lrc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b

Re: [Intel-gfx] [PATCH v2] drm/i915/bdw: Implement WaForceContextSaveRestoreNonCoherent

On Mon, Feb 09, 2015 at 07:25:56PM +, Damien Lespiau wrote: > v2: Reorder defines (Ben) Bikeshed time? > /* WaCatErrorRejectionIssue */ > #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > b/drivers/gpu/drm/i915/intel_ringbu

[Intel-gfx] [PATCH 18/18] drm/i915/skl: Implement WaBarrierPerformanceFixDisable

Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 090ddd7..b4abd50 100644 --- a/drivers/gpu/dr

[Intel-gfx] [PATCH 16/18] drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS

Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 7 ++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b363c5e..610fcd4 100644 --- a/drivers/gpu/d

[Intel-gfx] [PATCH 01/18] drm/i915: Support not having an init clock gating function defined

When enabling new platforms, we may not have any W/A to apply, especially that, now, a bunch of them have to be done from the ring. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_pm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_p

[Intel-gfx] [PATCH 09/18] drm/i915/skl: Implement WaEnableLbsSlaRetryTimerDecrement

This W/A is put in a gen9 specific function because it may well be needed on other gen9 platforms. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 11 +++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/i9

[Intel-gfx] [PATCH 07/18] drm/i915/skl: Implement WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken

Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_reg.h | 4 drivers/gpu/drm/i915/intel_ringbuffer.c | 8 2 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 578fd90..cb66c8f 100644 --- a/drivers/g

[Intel-gfx] [PATCH 02/18] drm/i915/skl: Implement WaDisableHBR2

Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_dp.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index d4c82d7..4a60c6a 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i91

[Intel-gfx] [PATCH 10/18] drm/i915/skl: Implement WaDisableVFUnitClockGating

Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 4 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2043e82..a457c28 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +

[Intel-gfx] [PATCH 15/18] drm/i915/skl: Implement WaDisableHDCInvalidation

Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 6 ++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3ae7a09..b363c5e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 14/18] drm/i915/skl: Implement WaDisableLSQCROPERFforOCL

Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 5 + 3 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c0b8644..0765bd1 1006

[Intel-gfx] [PATCH 13/18] drm/i915/skl: Implement WaDisablePartialResolveInVc

Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fdfbdb3..d519ed9 100644 --- a/drivers/gpu/drm/i9

[Intel-gfx] [PATCH 17/18] drm/i915/skl: Implement WaCcsTlbPrefetchDisable:skl

Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 4 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 610fcd4..090ddd7 100644 --- a/drivers/gpu/drm/i

[Intel-gfx] [PATCH 11/18] drm/i915/skl: Introduce a SKL specific init_workarounds()

This function will host SKL-only W/As. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_ringbuffer.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index b15d596..27d10

[Intel-gfx] [PATCH 08/18] drm/i915/skl: Document that we implement WaRsClearFWBitsAtReset

Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_uncore.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index c47a3ba..ad71575 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/i

[Intel-gfx] [PATCH 06/18] drm/i915/skl: Implement WaSetGAPSunitClckGateDisable

Let's also take the opportunity the remove the comment telling it's a pre-prod W/A, it should be obvious from the stepping test. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff

[Intel-gfx] [PATCH 03/18] drm/i915/skl: Document the WM read latency W/A with its name

Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_pm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a3b979d..6fd6f26 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1

[Intel-gfx] [PATCH 12/18] drm/i915/skl: Implement WaDisablePowerCompilerClockGating

Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_reg.h | 5 +++-- drivers/gpu/drm/i915/intel_ringbuffer.c | 8 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a457c28..fdfbdb3 10064

[Intel-gfx] [PATCH 04/18] drm/i915/skl: Provide a gen9 specific init_render_ring()

WaDisableAsyncFlipPerfMode isn't listed for SKL and INSTPM_FORCE_ORDERING is MBZ so let's make a gen9 specific render init function. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_lrc.c | 16 +++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu

[Intel-gfx] [PATCH 00/18] A few more workarounds

Following Nick's work, I found a few more. -- Damien Damien Lespiau (18): drm/i915: Support not having an init clock gating function defined drm/i915/skl: Implement WaDisableHBR2 drm/i915/skl: Document the WM read latency W/A with its name drm/i915/skl: Provide a gen9 specific init_rende

[Intel-gfx] [PATCH 05/18] drm/i915/skl: Make the init clock gating function skylake specific

We'll gather cross-gen9 W/A in a separate function later. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 6fd6f26..03e27c2 100644 ---

[Intel-gfx] [PATCH v2] drm/i915/bdw: Implement WaForceContextSaveRestoreNonCoherent

v2: Reorder defines (Ben) Reviewed-by: Ben Widawsky Reviewed-by: Ville Syrjälä Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_reg.h | 5 +++-- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i91

Re: [Intel-gfx] [PATCH 6/9] drm/i915: add frontbuffer tracking to FBC

On Mon, Feb 09, 2015 at 02:46:32PM -0200, Paulo Zanoni wrote: > From: Paulo Zanoni > > Kill the blt/render tracking we currently have and use the frontbuffer > tracking infrastructure. > > Don't enable things by default yet. > > v2: (Rodrigo) Fix small conflict on rebase and typo at subject. >

Re: [Intel-gfx] [PATCH 5/9] drm/i915: also do frontbuffer tracking on pwrites

On Mon, Feb 09, 2015 at 02:46:31PM -0200, Paulo Zanoni wrote: > From: Paulo Zanoni > > We need this for FBC, and possibly for PSR too. > > Reviewed-by: Rodrigo Vivi > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/i915_gem.c | 4 > 1 file changed, 4 insertions(+) > > diff --gi

Re: [Intel-gfx] [PATCH] drm/i915: Do not invalidate obj->pages under mempressure

On 02/09/2015 08:46 AM, Chris Wilson wrote: > On Sun, Feb 08, 2015 at 03:27:13PM -0800, Sean V Kelley wrote: >> >> >> On 01/16/2015 08:05 PM, Daniel Vetter wrote: >>> On Thu, Jan 15, 2015 at 08:44:00PM +, Chris Wilson wrote: On Thu, Jan 15, 2015 at 08:36:15PM +0100, Daniel Vetter

Re: [Intel-gfx] [PATCH 4/9] drm/i915: pass which operation triggered the frontbuffer tracking

On Mon, Feb 09, 2015 at 02:46:30PM -0200, Paulo Zanoni wrote: > From: Paulo Zanoni > > We want to port FBC to the frontbuffer tracking infrastructure, but > for that we need to know what caused the object invalidation/flush so > we can react accordingly: CPU mmaps need manual, GTT mmaps and > fli

Re: [Intel-gfx] [PATCH] drm/i915: Correct the base value while updating LP_OUTPUT_HOLD in MIPI_PORT_CTRL

On Thu, 05 Feb 2015, Shobhit Kumar wrote: > LP_OUTPUT_HOLD is only in MIPI_PORT_CTRL(PORT_A) even for PORT_C in case > of dual link. In the dual link implementation, the bit is correctly set > or unset for hardcoded PORT_A, but for bit update the register base value > is read by using MIPI_PORT_CT

Re: [Intel-gfx] [PATCH v2] drm/i915: Insert a command barrier on BLT/BSD cache flushes

On Mon, 09 Feb 2015, Chris Wilson wrote: > On Mon, Feb 09, 2015 at 06:00:25PM +0200, Jani Nikula wrote: >> On Thu, 22 Jan 2015, Chris Wilson wrote: >> > This looked like an odd regression from >> > >> > commit ec5cc0f9b019af95e4571a9fa162d94294c8d90b >> > Author: Chris Wilson >> > Date: Thu Ju

Re: [Intel-gfx] [PATCH 1/2] drm/i915: gen 9 h/w w/a Fix stepping check

On Fri, Feb 06, 2015 at 11:52:42AM +, Damien Lespiau wrote: > On Fri, Feb 06, 2015 at 11:30:03AM +, Nick Hoath wrote: > > Fixed the stepping check on WaDisableDgMirrorFixInHalfSliceChicken5 > > to be for the correct SOC (Skylake) > > > > Signed-off-by: Nick Hoath > > --- > > drivers/gpu/

Re: [Intel-gfx] [PATCH 03/10] drm/i915: gen 9 h/w w/a (WaDisablePartialInstShootdown)

On Fri, Feb 06, 2015 at 09:36:08AM +, Nick Hoath wrote: > On 06/02/2015 08:52, Daniel Vetter wrote: > >On Thu, Feb 05, 2015 at 05:51:46PM +, Damien Lespiau wrote: > >>On Thu, Feb 05, 2015 at 10:47:18AM +, Nick Hoath wrote: > >>>From: "Hoath, Nicholas" > >>> > >>>Add: > >>>WaDisablePart

[Intel-gfx] [PATCH 5/5] drm: Also check unused fields for addfb2

Just the usual paranoia ... Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_crtc.c | 17 + 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index b15d720eda4c..a12d7e8a0ca0 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/dr

[Intel-gfx] [PATCH 2/5] drm/i915: Add fb format modifier support

Currently we don't support anything but X tiled. And for an easier transition it makes a lot of sense to just keep requiring that X tiled is properly fenced. Which means we need to do absolutely nothing in old code to support fb modifiers, yay! Cc: Tvrtko Ursulin Signed-off-by: Daniel Vetter --

[Intel-gfx] [PATCH 4/5] drm/i915: Announce support for framebuffer modifiers

From: Tvrtko Ursulin Let the DRM core know we can handle it. v2: Change to boolean true. (Daniel Vetter) Signed-off-by: Tvrtko Ursulin Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_displa

[Intel-gfx] [PATCH 0/5] i915 fb modifier support, respun

Hi all, So this is the very quickly spun together version for my take on fb modifiers. Aim is to reduce the churn a bit with: - Only validate fb modifiers and old tiling_mode behaviour in framebuffer_init to ensure they are consistent. Don't convert over all the code for old platforms. - Guara

[Intel-gfx] [PATCH 1/5] drm/i915: Add tiled framebuffer modifiers

From: Tvrtko Ursulin To be used from the new addfb2 extension. v2: - Drop Intel-specific untiled modfier. - Move to drm_fourcc.h. - Document layouts a bit and denote them as platform-specific and not useable for cross-driver sharing. - Add Y-tiling for completeness. - Drop special docstring ma

[Intel-gfx] [PATCH 3/5] drm/i915: Use fb format modifiers in skylake_update_primary_plane

Just a little demo really. We probably need to introduce skl specific functions for a lot of the format validation stuff, or at least helpers. Specifically I think intel_framebuffer_init and intel_fb_align_height must be adjusted to have an i915_ and a skl_ variant. And only shared code should be c

Re: [Intel-gfx] Kernel 3.19rc6 flooding intel_check_page_flip warnings when using compton

On 05/02/15 11:01, Chris Wilson wrote: > On Thu, Feb 05, 2015 at 12:44:21PM +0200, Sakari Kapanen wrote: >> On 02/04/2015 11:26 AM, Jani Nikula wrote: >>> On Mon, 02 Feb 2015, Sakari Kapanen wrote: Dear maintainers, On an Asus Zenbook UX32VD laptop with an i5-3317U CPU and Intel HD4

Re: [Intel-gfx] [PATCH] drm/i915: Use symbolic irqreturn for ->hpd_pulse

On Mon, 09 Feb 2015, Daniel Vetter wrote: > On Fri, Feb 06, 2015 at 08:49:12PM +0200, Ville Syrjälä wrote: >> On Fri, Jan 23, 2015 at 06:00:31AM +0100, Daniel Vetter wrote: >> > Self-explanatory code is better code. >> >> This causes the VDD off -> HPD -> VDD on -> VDD off -> HPD ... cycle to >>

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Add tiled framebuffer modifiers

On Thu, Feb 05, 2015 at 02:41:53PM +, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > To be used from the new addfb2 extension. > > Signed-off-by: Tvrtko Ursulin > --- > include/uapi/drm/i915_drm.h | 15 +++ > 1 file changed, 15 insertions(+) > > diff --git a/include/uapi/drm

Re: [Intel-gfx] [PATCH] drm/i915: Drop vblank wait from intel_dp_link_down

On Mon, 09 Feb 2015, Jani Nikula wrote: > On Mon, 09 Feb 2015, Ville Syrjälä wrote: >> On Mon, Feb 09, 2015 at 03:15:56PM +0200, Jani Nikula wrote: >>> On Wed, 26 Nov 2014, Paulo Zanoni wrote: >>> > 2014-11-24 13:54 GMT-02:00 Daniel Vetter : >>> >> Nothing in Bspec seems to indicate that we actu

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Add tiled framebuffer modifiers

On Thu, Feb 05, 2015 at 02:41:53PM +, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > To be used from the new addfb2 extension. > > Signed-off-by: Tvrtko Ursulin > --- > include/uapi/drm/i915_drm.h | 15 +++ > 1 file changed, 15 insertions(+) > > diff --git a/include/uapi/drm

[Intel-gfx] [PATCH 2/9] drm/i915: don't keep reassigning FBC_UNSUPPORTED

From: Paulo Zanoni This may save a few picoseconds on !HAS_FBC platforms. And it also satisfies my OCD. Reviewed-by: Rodrigo Vivi Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_fbc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/inte

[Intel-gfx] [PATCH 4/9] drm/i915: pass which operation triggered the frontbuffer tracking

From: Paulo Zanoni We want to port FBC to the frontbuffer tracking infrastructure, but for that we need to know what caused the object invalidation/flush so we can react accordingly: CPU mmaps need manual, GTT mmaps and flips don't need handling and ring rendering needs nukes. v2: - s/ORIGIN_REN

[Intel-gfx] [PATCH 8/9] drm/i915: HSW+ FBC is tied to pipe A

From: Paulo Zanoni So add code to consider this case. Reviewed-by: Rodrigo Vivi Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_fbc.c | 20 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/in

[Intel-gfx] [PATCH 6/9] drm/i915: add frontbuffer tracking to FBC

From: Paulo Zanoni Kill the blt/render tracking we currently have and use the frontbuffer tracking infrastructure. Don't enable things by default yet. v2: (Rodrigo) Fix small conflict on rebase and typo at subject. v3: (Paulo) Rebase on RENDER_CS change. v4: (Paulo) Rebase. Reviewed-by: Rodrig

[Intel-gfx] [PATCH 5/9] drm/i915: also do frontbuffer tracking on pwrites

From: Paulo Zanoni We need this for FBC, and possibly for PSR too. Reviewed-by: Rodrigo Vivi Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_gem.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 3d198f8.

[Intel-gfx] [PATCH 9/9] drm/i915: gen5+ can have FBC with multiple pipes

From: Paulo Zanoni So allow it. Reviewed-by: Rodrigo Vivi Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_fbc.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 0d1c75d..6c84fb2 10064

[Intel-gfx] [PATCH 3/9] drm/i915: change dev_priv->fbc.plane to dev_priv->fbc.crtc

From: Paulo Zanoni Since the mapping from CRTCs to planes is fixed, looking at the CRTC is essentially the same as looking at the plane. Also, the next patches wil start using the frontbuffer_bits macros, and they take the pipe as the parameter instead of the plane, and this could differ on gens

[Intel-gfx] [PATCH 1/9] drm/i915: don't try to find crtcs for FBC if it's disabled

From: Paulo Zanoni .. because it would be a waste of time, so move the place where the check is done. Also, with this we won't risk printing "more than one pipe active, disabling compression" or "no output, disabling" when FBC is actually disabled. This patch also represents a small behavior dif

[Intel-gfx] [PATCH 7/9] drm/i915: extract intel_fbc_find_crtc()

From: Paulo Zanoni I want to make this code a little more complicated, so let's extract the function first. Reviewed-by: Rodrigo Vivi Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_fbc.c | 46 +--- 1 file changed, 29 insertions(+), 17 deletions(

Re: [Intel-gfx] [PATCH] drm/i915: Use symbolic irqreturn for ->hpd_pulse

On Fri, Feb 06, 2015 at 08:49:12PM +0200, Ville Syrjälä wrote: > On Fri, Jan 23, 2015 at 06:00:31AM +0100, Daniel Vetter wrote: > > Self-explanatory code is better code. > > This causes the VDD off -> HPD -> VDD on -> VDD off -> HPD ... cycle to > make another appearance on my BSW. Looks like you

[Intel-gfx] [RESEND 0/9] Reviewed FBC patches

From: Paulo Zanoni As requested by Daniel, here is the series with the FBC patches that were already reviewed. Some of them were rebased after the review, but the changes are minor. Paulo Zanoni (9): drm/i915: don't try to find crtcs for FBC if it's disabled drm/i915: don't keep reassigning

Re: [Intel-gfx] [PATCH] drm/i915: Do not invalidate obj->pages under mempressure

On Sun, Feb 08, 2015 at 03:27:13PM -0800, Sean V Kelley wrote: > > > On 01/16/2015 08:05 PM, Daniel Vetter wrote: > > On Thu, Jan 15, 2015 at 08:44:00PM +, Chris Wilson wrote: > >> On Thu, Jan 15, 2015 at 08:36:15PM +0100, Daniel Vetter wrote: > >>> On Wed, Jan 14, 2015 at 9:34 PM, Chris Wils

[Intel-gfx] [PATCH] drm/i915: Do not invalidate obj->pages under mempressure

From: Chris Wilson This (partially) reverts commit 5537252b6b6d71fb1a8ed7395a8e5babf91953fd Author: Chris Wilson Date: Tue Mar 25 13:23:06 2014 + drm/i915: Invalidate our pages under memory pressure It appears given the right workload, that pages which are swapped out more than once

Re: [Intel-gfx] [PATCH v4 04/24] drm/i915/gen8: Un-hardcode number of page directories

On Mon, Feb 09, 2015 at 05:30:45PM +0200, Mika Kuoppala wrote: > Michel Thierry writes: > > > From: Ben Widawsky > > > > Signed-off-by: Ben Widawsky > > Signed-off-by: Michel Thierry > > Reviewed-by: Mika Kuoppala Merged up to this one, thanks for patches&review. -Daniel > > > --- > > dr

Re: [Intel-gfx] [PATCH v2] drm/i915: Insert a command barrier on BLT/BSD cache flushes

On Mon, Feb 09, 2015 at 06:00:25PM +0200, Jani Nikula wrote: > On Thu, 22 Jan 2015, Chris Wilson wrote: > > This looked like an odd regression from > > > > commit ec5cc0f9b019af95e4571a9fa162d94294c8d90b > > Author: Chris Wilson > > Date: Thu Jun 12 10:28:55 2014 +0100 > > > > drm/i915: Res

Re: [Intel-gfx] [PATCH v2] drm/i915: Insert a command barrier on BLT/BSD cache flushes

On Thu, 22 Jan 2015, Chris Wilson wrote: > This looked like an odd regression from > > commit ec5cc0f9b019af95e4571a9fa162d94294c8d90b > Author: Chris Wilson > Date: Thu Jun 12 10:28:55 2014 +0100 > > drm/i915: Restrict GPU boost to the RCS engine > > but in reality it undercovered a much o

Re: [Intel-gfx] [PATCH v4 04/24] drm/i915/gen8: Un-hardcode number of page directories

Michel Thierry writes: > From: Ben Widawsky > > Signed-off-by: Ben Widawsky > Signed-off-by: Michel Thierry Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h >

Re: [Intel-gfx] [PATCH v4 03/24] drm/i915: Setup less PPGTT on failed page_directory

Michel Thierry writes: > From: Ben Widawsky > > The current code will both potentially print a WARN, and setup part of > the PPGTT structure. Neither of these harm the current code, it is > simply for clarity, and to perhaps prevent later bugs, or weird > debug messages. > > Signed-off-by: Ben W

[Intel-gfx] About CTX_CONTEXT_CONTROL initialization in populate_lr_context() intel_lrc.c

Hi Gurus: Forgive my junior HW knowledge, I just found that in execlist context initialization function populate_lr_context(), this line: reg_state[CTX_CONTEXT_CONTROL+1] = _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT); It seems the "Inhibit Synchronou

Re: [Intel-gfx] [PATCH] drm/i915: Correct the base value while updating LP_OUTPUT_HOLD in MIPI_PORT_CTRL

On Mon, 09 Feb 2015, Shobhit Kumar wrote: > On 02/06/2015 01:11 AM, shuang...@intel.com wrote: >> Tested-By: PRC QA PRTS (Patch Regression Test System Contact: >> shuang...@intel.com) >> Task id: 5718 >> -Summary- >> Platform

Re: [Intel-gfx] [PATCH v2] drm/i915/skl: Make sure to allocate mininum sizes in the DDB

On Mon, Feb 09, 2015 at 03:56:20PM +0200, Ville Syrjälä wrote: > > @@ -2544,8 +2557,9 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc, > > * promote the expression to 64 bits to avoid overflowing, the > > * result is < available as data_rate / total_data_rate < 1 > >

Re: [Intel-gfx] [PATCH v2] drm/i915/skl: Make sure to allocate mininum sizes in the DDB

On Mon, Feb 09, 2015 at 01:35:10PM +, Damien Lespiau wrote: > I overlooked the fact that we need to allocate a minimum 8 blocks and > that just allocating the planes depending on how much they need to fetch > from the DDB in proportion of how much memory bw is necessary for the > whole display

Re: [Intel-gfx] [PATCH] drm/i915: Drop vblank wait from intel_dp_link_down

On Mon, 09 Feb 2015, Ville Syrjälä wrote: > On Mon, Feb 09, 2015 at 03:15:56PM +0200, Jani Nikula wrote: >> On Wed, 26 Nov 2014, Paulo Zanoni wrote: >> > 2014-11-24 13:54 GMT-02:00 Daniel Vetter : >> >> Nothing in Bspec seems to indicate that we actually needs this, and it >> >> looks like can't

Re: [Intel-gfx] [PATCH] drm/i915: Drop vblank wait from intel_dp_link_down

On Mon, Feb 09, 2015 at 03:15:56PM +0200, Jani Nikula wrote: > On Wed, 26 Nov 2014, Paulo Zanoni wrote: > > 2014-11-24 13:54 GMT-02:00 Daniel Vetter : > >> Nothing in Bspec seems to indicate that we actually needs this, and it > >> looks like can't work since by this point the pipe is off and so >

[Intel-gfx] [PATCH v2] drm/i915/skl: Make sure to allocate mininum sizes in the DDB

I overlooked the fact that we need to allocate a minimum 8 blocks and that just allocating the planes depending on how much they need to fetch from the DDB in proportion of how much memory bw is necessary for the whole display can lead to cases where we don't respect those minima (and thus overrun)

Re: [Intel-gfx] [PATCH] drm/i915/skl: Add check for minimum allocable Display Data Blocks

On Mon, Feb 09, 2015 at 03:06:09PM +0530, Kumar, Mahesh wrote: > Fifo Underrun is observed when allocating < minimum allocable blocks > for any plane, This patch calculate & checks for upper & lower DDB > bound for each plane according to total allocated DDB for that Pipe. > > Signed-off-by: Kumar

Re: [Intel-gfx] [PATCH] drm/i915: Drop vblank wait from intel_dp_link_down

On Wed, 26 Nov 2014, Paulo Zanoni wrote: > 2014-11-24 13:54 GMT-02:00 Daniel Vetter : >> Nothing in Bspec seems to indicate that we actually needs this, and it >> looks like can't work since by this point the pipe is off and so >> vblanks won't really happen any more. >> >> Note that Bspec mention

Re: [Intel-gfx] [PATCH] drm/i915: Squelch overzealous uncore reset WARN_ON

On Thu, 05 Feb 2015, Chris Wilson wrote: > On Thu, Feb 05, 2015 at 05:45:42PM +0200, Mika Kuoppala wrote: >> We added this WARN_ON to guard against using uninitialized >> forcewake domains. But forgot blissfully that not all >> gens have forcewake domains in the first place. >> >> v2: Move WARN_O

Re: [Intel-gfx] [PATCH] drm/i915: Take runtime pm reference on hangcheck_info

On Thu, 05 Feb 2015, Chris Wilson wrote: > On Thu, Feb 05, 2015 at 06:41:48PM +0200, Mika Kuoppala wrote: >> We read the coherent current seqno and actual head from ring. >> For hardware access we need to take runtime_pm reference. >> >> Get hardware specific values with runtime reference held >>

Re: [Intel-gfx] [PATCH] drm/i915: Correct the IOSF Dev_FN field for IOSF transfers

On Mon, 09 Feb 2015, Shobhit Kumar wrote: > On 02/05/2015 10:44 PM, Ville Syrjälä wrote: >> On Thu, Feb 05, 2015 at 05:10:56PM +0530, Shobhit Kumar wrote: >>> As per the specififcation, the SB_DevFn is the PCI_DEVFN of the target >>> device and not the source. So PCI_DEVFN(2,0) is not correct. Fur

Re: [Intel-gfx] [PATCH 4/7] drm/i915/skl: Updated the gen6_rps_limits function

On Mon, 2015-02-09 at 11:03 +, Chris Wilson wrote: > On Mon, Feb 09, 2015 at 10:26:33AM +0530, Akash Goel wrote: > > On Fri, 2015-02-06 at 15:43 +, Chris Wilson wrote: > > > On Fri, Feb 06, 2015 at 08:26:35PM +0530, akash.g...@intel.com wrote: > > > > From: Akash Goel > > > > > > > > RP I

Re: [Intel-gfx] [PATCH] drm/i915: Correct the IOSF Dev_FN field for IOSF transfers

On 02/05/2015 10:44 PM, Ville Syrjälä wrote: > On Thu, Feb 05, 2015 at 05:10:56PM +0530, Shobhit Kumar wrote: >> As per the specififcation, the SB_DevFn is the PCI_DEVFN of the target >> device and not the source. So PCI_DEVFN(2,0) is not correct. Further the >> port ID should be enough to identify

Re: [Intel-gfx] [PATCH] drm/i915: Correct the base value while updating LP_OUTPUT_HOLD in MIPI_PORT_CTRL

On 02/06/2015 01:11 AM, shuang...@intel.com wrote: > Tested-By: PRC QA PRTS (Patch Regression Test System Contact: > shuang...@intel.com) > Task id: 5718 > -Summary- > Platform Delta drm-intel-nightly

Re: [Intel-gfx] [PATCH 4/7] drm/i915/skl: Updated the gen6_rps_limits function

On Mon, Feb 09, 2015 at 10:26:33AM +0530, Akash Goel wrote: > On Fri, 2015-02-06 at 15:43 +, Chris Wilson wrote: > > On Fri, Feb 06, 2015 at 08:26:35PM +0530, akash.g...@intel.com wrote: > > > From: Akash Goel > > > > > > RP Interrupt Up/Down Frequency Limits register (A014) definition > > >

[Intel-gfx] [PATCH] drm/i915/skl: Add check for minimum allocable Display Data Blocks

Fifo Underrun is observed when allocating < minimum allocable blocks for any plane, This patch calculate & checks for upper & lower DDB bound for each plane according to total allocated DDB for that Pipe. Signed-off-by: Kumar, Mahesh --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i

Re: [Intel-gfx] PCH fifo underrun in 3.18

On Fri, 30 Jan 2015, jon wrote: > Just updated my thinkpad (x230, ivy bridge platform) to 3.18 and boot > fails with the error 'PCH fifo underrun'. This is under fedora 21 with > the fedora kernel version 3.18.3-201 Please file a bug on [1], attach a dmesg from boot to the problem with drm.debu

[Intel-gfx] [PATCH] drm/i915: Remove references to previously removed UMS config option

Commit 03dae59c72d8 ("drm/i915: Ditch UMS config option") removed CONFIG_DRM_I915_UMS from the Kconfig file, but i915_drv.c still references this option in two #ifndef statements. As an undefined config option will always be 'false', we can drop the #ifndefs alltogether and adapt the printed e