[Intel-gfx] [PATCH 1/5] drm/i915: Add IS_BDW_GT3 macro.

It will be usefull to specify w/a that affects only BDW GT3. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5fce16c..a00214e 100644 --- a/drivers/gpu/drm

[Intel-gfx] [PATCH 5/5] drm/i915/bdw: Remove BDW preproduction W/As until C stepping.

Let's clean this a bit Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_pm.c | 10 -- drivers/gpu/drm/i915/intel_ringbuffer.c | 20 2 files changed, 4 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i91

[Intel-gfx] [PATCH 3/5] drm/i915/bdw: WaProgramL3SqcReg1Default

Program the default initial value of the L3SqcReg1 on BDW for performance Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_r

[Intel-gfx] [PATCH 4/5] drm/i915: Let number of workarounds more clear

This helps when including or removing cs workarounds. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_ringbuffer.c | 16 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c i

[Intel-gfx] [PATCH 2/5] drm/i915/bdw: WaDisableFenceDestinationToSLM

This WA affect BDW GT3 E and F steppings. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_r

Re: [Intel-gfx] [PATCH 1/8] drm/i915: Introduce a PV INFO page structure for Intel GVT-g.

> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of > Daniel Vetter > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > > index b65bdfc..a70f12e 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg

Re: [Intel-gfx] [PATCH 5/5] drm/i915: remove intel_pipe_set_base()

2014-09-19 Ville Syrjälä : > On Thu, Sep 18, 2014 at 04:43:16PM -0300, Gustavo Padovan wrote: > > From: Gustavo Padovan > > > > After some refactor intel_primary_plane_setplane() does the same > > as intel_pipe_set_base() so we can get rid of it and replace the calls > > with intel_primary_plane

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Suppress redundant syncs with mmio page flips

On Fri, Sep 19, 2014 at 08:58:58PM +0300, Ville Syrjälä wrote: > On Wed, Jun 18, 2014 at 12:23:14PM +0100, Chris Wilson wrote: > > Since mmio-flips do not occur on the suggested ring, we are introducing > > an extra sync operation where none is required. Pass the current > > obj->ring, which is wha

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Adds graphic address space ballooning logic

On Fri, Sep 19, 2014 at 06:21:46PM +, Tian, Kevin wrote: > > From: Chris Wilson > > The implementation also looks backwards. To work correctly with the GTT > > allocator, you need to preallocate the reserved space such that it can > > only allocate from the allowed ranges. Similarly, it should

Re: [Intel-gfx] [PATCH 2/2] drm/i915: add SW tracking to FBC enabling

Reviewed-by: Rodrigo Vivi But I think it would be good now to change fbc_status interface on debugfs to show the current bit state as well. On Fri, Sep 19, 2014 at 12:04 PM, Paulo Zanoni wrote: > From: Paulo Zanoni > > Currently, calling intel_fbc_enabled() will trigger a register read. > An

Re: [Intel-gfx] [PATCH 1/2] drm/i915: extract intel_init_fbc()

Reviewed-by: Rodrigo Vivi On Fri, Sep 19, 2014 at 12:04 PM, Paulo Zanoni wrote: > From: Paulo Zanoni > > Because I plan to expand it a little bit. > > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_pm.c | 50 > +++-- > 1 file changed, 28 in

[Intel-gfx] [PATCH 2/2] drm/i915: add SW tracking to FBC enabling

From: Paulo Zanoni Currently, calling intel_fbc_enabled() will trigger a register read. And we call it a lot of times, even when FBC is disabled, so saving a few cycles would be a good thing. Another reason for this patch is because we currently call intel_fbc_enabled() while the HW is runtime s

[Intel-gfx] [PATCH 1/2] drm/i915: extract intel_init_fbc()

From: Paulo Zanoni Because I plan to expand it a little bit. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c | 50 +++-- 1 file changed, 28 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/in

Re: [Intel-gfx] [PATCH] drm/i915: Avoid reading fbc registers in vain when fbc was never enabled.

2014-09-19 15:24 GMT-03:00 Rodrigo Vivi : > > > On Fri, Sep 19, 2014 at 8:40 AM, Daniel Vetter wrote: >> >> On Thu, Sep 18, 2014 at 11:42:44AM -0700, Rodrigo Vivi wrote: >> > On Thu, Sep 18, 2014 at 4:39 AM, Daniel Vetter wrote: >> > >> > > On Thu, Sep 18, 2014 at 07:28:48AM +0100, Chris Wilson w

Re: [Intel-gfx] [PATCH] drm/i915: Avoid reading fbc registers in vain when fbc was never enabled.

On Fri, Sep 19, 2014 at 8:40 AM, Daniel Vetter wrote: > On Thu, Sep 18, 2014 at 11:42:44AM -0700, Rodrigo Vivi wrote: > > On Thu, Sep 18, 2014 at 4:39 AM, Daniel Vetter wrote: > > > > > On Thu, Sep 18, 2014 at 07:28:48AM +0100, Chris Wilson wrote: > > > > On Wed, Sep 17, 2014 at 04:59:20PM -0400

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Adds graphic address space ballooning logic

> From: Chris Wilson > Sent: Friday, September 19, 2014 1:06 AM > > On Sat, Sep 20, 2014 at 02:47:02AM +0800, Jike Song wrote: > > From: Yu Zhang > > > > In XenGT, the global graphic memory space is partitioned by multiple > > vgpu instances in different VMs. The ballooning code is added in > > i

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Suppress redundant syncs with mmio page flips

On Wed, Jun 18, 2014 at 12:23:14PM +0100, Chris Wilson wrote: > Since mmio-flips do not occur on the suggested ring, we are introducing > an extra sync operation where none is required. Pass the current > obj->ring, which is what mmio flip will use, to pin_to_display_plane so > that we emit the app

Re: [Intel-gfx] [PATCH] drm/i915/bdw: Cleanup pre prod workarounds

On Fri, Sep 19, 2014 at 08:05:26PM +0300, Mika Kuoppala wrote: > as these have been fixed in production hw and hurt performance > if applied. > > v2: adjust requested ring space (Ville) > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83482 > Tested-by: zhoujian > Signed-off-by: Mika K

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Reinitialize default context after reset

[snip] On Thu, Sep 18, 2014 at 07:58:30AM -0700, Mika Kuoppala wrote: > @@ -577,7 +596,7 @@ static int do_switch(struct intel_engine_cs *ring, > vma->bind_vma(vma, to->legacy_hw_ctx.rcs_state->cache_level, > GLOBAL_BIND); > } > > - if (!to->legacy_hw_ctx.initialized || i

[Intel-gfx] [PATCH] drm/i915: DocBook integration for frontbuffer tracking

I shouldn't ask everyone to do this and fail myself ... This extracts all the frontbuffer tracking functions into intel_frontbuffer.c, adds a DOC overview section and also adds the missing kerneldoc for i915_gem_track_fb and also pulls it into the same section for convenience. v2: Don't forget ab

[Intel-gfx] [PATCH] drm/i915/bdw: Cleanup pre prod workarounds

as these have been fixed in production hw and hurt performance if applied. v2: adjust requested ring space (Ville) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83482 Tested-by: zhoujian Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_ringbuffer.c | 15 ++- 1 f

[Intel-gfx] [PATCH] drm/i915: DocBook integration for frontbuffer tracking

I shouldn't ask everyone to do this and fail myself ... This extracts all the frontbuffer tracking functions into intel_frontbuffer.c, adds a DOC overview section and also adds the missing kerneldoc for i915_gem_track_fb and also pulls it into the same section for convenience. v2: Don't forget ab

[Intel-gfx] [PATCH] drm/i915: DocBook integration for frontbuffer tracking

I shouldn't ask everyone to do this and fail myself ... This extracts all the frontbuffer tracking functions into intel_frontbuffer.c, adds a DOC overview section and also adds the missing kerneldoc for i915_gem_track_fb and also pulls it into the same section for convenience. v2: Don't forget ab

[Intel-gfx] [PATCH] drm/i915: DocBook integration for frontbuffer tracking

I shouldn't ask everyone to do this and fail myself ... This extracts all the frontbuffer tracking functions into intel_frontbuffer.c, adds a DOC overview section and also adds the missing kerneldoc for i915_gem_track_fb and also pulls it into the same section for convenience. v2: Don't forget ab

Re: [Intel-gfx] [PATCH] drm/i915: Minimize the huge amount of unecessary fbc sw cache clean.

2014-09-18 12:29 GMT-03:00 Rodrigo Vivi : > The sw cache clean on BDW is a tempoorary workaround because we cannot > set cache clean on blt ring with risk of hungs. So we are doing the cache > clean on sw. > However we are doing much more than needed. Not only when using blt ring. > So, with this

Re: [Intel-gfx] [PATCH 5/8] drm/i915: Add the display switch logic for vgpu in i915 driver

On Sat, Sep 20, 2014 at 02:47:05AM +0800, Jike Song wrote: > From: Yu Zhang > > Display switch logic is added to notify the vgt mediator that > current vgpu have a valid surface to show. It does so by writing > the display_ready field in PV INFO page, and then will be handled > in vgt mediator. T

Re: [Intel-gfx] [PATCH 1/8] drm/i915: Introduce a PV INFO page structure for Intel GVT-g.

On Fri, Sep 19, 2014 at 06:02:46PM +0200, Daniel Vetter wrote: > I think a new header file i915_vgt.h for these definitions would be good. > i915_reg.h is giant already ... Separate header would also lend itself well for some kerneldoc DOC: overview section and for properly documenting all the vgt

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Adds graphic address space ballooning logic

On Fri, Sep 19, 2014 at 09:05:57AM +0100, Chris Wilson wrote: > On Sat, Sep 20, 2014 at 02:47:02AM +0800, Jike Song wrote: > > From: Yu Zhang > > If all entries may have prefetch issues, > > then this special guard page is necessary, to protect unexpected > > accesses into GTT entries partitioned

Re: [Intel-gfx] turn off lowmemorykiller when running IGT on Android?

> -Original Message- > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel > Vetter > Sent: Friday, September 19, 2014 4:52 PM > To: Gore, Tim > Cc: Daniel Vetter; intel-gfx@lists.freedesktop.org; Gardiner, Kelvin; Joncour, > Yann; Sharp, Robert; Daniel, Thomas > Subje

Re: [Intel-gfx] [PATCH 1/8] drm/i915: Introduce a PV INFO page structure for Intel GVT-g.

On Sat, Sep 20, 2014 at 02:47:01AM +0800, Jike Song wrote: > From: Yu Zhang > > Introduce a PV INFO structure, to facilitate the Intel GVT-g > technology, which is a GPU virtualization solution with mediated > pass-through(previously known as XenGT). This page contains the > shared information be

Re: [Intel-gfx] [PATCH] drm/i915: Inline feature detection into sanitize_enable_ppgtt

On Fri, Sep 19, 2014 at 11:56:27AM +0100, Chris Wilson wrote: > Rather than splitting and hiding away critical parts of > sanitize_enable_ppgtt() into single use macros in the headers, inline > them into the function for clarity. > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/i915_

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Re-enable the command parser when using PPGTT

On Thu, Sep 18, 2014 at 04:26:26PM -0700, bradley.d.vol...@intel.com wrote: > From: Brad Volkin > > In commit > > commit 896ab1a5d54269b463a24194c2e4a369103b46d8 > Author: Daniel Vetter > Date: Wed Aug 6 15:04:51 2014 +0200 > > drm/i915: Fix up checks for aliasing ppgtt > > it looks lik

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Log a message when rejecting LRM to OACONTROL

On Thu, Sep 18, 2014 at 04:26:27PM -0700, bradley.d.vol...@intel.com wrote: > From: Brad Volkin > > The other paths in the command parser that reject a batch all > log a message indicating the reason. We simply missed this one. > > Signed-off-by: Brad Volkin Both patches merged to dinq, thanks

Re: [Intel-gfx] [PATCH] intel: Adding locks for drm objects synchronization.

On 09/19/14 17:36, Daniel Vetter wrote: > Hm, I don't see what this fixes, except maybe a race in the kernel? > Testcase plus some analysis in the commit message about what blows up > exactly and how this fixes it is required here. Currently we can reproduce this issue using our "internal" project

Re: [Intel-gfx] turn off lowmemorykiller when running IGT on Android?

On Fri, Sep 19, 2014 at 08:21:49AM +, Gore, Tim wrote: > > > > -Original Message- > > From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of > > Daniel Vetter > > Sent: Thursday, September 18, 2014 7:57 PM > > To: Gore, Tim > > Cc: intel-gfx@lists.freedesktop.org; G

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Build workaround list in ring initialization

On Thu, Sep 18, 2014 at 05:58:33PM +0300, Mika Kuoppala wrote: > to disassociate workaround list init from the actual writing > of values. This is needed as not workarounds will be masked bit > enables and we want full control on when the read part of RMW > will happen. > > Signed-off-by: Mika Kuo

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Reinitialize default context after reset

On Thu, Sep 18, 2014 at 04:36:47PM +0100, Chris Wilson wrote: > On Thu, Sep 18, 2014 at 05:58:30PM +0300, Mika Kuoppala wrote: > > We don't know in what shape the default context was before reset. > > The reset also dropped our changes that were done in > > ring->init_context. > > > > Mark our def

Re: [Intel-gfx] [PATCH] drm/i915: Avoid reading fbc registers in vain when fbc was never enabled.

On Thu, Sep 18, 2014 at 11:42:44AM -0700, Rodrigo Vivi wrote: > On Thu, Sep 18, 2014 at 4:39 AM, Daniel Vetter wrote: > > > On Thu, Sep 18, 2014 at 07:28:48AM +0100, Chris Wilson wrote: > > > On Wed, Sep 17, 2014 at 04:59:20PM -0400, Rodrigo Vivi wrote: > > > > If it wasn't never enabled by kerne

Re: [Intel-gfx] [PATCH] intel: Adding locks for drm objects synchronization.

On Fri, Sep 19, 2014 at 03:45:27PM +0200, Jacek Danecki wrote: > On 09/18/14 14:43, Daniel Vetter wrote: > > I can't merge patches with this disclaimer ... > > We're working on this, sorry... We'll send it again. Yeah just dropped it ;-) > Btw, in another tests with prime we have also found new

Re: [Intel-gfx] [PATCH] drm/i915: Revert "drm/i915: Reject the pin ioctl on gen6+"

On Fri, Sep 19, 2014 at 03:25:55PM +0100, Damien Lespiau wrote: > Hi Daniel, > > On Mon, Jul 07, 2014 at 11:04:55PM +0200, Daniel Vetter wrote: > > On Thu, Jul 03, 2014 at 08:12:35AM +0100, Damien Lespiau wrote: > > > This reverts commit 02f6bcccf7c324115747aae2f0addd6af5d321cd. > > > > > > The O

[Intel-gfx] Updated drm-intel-testing

Hi all, New -testing cycle with cool stuff: - bunch more i830M fixes from Ville - full ppgtt now again enabled by default - more ppgtt fixes from Michel Thierry and Chris Wilson - plane config work from Gustavo Padovan - spinlock clarifications - piles of smaller improvements all over, as usual H

Re: [Intel-gfx] [PATCH] drm/i915: Revert "drm/i915: Reject the pin ioctl on gen6+"

Hi Daniel, On Mon, Jul 07, 2014 at 11:04:55PM +0200, Daniel Vetter wrote: > On Thu, Jul 03, 2014 at 08:12:35AM +0100, Damien Lespiau wrote: > > This reverts commit 02f6bcccf7c324115747aae2f0addd6af5d321cd. > > > > The OA buffer can contain global data (in particular, not linked to a > > context o

Re: [Intel-gfx] [PATCH] drm/i915/bdw: Cleanup pre prod workarounds

On Fri, Sep 19, 2014 at 04:05:08PM +0300, Mika Kuoppala wrote: > as these have been fixed in production hw and hurt performance > if applied. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83482 > Tested-by: zhoujian > Signed-off-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/intel_

Re: [Intel-gfx] [PATCH 5/5] drm/i915: remove intel_pipe_set_base()

On Thu, Sep 18, 2014 at 04:43:16PM -0300, Gustavo Padovan wrote: > From: Gustavo Padovan > > After some refactor intel_primary_plane_setplane() does the same > as intel_pipe_set_base() so we can get rid of it and replace the calls > with intel_primary_plane_setplane(). > > Signed-off-by: Gustavo

Re: [Intel-gfx] [PATCH 11/89 v2] drm/i915/skl: Framebuffers need to be aligned to 256KB on Skylake

On 19 September 2014 12:26, Damien Lespiau wrote: > v2: Also align X tiled fbs to 256KB (Thomas) > > Signed-off-by: Damien Lespiau Reviewed-by: Thomas Wood > --- > drivers/gpu/drm/i915/intel_display.c | 12 +--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/driver

Re: [Intel-gfx] [PATCH] intel: Adding locks for drm objects synchronization.

On 09/18/14 14:43, Daniel Vetter wrote: > I can't merge patches with this disclaimer ... We're working on this, sorry... We'll send it again. Btw, in another tests with prime we have also found new problem with synchronization, which below patch fixed. From: Rafal Sapala Date: Thu, 18 Sep 2014

Re: [Intel-gfx] [PATCH] intel: Don't leak the test page in an has_userptr() error path

On Fri, Sep 19, 2014 at 02:31:56PM +0100, Tvrtko Ursulin wrote: > > Reviewed-by: Tvrtko Ursulin > Thanks for the review, pushed the patch. -- Damien ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/list

Re: [Intel-gfx] [PATCH] intel: Don't leak the test page in an has_userptr() error path

Reviewed-by: Tvrtko Ursulin On 09/17/2014 01:37 PM, Damien Lespiau wrote: When handling the error on GEM_CLOSE, we weren't freeing the allocated page. Plug that. Signed-off-by: Damien Lespiau --- intel/intel_bufmgr_gem.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --g

[Intel-gfx] [PATCH] drm/i915/bdw: Cleanup pre prod workarounds

as these have been fixed in production hw and hurt performance if applied. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83482 Tested-by: zhoujian Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_ringbuffer.c | 13 + 1 file changed, 1 insertion(+), 12 deletions(-

Re: [Intel-gfx] [PATCH 2/5] drm/i915: move checks of intel_crtc_cursor_set_obj() out

On Thu, Sep 18, 2014 at 04:43:13PM -0300, Gustavo Padovan wrote: > From: Gustavo Padovan > > Move checks inside intel_crtc_cursor_set_obj() to > intel_check_cursor_plane(), we only use they there so move them out to > make the merge of intel_crtc_cursor_set_obj() into > intel_check_cursor_plane()

Re: [Intel-gfx] [PATCH 5/8] drm/i915: Add the display switch logic for vgpu in i915 driver

Hi Chris: Thanks for the comment. See my comments below. -Original Message- From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of Chris Wilson Sent: Friday, September 19, 2014 4:15 PM To: Song, Jike Cc: Vetter, Daniel; intel-gfx@lists.freedesktop.org Subject: R

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Merge of visible and !visible paths for primary planes

On Thu, Sep 18, 2014 at 04:43:12PM -0300, Gustavo Padovan wrote: > From: Gustavo Padovan > > Fold intel_pipe_set_base() in the update primary plane path merging > pieces of code that are common to both paths. > > Basically the the pin/unpin procedures are the same for both paths > and some check

[Intel-gfx] [PATCH 11/89 v2] drm/i915/skl: Framebuffers need to be aligned to 256KB on Skylake

v2: Also align X tiled fbs to 256KB (Thomas) Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_display.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index cf51704..a48a2f3

Re: [Intel-gfx] [PATCH 08/89] drm/i915/skl: Use gen8_ring_dispatch_execbuffer() on GEN9

On Tue, Sep 16, 2014 at 03:53:12PM +0100, Thomas Wood wrote: > On 4 September 2014 12:26, Damien Lespiau wrote: > > Signed-off-by: Damien Lespiau > > --- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i91

[Intel-gfx] [PATCH] drm/i915: Inline feature detection into sanitize_enable_ppgtt

Rather than splitting and hiding away critical parts of sanitize_enable_ppgtt() into single use macros in the headers, inline them into the function for clarity. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.h | 2 -- drivers/gpu/drm/i915/i915_gem_gtt.c | 14 +++---

Re: [Intel-gfx] [PATCH 79/89] drm/i915/skl: Read back the DDB allocation hw state

On Thu, Sep 04, 2014 at 12:27:45PM +0100, Damien Lespiau wrote: > This logically belongs to the WM state, so do it there. > > Signed-off-by: Damien Lespiau > --- > drivers/gpu/drm/i915/intel_pm.c | 29 + > 1 file changed, 29 insertions(+) > > diff --git a/drivers/gpu

Re: [Intel-gfx] [PATCH 80/89] drm/i915/skl: Augment the latency debugfs files for SKL

On Thu, Sep 04, 2014 at 12:27:46PM +0100, Damien Lespiau wrote: > Signed-off-by: Damien Lespiau > --- > drivers/gpu/drm/i915/i915_debugfs.c | 76 > ++--- > 1 file changed, 62 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c > b

Re: [Intel-gfx] [PATCH 78/89] drm/i915/skl: Flush the WM configuration

On Thu, Sep 04, 2014 at 12:27:44PM +0100, Damien Lespiau wrote: > When we write new values for the DDB allocation and WM parameters, we now > need to trigger the double buffer update for the pipe to take the new > configuration into account. > > As the DDB is a global resource shared between plane

Re: [Intel-gfx] [PATCH 1/8] drm/i915: Introduce a PV INFO page structure for Intel GVT-g.

Hi Chris, thanks very much for your detailed comments! I'll try to address them as well as in your other emails. On 09/19/2014 03:25 PM, Chris Wilson wrote: On Sat, Sep 20, 2014 at 02:47:01AM +0800, Jike Song wrote: From: Yu Zhang Introduce a PV INFO structure, to facilitate the Intel GVT-g t

Re: [Intel-gfx] [PATCH 52/89] drm/i915/gen9: Disable WM if corresponding latency is 0

On Thu, Sep 04, 2014 at 12:27:18PM +0100, Damien Lespiau wrote: > From: Vandana Kannan > > According to updated BSpec, If level 1 or any higher level has a value of > 0x00, > that level and any higher levels are unused and the associated watermark > registers must not be enabled. > > This patch

Re: [Intel-gfx] [PATCH 49/89] drm/i915/skl: Program the DDB allocation

On Thu, Sep 04, 2014 at 12:27:15PM +0100, Damien Lespiau wrote: > v2: Adapt to the planes/cursor split > > Signed-off-by: Damien Lespiau > --- > drivers/gpu/drm/i915/i915_reg.h | 16 > drivers/gpu/drm/i915/intel_pm.c | 9 + > 2 files changed, 25 insertions(+) > > diff

Re: [Intel-gfx] [PATCH 51/89] drm/i915/gen9: Add 2us read latency to WM level

On Thu, Sep 04, 2014 at 12:27:17PM +0100, Damien Lespiau wrote: > From: Vandana Kannan > > According to the updated Bspec, The mailbox response data is not currently > accounting for memory read latency. Add 2 microseconds to the result for > each level. > This patch adds 2us to latency of level

Re: [Intel-gfx] [PATCH 48/89] drm/i915/skl: Allocate DDB portions for display planes

On Thu, Sep 04, 2014 at 12:27:14PM +0100, Damien Lespiau wrote: > v2: Fix the 3rd plane/cursor logic (Pradeep Bhat) > v3: Fix one-by-one error in the DDB allocation code > > Signed-off-by: Damien Lespiau > --- > drivers/gpu/drm/i915/intel_pm.c | 150 > >

Re: [Intel-gfx] [QA 09/19 ww38] Testing report for `drm-intel-testing` (was: Updated -next)

One more new bug Bug 84083 - [BDW Regression]DP unable to light up after unplug/plug while X running Thanks --Sun, Yi From: Sun, Yi Sent: Friday, September 19, 2014 1:44 PM To: 'Daniel Vetter'; Jin, Gordon Cc: 'intel-gfx@lists.freedesktop.org

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Support alias ppgtt in VM if ppgtt is enabled

On Sat, Sep 20, 2014 at 02:47:08AM +0800, Jike Song wrote: > From: Yu Zhang > > The current XenGT only supports alias ppgtt. And the emulation > is done in XenGT host by first trapping PP_DIR_BASE mmio > accesses. Updating PP_DIR_BASE by using instructions such as > MI_LOAD_REGISTER_IMM are hard

Re: [Intel-gfx] turn off lowmemorykiller when running IGT on Android?

> -Original Message- > From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of > Daniel Vetter > Sent: Thursday, September 18, 2014 7:57 PM > To: Gore, Tim > Cc: intel-gfx@lists.freedesktop.org; Gardiner, Kelvin; Joncour, Yann; Sharp, > Robert; Daniel, Thomas > Subject:

Re: [Intel-gfx] [PATCH 6/8] drm/i915: Disable power management for i915 driver in VM

On Sat, Sep 20, 2014 at 02:47:06AM +0800, Jike Song wrote: > From: Yu Zhang > > In XenGT, GPU power management is controlled by host i915 > driver, so there is no need to provide virtualized GPU PM > support. In the future it might be useful to gather VM > input for freq boost, but now let's disa

Re: [Intel-gfx] [PATCH 5/8] drm/i915: Add the display switch logic for vgpu in i915 driver

On Sat, Sep 20, 2014 at 02:47:05AM +0800, Jike Song wrote: > From: Yu Zhang > > Display switch logic is added to notify the vgt mediator that > current vgpu have a valid surface to show. It does so by writing > the display_ready field in PV INFO page, and then will be handled > in vgt mediator. T

Re: [Intel-gfx] [PATCH 4/8] drm/i915: Disable framebuffer compression for i915 driver in VM

On Sat, Sep 20, 2014 at 02:47:04AM +0800, Jike Song wrote: > From: Yu Zhang > > Framebuffer compression is disabled when driver detects it's > running in XenGT VM, because XenGT does not provide emulations > for FBC related operations, and we do not expose stolen memory > to the VM. > > Signed-o

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Adds graphic address space ballooning logic

On Sat, Sep 20, 2014 at 02:47:02AM +0800, Jike Song wrote: > From: Yu Zhang > > In XenGT, the global graphic memory space is partitioned by multiple > vgpu instances in different VMs. The ballooning code is added in > i915_gem_setup_global_gtt(), utilizing the drm mm allocator APIs to > mark the

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Create vgpu specific write MMIO to reduce traps

[adding cc. By mistake I set suppresscc=all in my ~/.gitconfig] On 09/19/2014 02:59 PM, Chris Wilson wrote: On Sat, Sep 20, 2014 at 02:47:07AM +0800, Jike Song wrote: From: Yu Zhang In the virtualized environment, forcewake operations are not necessory for the driver, because mmio accesses wi

[Intel-gfx] [PATCH 1/2] tests: Add drm_import_export

Multithreaded test to validate the (lack of) locking in the flink/open code in libdrm-intel. Based on a testcase from Rafel Sapala. Cc: Rafal Sapala Signed-off-by: Daniel Vetter --- tests/.gitignore | 1 + tests/Makefile.am | 2 + tests/Makefile.sources| 1 + tests/dr

[Intel-gfx] [PATCH 2/2] tests/drm_import_export: Add subtest for prime

Cc: Rafal Sapala Signed-off-by: Daniel Vetter --- tests/drm_import_export.c | 90 --- 1 file changed, 62 insertions(+), 28 deletions(-) diff --git a/tests/drm_import_export.c b/tests/drm_import_export.c index 52387635db9c..83e753bf420c 100644 --- a/te

Re: [Intel-gfx] [PATCH 1/8] drm/i915: Introduce a PV INFO page structure for Intel GVT-g.

On Sat, Sep 20, 2014 at 02:47:01AM +0800, Jike Song wrote: > From: Yu Zhang > > Introduce a PV INFO structure, to facilitate the Intel GVT-g > technology, which is a GPU virtualization solution with mediated > pass-through(previously known as XenGT). This page contains the > shared information be

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Create vgpu specific write MMIO to reduce traps

On Sat, Sep 20, 2014 at 02:47:07AM +0800, Jike Song wrote: > From: Yu Zhang > > In the virtualized environment, forcewake operations are not > necessory for the driver, because mmio accesses will be trapped > and emulated by the host side, and real forcewake operations are > also done in the host