Re: [Intel-gfx] [PATCH] drm/i915/bdw: Initialize workarounds in render ring init fn.

On 08/14/2014 09:51 AM, arun.siluv...@linux.intel.com wrote: From: Arun Siluvery The workarounds at the moment are initialized in init_clock_gating() but they are lost during reset, suspend/resume; this patch moves workarounds that are part of register state context to render ring init fn oth

[Intel-gfx] [PATCH i-g-t 1/1] tests: Fix seg fault when gem_mmap is run without specifying a subtest

From: Mike Mason gem_mmap seg faults when all tests are run together. This occurs because the new-object subtest closes the gem object, but short-mmap assumes it still exists. Thus gem_mmap__cpu() returns nil for addr and memset() seg faults. This patch makes new-object and short-mmap create and

[Intel-gfx] [PATCH i-g-t 1/1] scripts: Allow multiple -t and -x regular expressions for run-tests.sh

Piglit allows multiple -t and -x regular expressions to be given on the command line. This patch enables run-tests.sh to support that as well. Signed-off-by: Mike Mason --- scripts/run-tests.sh | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/scripts/run-tests.sh b/scrip

[Intel-gfx] [PATCH i-g-t 1/1] Add kms_flip_event_leak to .gitignore

This patch just adds kms_flip_event_leak to tests/.gitignore. Signed-off-by: Mike Mason --- tests/.gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/.gitignore b/tests/.gitignore index d14d87b..3da061e 100644 --- a/tests/.gitignore +++ b/tests/.gitignore @@ -121,6 +121,7 @@ kms

[Intel-gfx] [PATCH] drm/i915: fix plane/cursor handling when runtime suspended

From: Paulo Zanoni If we're runtime suspended and try to use the plane interfaces, we will get a lot of WARNs saying we did the wrong thing. We need to get runtime PM references to pin the objects, and to change the fences. The pin functions are the ideal places for this, but intel_crtc_cursor_s

Re: [Intel-gfx] [PATCH] drm/i915: Use dev_priv as first argument of for_each_pipe()

On Fri, Aug 15, 2014 at 06:34:06PM +0100, Damien Lespiau wrote: > -#define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; > (p)++) > +#define for_each_pipe(dev, p) for ((p) = 0; (p) < (dev)->info.num_pipes; > (p)++) > #define for_each_sprite(p, s) for ((s) = 0; (s) < > INTEL_I

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Suppress a WARN on reading an object back for a GPU hang

Chris Wilson writes: > Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/i915_gpu_error.c | 5 - > 1

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Remove num_pages parameter to i915_error_object_create()

Chris Wilson writes: > For cleanliness, i915_error_object_create() was written to handle the > NULL pointer in a central location. The macro that wrapped it and passed > it a num_pages to use, was not safe. As we now never limit the num_pages > to use (we did so at one point to only capture the f

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Do not access stolen memory directly by the CPU, even for error capture

Mika Kuoppala writes: > Chris Wilson writes: > >> For stolen pages, since it is verboten to access them directly on many >> architectures, we have to read them through the GTT aperture. If they >> are not accessible through the aperture, then we have to abort. >> >> This was complicated by >> >>

[Intel-gfx] [PULL] topic/core-stuff for 3.18

Hi Dave, So small drm stuff all over for 3.18. Biggest one is the cmdline parsing from Chris with a few fixes from me to make it work for stupid kernel configs. Plus the atomic prep series. Tested for more than a week in -nightly and Ville/Imre indeed discovered some fun which is now fixed (and

[Intel-gfx] [PULL] first drm-intel-next for 3.18

Hi Dave, So you made noises that you wanted to open drm-next right after -rc1, so I've figured I'll test this ;-) drm-intel-next-2014-08-08: - Setting dp M2/N2 values plus state checker support (Vandana Kannan) - chv power well support (Ville) - DP training pattern 3 support for chv (Ville) - cle

[Intel-gfx] [PATCH v3] drm/i915: Rework GPU reset sequence to match driver load & thaw

From: "McAulay, Alistair" This patch is to address Daniels concerns over different code during reset: http://lists.freedesktop.org/archives/intel-gfx/2014-June/047758.html "The reason for aiming as hard as possible to use the exact same code for driver load, gpu reset and runtime pm/system resu

[Intel-gfx] [PATCH] drm/i915: Use dev_priv as first argument of for_each_pipe()

Chris has decided that enough is enough. It's time to fixup dev Vs dev_priv and the, oh so awful, INTEL_INFO(). This is a modest contribution to the crusade. Suggested-by: Chris Wilson Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_debugfs.c | 10 +++--- drivers/gpu/drm/i915/i915_

Re: [Intel-gfx] [PATCH] drm/i915: Idleness detection for DRRS

On Aug-07-2014 7:27 PM, Daniel Vetter wrote: > Hi Vandana, > > I think we need to start over from a fresh&clean slate with this part > - too much changed and all the differen revisions of this patch don't > provide that much information. > > Also as Chris says this introduces yet another idleness

Re: [Intel-gfx] [PATCH] drm/i915: fix i915_frequency_info on BDW

2014-08-15 13:50 GMT-03:00 Rodrigo Vivi : > > > > On Fri, Aug 1, 2014 at 2:14 PM, Paulo Zanoni wrote: >> >> From: Paulo Zanoni >> >> The GEN6_PM* registers don't exist on BDW anymore, so when we read >> this file we trigger unclaimed register errors. The equivalent BDW >> register for PMs is GEN8

Re: [Intel-gfx] [PATCH v2] drm/i915: Rework GPU reset sequence to match driver load & thaw

"Mcaulay, Alistair" writes: > Hi Mika / Daniel, > > below is the basic code path of a reset which has been changed by my patch: > > i915_reset() > { > > i915_gem_reset() -> This used to call i915_gem_context_reset(), which > has now been removed. > . > i915_gem_

Re: [Intel-gfx] [PATCH] drm/i915: fix plane/cursor handling when runtime suspended

On Fri, Aug 15, 2014 at 01:47:18PM -0300, Paulo Zanoni wrote: > 2014-08-15 5:39 GMT-03:00 Ville Syrjälä : > > On Thu, Aug 14, 2014 at 12:06:02PM -0300, Paulo Zanoni wrote: > >> From: Paulo Zanoni > >> > >> If we're runtime suspended and try to use the plane interfaces, we > >> will get a lot of WA

Re: [Intel-gfx] [PATCH] drm/i915: fix i915_frequency_info on BDW

On Fri, Aug 1, 2014 at 2:14 PM, Paulo Zanoni wrote: > From: Paulo Zanoni > > The GEN6_PM* registers don't exist on BDW anymore, so when we read > this file we trigger unclaimed register errors. The equivalent BDW > register for PMs is GEN8_GT_I*R(2), so use it. > > Testcase: igt/pm_rpm/debugfs-r

Re: [Intel-gfx] [PATCH] drm/i915: fix plane/cursor handling when runtime suspended

2014-08-15 5:39 GMT-03:00 Ville Syrjälä : > On Thu, Aug 14, 2014 at 12:06:02PM -0300, Paulo Zanoni wrote: >> From: Paulo Zanoni >> >> If we're runtime suspended and try to use the plane interfaces, we >> will get a lot of WARNs saying we did the wrong thing. >> >> We need to get runtime PM referen

[Intel-gfx] [QA 08/15 ww33] Testing report for `drm-intel-testing` (was: Updated -next)

Summary We covered the platform: Broadwell, Baytrail-M, Haswell (mobile, desktop and ULT), Ivybridge, SandyBridge, IronLake. In this circle, 3 new bugs are filed. Bug 82611 - [BDW Regression ]HDMI hot plug case ERROR. Bug 82551

[Intel-gfx] [PATCH] drm/i915/bdw: Disable execlists by default

We still have a few missing bits and pieces to have execlists enabled by default eg. the error capture or the render state initialization and so it wouldn't be wise to enable it by default on BDW just yet. Cc: Daniel Vetter Cc: Thomas Daniel Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i9

Re: [Intel-gfx] [PATCH v2] drm/i915: Rework GPU reset sequence to match driver load & thaw

On Fri, Aug 15, 2014 at 3:33 PM, Mcaulay, Alistair wrote: > below is the basic code path of a reset which has been changed by my patch: > > i915_reset() > { > > i915_gem_reset() -> This used to call i915_gem_context_reset(), which > has now been removed. > . >

Re: [Intel-gfx] [PATCH 11/43] drm/i915/bdw: Render moot context reset and switch with Execlists

On Fri, Aug 15, 2014 at 10:22:01AM +, Daniel, Thomas wrote: > > > > -Original Message- > > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel > > Vetter > > Sent: Monday, August 11, 2014 3:30 PM > > To: Daniel, Thomas > > Cc: intel-gfx@lists.freedesktop.org > > Su

Re: [Intel-gfx] [PATCH] drm: fix plane rotation when restoring fbdev configuration

On 15 August 2014 11:22, Daniel Vetter wrote: > On Fri, Aug 15, 2014 at 10:48:05AM +0100, Thomas Wood wrote: >> On 15 August 2014 10:42, Thomas Wood wrote: >> > On 14 August 2014 17:02, Daniel Vetter wrote: >> >> On Thu, Aug 14, 2014 at 04:33:18PM +0100, Thomas Wood wrote: >> >>> Make sure plane

Re: [Intel-gfx] [REGRESSION BISECTED] backlight control stops workin with 3.14 and later

On Thu, 14 Aug 2014, Bertrik Sikken wrote: > Hi Jani, > > On 13-8-2014 3:43, Jani Nikula wrote: >> On Wed, 23 Jul 2014, Hans de Goede wrote: >>> On 07/22/2014 08:52 AM, Daniel Vetter wrote: On Tue, Jul 22, 2014 at 8:42 AM, Hans de Goede wrote: > > > Also please grab latest intel-gpu-t

Re: [Intel-gfx] [PATCH 16/16] drm/i915: Preserve VGACNTR bits from the BIOS

On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä My Fujistsu-Siemens Lifebook S6010 doesn't like to resume from S3 unless VGACNTR has been restore to the original value. The BIOS value in this case was 0x0124008E. Setting the "VGA disable" bit doesn't interfere with

Re: [Intel-gfx] [PATCH v2 15/16] drm/i915: Add pipe B force quirk for 830M

On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä 830M has problems when some of the pipes are disabled. Namely if a plane, DVO port etc. is currently assigned to a disabled pipe, it can't moved to the other pipe until the current pipe is also enabled. To keep things

Re: [Intel-gfx] [PATCH 14/16] Revert "drm/i915: Nuke pipe A quirk on i830M"

On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä 830 really does want the pipe A quirk. The planes and ports don't react to any register writes unless the pipe currently attached to them is running, so it's impossible to move them to the other pipe unless both pipes

Re: [Intel-gfx] [PATCH 13/16] drm/i915: Fix DVO 2x clock enable on 830M

On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä The spec says: "For the correct operation of the muxed DVO pins (GDEVSELB/ I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock Enable) must be set to “1” in bo

Re: [Intel-gfx] [PATCH 12/16] drm/i915: Check pixel clock in ns2501 mode_valid hook

On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä The vbt on my Fujitsu-Siemens Lifebook S6010 provides two 800x600 modes, 60Hz and 56Hz. The magic register values we have correspond to the 60Hz mode, and as I don't know how one would trick the VGA BIOS to set up the

Re: [Intel-gfx] [PATCH v2] drm/i915: Rework GPU reset sequence to match driver load & thaw

Hi Mika / Daniel, below is the basic code path of a reset which has been changed by my patch: i915_reset() { i915_gem_reset() -> This used to call i915_gem_context_reset(), which has now been removed. . i915_gem_init_hw() .

Re: [Intel-gfx] [PATCH 11/16] drm/i915: Init important ns2501 registers

On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä In my earlier rewrite I missed a few important registers. Thomas Richter noticed that they're needed to make his machine resume correctly. Looks like IEGD does a one time init of these three registers. We don't have

Re: [Intel-gfx] [PATCH 10/16] drm/i915: Rewrite ns2501 driver a bit

On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä Try to use the same programming sequence as used by the IEGD driver. Also shovel the magic register values into a big static const array. The register values are actually the based on what the BIOS programs on the F

Re: [Intel-gfx] [PATCH 09/16] drm/i915: Kill useless ns2501_dump_regs

On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä Signed-off-by: Ville Syrjälä Reviewed-by: Thomas Richter --- drivers/gpu/drm/i915/dvo_ns2501.c | 17 - 1 file changed, 17 deletions(-) diff --git a/drivers/gpu/drm/i915/dvo_ns2501.c b/driver

Re: [Intel-gfx] [PATCH 07/16] drm/i915: Enable DVO between mode_set and dpms hooks

On 15.08.2014 00:21, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä To more closely match the IEGD ns2501 driver behaviour, call the mode_set hook while the DVO port is still disabled, then enable the DVO port, and finally call the dpms hook. Signed-off-by: Ville Syrjälä Tested-by

Re: [Intel-gfx] [PATCH 08/16] drm/i915: Don't call DVO mode_set hook on DPMS changes

On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä Calling the mode_set hook on DPMS changes doesn't seem to be necessary for ns2501. Just drop it. Signed-off-by: Ville Syrjälä Tested-by: Thomas Richter --- drivers/gpu/drm/i915/intel_dvo.c | 4 1 file c

Re: [Intel-gfx] [PATCH 06/16] drm/i915: ns2501 is on DVOB

On 15.08.2014 00:21, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä On Fujitsu-Siememens S6010 the ns2501 chip is hooked up to DVOB instead of DVOC. FIXME: Maybe need to dig out the correct DVO port from VBT Signed-off-by: Ville Syrjälä Tested-by: Thomas Richter --- drivers/

Re: [Intel-gfx] [PATCH v3 05/16] drm/i915: Disable double wide even when leaving the pipe on

On 15.08.2014 00:21, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä Disable double wide even if the pipe quirk compels us to leave the pipe running. Double wide has certain implications for the plane assignments so best keep it off. Also helps resuming from S3 on the Fujitsu-Siemens

Re: [Intel-gfx] [PATCH 04/16] drm/i915: Pass intel_crtc to intel_disable_pipe() and intel_wait_for_pipe_off()

On 15.08.2014 00:21, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä Just pass the intel_crtc around instead of dev_priv+pipe. Also make intel_wait_for_pipe_off() static since it's only used in intel_display.c. Signed-off-by: Ville Syrjälä Tested-by: Thomas Richter --- driver

Re: [Intel-gfx] [PATCH 01/16] drm/i915: Fix gen2 planes B and C max watermark value

On 15.08.2014 00:21, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä The max watermark value for gen2 planes B and C is 0x1f, instead of the 0x3f that plane A uses. Also check against the max even if the pipe is disabled since the FIFO size exceeds the plane B and C max watermark valu

Re: [Intel-gfx] [PATCH 12/16] drm/i915: Check pixel clock in ns2501 mode_valid hook

On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä The vbt on my Fujitsu-Siemens Lifebook S6010 provides two 800x600 modes, 60Hz and 56Hz. The magic register values we have correspond to the 60Hz mode, and as I don't know how one would trick the VGA BIOS to set up the

Re: [Intel-gfx] [PATCH 11/16] drm/i915: Init important ns2501 registers

On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä In my earlier rewrite I missed a few important registers. Thomas Richter noticed that they're needed to make his machine resume correctly. Looks like IEGD does a one time init of these three registers. We don't have

Re: [Intel-gfx] [PATCH 10/16] drm/i915: Rewrite ns2501 driver a bit

On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä Try to use the same programming sequence as used by the IEGD driver. Also shovel the magic register values into a big static const array. The register values are actually the based on what the BIOS programs on the F

Re: [Intel-gfx] [PATCH 09/16] drm/i915: Kill useless ns2501_dump_regs

On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä Looks perfectly fine to me. Signed-off-by: Thomas Richter Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/dvo_ns2501.c | 17 - 1 file changed, 17 deletions(-) diff --git a/drivers/gpu/

Re: [Intel-gfx] [PATCH 42/43] drm/i915/bdw: Pin the context backing objects to GGTT on-demand

On Thu, Jul 24, 2014 at 05:04:50PM +0100, Thomas Daniel wrote: > From: Oscar Mateo > > Up until now, we have pinned every logical ring context backing object > during creation, and left it pinned until destruction. This made my life > easier, but it's a harmful thing to do, because we cause fragm

Re: [Intel-gfx] [PATCH 40/43] drm/i915/bdw: Document Logical Rings, LR contexts and Execlists

On Thu, Jul 24, 2014 at 05:04:48PM +0100, Thomas Daniel wrote: > +/** > + * intel_lr_context_render_state_init() - render state init for Execlists > + * @ring: Engine Command Streamer. > + * @ctx: Context to initialize. > + * > + * A.K.A. null-context, A.K.A. golden-context. In a word, the render e

Re: [Intel-gfx] [PATCH 35/43] drm/i915/bdw: Make sure error capture keeps working with Execlists

On Thu, Jul 24, 2014 at 05:04:43PM +0100, Thomas Daniel wrote: > From: Oscar Mateo > > Since the ringbuffer does not belong per engine anymore, we have to > make sure that we are always recording the correct ringbuffer. > > TODO: This is only a small fix to keep basic error capture working, but

Re: [Intel-gfx] [PATCH] drm/i915/dp: Backlight PWM enable before BL Enable assert

On Fri, 15 Aug 2014, clinton.a.tay...@intel.com wrote: > From: Clint Taylor > > Backlight on delay uses PWM enable time to seperate PWM to > backlight enable assert. Previous time difference used timing > from VDD enable which occur several seconds before resulting > in PWM starting 5ms after back

Re: [Intel-gfx] [PATCH 1/4] drm/i915: fix HPD IRQ reenable work cancelation

On Fri, 2014-08-15 at 12:48 +0300, Jani Nikula wrote: > On Fri, 15 Aug 2014, Imre Deak wrote: > > On Wed, 2014-08-13 at 19:33 +0300, Ville Syrjälä wrote: > >> The series seems fine to me. > >> > >> Reviewed-by: Ville Syrjälä > >> for the rest as well. > > > > Thanks, I assume it's for v2. I'd sa

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Do not access stolen memory directly by the CPU, even for error capture

Chris Wilson writes: > For stolen pages, since it is verboten to access them directly on many > architectures, we have to read them through the GTT aperture. If they > are not accessible through the aperture, then we have to abort. > > This was complicated by > > commit 8b6124a633d8095b0c8364f585

[Intel-gfx] [PATCH] drm/i915/bdw: Don't write PDP in the legacy way when using LRCs

From: Oscar Mateo This is mostly for correctness so that we know we are running the LR context correctly (this is, the PDPs are contained inside the context object). v2: Move the check to inside the enable PPGTT function. The switch happens in two places: the legacy context switch (that we won't

Re: [Intel-gfx] [PATCH] drm: fix plane rotation when restoring fbdev configuration

On Fri, Aug 15, 2014 at 10:48:05AM +0100, Thomas Wood wrote: > On 15 August 2014 10:42, Thomas Wood wrote: > > On 14 August 2014 17:02, Daniel Vetter wrote: > >> On Thu, Aug 14, 2014 at 04:33:18PM +0100, Thomas Wood wrote: > >>> Make sure plane rotation is reset correctly when restoring the fbdev

Re: [Intel-gfx] Usage of _PAGE_PCD et al in i915 driver

On Thu, Aug 14, 2014 at 05:55:11AM +0200, Juergen Gross wrote: > On 08/13/2014 05:07 PM, Jesse Barnes wrote: > > On Fri, 8 Aug 2014 15:14:15 +0200 > > Daniel Vetter wrote: > > > >> Adding relevant mailing lists. > >> > >> On Fri, Aug 8, 2014 at 1:23 PM, Juergen Gross wrote: > >>> I'm just about t

Re: [Intel-gfx] [PATCH 11/43] drm/i915/bdw: Render moot context reset and switch with Execlists

> -Original Message- > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel > Vetter > Sent: Monday, August 11, 2014 3:30 PM > To: Daniel, Thomas > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 11/43] drm/i915/bdw: Render moot context > reset and

Re: [Intel-gfx] Usage of _PAGE_PCD et al in i915 driver

On 08/13/2014 05:07 PM, Jesse Barnes wrote: On Fri, 8 Aug 2014 15:14:15 +0200 Daniel Vetter wrote: Adding relevant mailing lists. On Fri, Aug 8, 2014 at 1:23 PM, Juergen Gross wrote: I'm just about to create a patch for full PAT support in the Linux kernel, including Xen. For this purpose I

Re: [Intel-gfx] [PATCH 1/4] drm/i915: fix HPD IRQ reenable work cancelation

On Fri, 15 Aug 2014, Imre Deak wrote: > On Wed, 2014-08-13 at 19:33 +0300, Ville Syrjälä wrote: >> The series seems fine to me. >> >> Reviewed-by: Ville Syrjälä >> for the rest as well. > > Thanks, I assume it's for v2. I'd say this is for -fixes. The problem > existed even in 3.16, but only the

Re: [Intel-gfx] [PATCH] drm: fix plane rotation when restoring fbdev configuration

On 15 August 2014 10:42, Thomas Wood wrote: > On 14 August 2014 17:02, Daniel Vetter wrote: >> On Thu, Aug 14, 2014 at 04:33:18PM +0100, Thomas Wood wrote: >>> Make sure plane rotation is reset correctly when restoring the fbdev >>> configuration by using drm_mode_plane_set_obj_prop. This calls t

Re: [Intel-gfx] [PATCH] drm: fix plane rotation when restoring fbdev configuration

On 14 August 2014 17:02, Daniel Vetter wrote: > On Thu, Aug 14, 2014 at 04:33:18PM +0100, Thomas Wood wrote: >> Make sure plane rotation is reset correctly when restoring the fbdev >> configuration by using drm_mode_plane_set_obj_prop. This calls the >> driver's set_property callback and ensures t

Re: [Intel-gfx] [PATCH 30/43] drm/i915/bdw: Two-stage execlist submit process

On Fri, Aug 15, 2014 at 08:51:22AM +, Daniel, Thomas wrote: > > -Original Message- > > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel > > Vetter > > Sent: Thursday, August 14, 2014 9:10 PM > > To: Daniel, Thomas > > Cc: intel-gfx@lists.freedesktop.org > > Subjec

Re: [Intel-gfx] [PATCH 1/4] drm/i915: fix HPD IRQ reenable work cancelation

On Wed, 2014-08-13 at 19:33 +0300, Ville Syrjälä wrote: > The series seems fine to me. > > Reviewed-by: Ville Syrjälä > for the rest as well. Thanks, I assume it's for v2. I'd say this is for -fixes. The problem existed even in 3.16, but only the MST support made it apparent with the extra HPD s

Re: [Intel-gfx] [PATCH 30/43] drm/i915/bdw: Two-stage execlist submit process

> -Original Message- > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel > Vetter > Sent: Thursday, August 14, 2014 9:10 PM > To: Daniel, Thomas > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 30/43] drm/i915/bdw: Two-stage execlist > submit p

Re: [Intel-gfx] [PATCH 27/43] drm/i915/bdw: Render state init for Execlists

> -Original Message- > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel > Vetter > Sent: Thursday, August 14, 2014 9:00 PM > To: Daniel, Thomas > Cc: Daniel Vetter; intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 27/43] drm/i915/bdw: Render state i

Re: [Intel-gfx] [PATCH] drm/i915: fix plane/cursor handling when runtime suspended

On Thu, Aug 14, 2014 at 12:06:02PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > > If we're runtime suspended and try to use the plane interfaces, we > will get a lot of WARNs saying we did the wrong thing. > > We need to get runtime PM references to pin the objects, and to > change the fenc

Re: [Intel-gfx] [PATCH 00/16] drm/i915: 830M/ns201 fixes again

On Fri, Aug 15, 2014 at 01:21:52AM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Thomas asked me to repost my 830/ns2501 patches. So here they are. I added > a few more patches (trickle feed and unused ring init) to fix some post-resume > issues. The primary plane rmw elim