On Fri, Aug 1, 2014 at 2:14 PM, Paulo Zanoni <przan...@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zan...@intel.com> > > The GEN6_PM* registers don't exist on BDW anymore, so when we read > this file we trigger unclaimed register errors. The equivalent BDW > register for PMs is GEN8_GT_I*R(2), so use it. > > Testcase: igt/pm_rpm/debugfs-read > Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 20 +++++++++++++++----- > 1 file changed, 15 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c > b/drivers/gpu/drm/i915/i915_debugfs.c > index 9e737b7..17bd20ff 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1024,6 +1024,7 @@ static int i915_frequency_info(struct seq_file *m, > void *unused) > u32 rpstat, cagf, reqf; > u32 rpupei, rpcurup, rpprevup; > u32 rpdownei, rpcurdown, rpprevdown; > + u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; > int max_freq; > > /* RPSTAT1 is in the GT power well */ > @@ -1061,12 +1062,21 @@ static int i915_frequency_info(struct seq_file *m, > void *unused) > gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); > mutex_unlock(&dev->struct_mutex); > > + if (IS_GEN6(dev) || IS_GEN7(dev)) { > + pm_ier = I915_READ(GEN6_PMIER); > + pm_imr = I915_READ(GEN6_PMIMR); > + pm_isr = I915_READ(GEN6_PMISR); > + pm_iir = I915_READ(GEN6_PMIIR); > + pm_mask = I915_READ(GEN6_PMINTRMSK); > + } else { > + pm_ier = I915_READ(GEN8_GT_IER(2)); > + pm_imr = I915_READ(GEN8_GT_IMR(2)); > + pm_isr = I915_READ(GEN8_GT_ISR(2)); > + pm_iir = I915_READ(GEN8_GT_IIR(2)); > Why do we care only about GT(2) interrupt reg? What about other 0, 1 and 3 regs? Could this explain GT3 failures? > + pm_mask = I915_READ(GEN6_PMINTRMSK); > + } > seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x > IIR=0x%08x, MASK=0x%08x\n", > - I915_READ(GEN6_PMIER), > - I915_READ(GEN6_PMIMR), > - I915_READ(GEN6_PMISR), > - I915_READ(GEN6_PMIIR), > - I915_READ(GEN6_PMINTRMSK)); > + pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); > seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); > seq_printf(m, "Render p-state ratio: %d\n", > (gt_perf_status & 0xff00) >> 8); > -- > 2.0.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > -- Rodrigo Vivi Blog: http://blog.vivi.eng.br
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