On Fri, 04 Apr 2014, Vandana Kannan wrote:
> Adding support to detect display idleness by tracking page flip from
> user space. Switch to low refresh rate is triggered after 2 seconds of
> idleness. The delay is configurable. If there is a page flip or call to
> update the plane, then high refresh
Adding support to detect display idleness by tracking page flip from
user space. Switch to low refresh rate is triggered after 2 seconds of
idleness. The delay is configurable. If there is a page flip or call to
update the plane, then high refresh rate is applied.
The feature is not used in dual-di
From: Pradeep Bhat
This patch computes and stored 2nd M/N/TU for switching to different
refresh rate dynamically. PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle
between alternate refresh rates programmed in 2nd M/N/TU registers.
v2: Daniel's review comments
Computing M2/N2 in compute_config and st
From: Pradeep Bhat
This patch and finds out the lowest refresh rate supported for the resolution
same as the fixed_mode.
It also checks the VBT fields to see if panel supports seamless DRRS or not.
Based on above data it marks whether eDP panel supports seamless DRRS or not.
This information is n
On Thu, Apr 03, 2014 at 08:06:30AM +0100, Chris Wilson wrote:
> If we always initialize kref for the context, even if we are using fake
> contexts for hangstats when there is no hw support, we can forgo the
> dance to dereference the ctx->obj and inspect whether we are permitted
> to use kref insid
On Thu, Apr 03, 2014 at 02:13:55PM -0400, Giacomo Comes wrote:
> The Dell XPS 8700 has a onboard Display port and HDMI port and no VGA port.
> The call intel_crt_init freeze the machine, so skip such call.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73559
> Signed-off-by: Giacomo Co
On Thu, Apr 03, 2014 at 09:28:34PM +0100, Chris Wilson wrote:
> On Thu, Apr 03, 2014 at 08:02:42PM +0300, Imre Deak wrote:
> > This typo may lead to missed RPS interrupts and as a result a too
> > low or too high frequency for the current workload. The interrupt mask
> > will be set properly at a s
On Thu, Apr 03, 2014 at 04:23:05PM +0100, Chris Wilson wrote:
> On Thu, Apr 03, 2014 at 05:16:16PM +0200, Daniel Vetter wrote:
> > btw the 1k thing at least on i865G is iirc just the writeout fifo between
> > the cpu and the gmch to paper over FSB latencies (or whatever irked hw
> > designers).
>
On Thu, Apr 03, 2014 at 05:31:17PM +0200, Takashi Iwai wrote:
> At Thu, 3 Apr 2014 17:23:10 +0200,
> Daniel Vetter wrote:
> >
> > On Wed, Apr 02, 2014 at 02:59:54PM +0200, Takashi Iwai wrote:
> > > At Tue, 1 Apr 2014 22:26:20 +0200,
> > > Daniel Vetter wrote:
> > > >
> > > > On Tue, Apr 01, 2014
On Thu, Apr 03, 2014 at 09:01:28PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> As per the inputs provided by hardware team we still use DDR
> Rates as 0,1=800, 2=1066, 3=1333.
> With this change, Turbo freqs used on current machines matches.
>
> This reverts commit f64a28a7c5ab2
On Thu, 3 Apr 2014 22:55:24 +0200
Daniel Vetter wrote:
> On Thu, Apr 3, 2014 at 6:49 PM, Jesse Barnes wrote:
> >> > static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
> >> > @@ -738,9 +736,13 @@ static void intel_enable_hdmi(struct intel_encoder
> >> > *encoder)
> >> > stru
On Thu, Apr 3, 2014 at 6:49 PM, Jesse Barnes wrote:
>> > static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
>> > @@ -738,9 +736,13 @@ static void intel_enable_hdmi(struct intel_encoder
>> > *encoder)
>> > struct drm_i915_private *dev_priv = dev->dev_private;
>> > struct i
On Thu, Apr 03, 2014 at 08:02:42PM +0300, Imre Deak wrote:
> This typo may lead to missed RPS interrupts and as a result a too
> low or too high frequency for the current workload. The interrupt mask
> will be set properly at a subsequent GPU idle event, but can get
> corrupted again at the next RP
The Dell XPS 8700 has a onboard Display port and HDMI port and no VGA port.
The call intel_crt_init freeze the machine, so skip such call.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73559
Signed-off-by: Giacomo Comes
diff -Nraub a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i9
On Thu, 2014-04-03 at 19:47 +0200, Friedrich Oslage wrote:
> Hi,
>
> several months ago Alex Williamson added a patch to the linux kernel to
> enable VGA arbiter support for the IGD of Intel Core CPUs [1]. But just
> a month after that the patch was reverted [2].
>
> With these patches I am able
Hi,
several months ago Alex Williamson added a patch to the linux kernel to
enable VGA arbiter support for the IGD of Intel Core CPUs [1]. But just
a month after that the patch was reverted [2].
With these patches I am able to use VFIO and Qemu to passthrough a GTX
770 while using the Intel HD of
This typo may lead to missed RPS interrupts and as a result a too
low or too high frequency for the current workload. The interrupt mask
will be set properly at a subsequent GPU idle event, but can get
corrupted again at the next RPS up/down event.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i9
On Thu, 3 Apr 2014 17:19:56 +0200
Daniel Vetter wrote:
> On Wed, Apr 02, 2014 at 10:08:54AM -0700, Jesse Barnes wrote:
> > Needs to happen after clock is running or it doesn't behave correctly.
> >
> > Signed-off-by: Jesse Barnes
> > ---
> > drivers/gpu/drm/i915/intel_hdmi.c |6 --
> >
On Thu, Apr 03, 2014 at 11:32:30AM +0200, Daniel Vetter wrote:
> On Wed, Apr 02, 2014 at 08:26:23AM -0700, Randy Dunlap wrote:
> > On 04/02/2014 01:24 AM, Jani Nikula wrote:
> > > Drop the cast from the pointer diff to fix:
> > >
> > > drivers/gpu/drm/i915/i915_cmd_parser.c:405:4: warning: format
From: Deepak S
As per the inputs provided by hardware team we still use DDR
Rates as 0,1=800, 2=1066, 3=1333.
With this change, Turbo freqs used on current machines matches.
This reverts commit f64a28a7c5ab2fc342326de9e126acf3cc0f91d6.
commit f64a28a7c5ab2fc342326de9e126acf3cc0f91d6
Author: Je
At Thu, 3 Apr 2014 17:23:10 +0200,
Daniel Vetter wrote:
>
> On Wed, Apr 02, 2014 at 02:59:54PM +0200, Takashi Iwai wrote:
> > At Tue, 1 Apr 2014 22:26:20 +0200,
> > Daniel Vetter wrote:
> > >
> > > On Tue, Apr 01, 2014 at 09:50:43PM +0300, Imre Deak wrote:
> > > > On Tue, 2014-04-01 at 19:48 +020
On Thu, Apr 03, 2014 at 01:21:38PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 03, 2014 at 08:05:35AM +0100, Chris Wilson wrote:
> > On Wed, Apr 02, 2014 at 10:30:23PM -0700, Ben Widawsky wrote:
> > > We have been setting the bit which was originally BIOS dependent since:
> > > commit f05bb0c7b624252
On Thu, Apr 03, 2014 at 12:04:51PM +0100, Damien Lespiau wrote:
> On Thu, Apr 03, 2014 at 11:30:16AM +0200, Daniel Vetter wrote:
> > I've merged all the patches Jesse reviewed from this series, expect the
> > one Damien has a bikeshed pending.
>
> It wasn't bikeshedding, we were printing "%c",0 in
On Thu, Apr 03, 2014 at 11:54:32AM +0100, Damien Lespiau wrote:
> On Thu, Apr 03, 2014 at 01:28:33PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Print the enable_mask and status_mask from
> > __i915_{enable,disable}_pipestat() when the caller has messed them up
> >
On Wed, Apr 02, 2014 at 02:59:54PM +0200, Takashi Iwai wrote:
> At Tue, 1 Apr 2014 22:26:20 +0200,
> Daniel Vetter wrote:
> >
> > On Tue, Apr 01, 2014 at 09:50:43PM +0300, Imre Deak wrote:
> > > On Tue, 2014-04-01 at 19:48 +0200, Daniel Vetter wrote:
> > > > On Tue, Apr 01, 2014 at 07:55:22PM +030
On Thu, Apr 03, 2014 at 05:16:16PM +0200, Daniel Vetter wrote:
> btw the 1k thing at least on i865G is iirc just the writeout fifo between
> the cpu and the gmch to paper over FSB latencies (or whatever irked hw
> designers).
Isn't there a 1024 byte supercacheline for msaa as well? At least that
s
On Wed, Apr 02, 2014 at 10:08:54AM -0700, Jesse Barnes wrote:
> Needs to happen after clock is running or it doesn't behave correctly.
>
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/intel_hdmi.c |6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/driv
On Wed, Apr 02, 2014 at 02:58:54PM -0700, Jesse Barnes wrote:
> On Wed, 2 Apr 2014 16:36:07 +0100
> Chris Wilson wrote:
>
> > In commit a51435a3137ad8ae75c288c39bd2d8b2696bae8f
> > Author: Naresh Kumar Kachhi
> > Date: Wed Mar 12 16:39:40 2014 +0530
> >
> > drm/i915: disable rings before
On Thu, Apr 03, 2014 at 07:45:40AM +0100, Chris Wilson wrote:
> On Wed, Apr 02, 2014 at 02:57:11PM -0700, Jesse Barnes wrote:
> > On Wed, 2 Apr 2014 16:36:06 +0100
> > Chris Wilson wrote:
> >
> > > For readibility and guess at the meaning behind the constants.
> > >
> > > Signed-off-by: Chris W
On Thu, Mar 27, 2014 at 06:00:12PM +, oscar.ma...@intel.com wrote:
> +void gen8_handle_context_events(struct intel_engine *ring)
> +{
> + struct drm_i915_private *dev_priv = ring->dev->dev_private;
> + u32 status_pointer;
> + u8 read_pointer;
> + u8 write_pointer;
> + u32 st
On Thu, 03 Apr 2014, Vandana Kannan wrote:
> From: Pradeep Bhat
>
> This patch and finds out the lowest refresh rate supported for the resolution
> same as the fixed_mode.
> It also checks the VBT fields to see if panel supports seamless DRRS or not.
> Based on above data it marks whether eDP pan
Adding support to detect display idleness by tracking page flip from
user space. Switch to low refresh rate is triggered after 2 seconds of
idleness. The delay is configurable. If there is a page flip or call to
update the plane, then high refresh rate is applied.
The feature is not used in dual-di
On Thu, Apr 03, 2014 at 11:30:16AM +0200, Daniel Vetter wrote:
> I've merged all the patches Jesse reviewed from this series, expect the
> one Damien has a bikeshed pending.
It wasn't bikeshedding, we were printing "%c",0 instead of "%c",'A' :)
--
Damien
_
From: Pradeep Bhat
This patch computes and stored 2nd M/N/TU for switching to different
refresh rate dynamically. PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle
between alternate refresh rates programmed in 2nd M/N/TU registers.
v2: Daniel's review comments
Computing M2/N2 in compute_config and st
On Wed, Apr 02, 2014 at 07:46:37PM -0700, Ben Widawsky wrote:
> It seems we need this at least for the current platforms we have, but
> probably not later. In any event, it should cause too much harm as we do
> the same thing on several other platforms.
>
> Signed-off-by: Ben Widawsky
> ---
> dr
From: Pradeep Bhat
This patch and finds out the lowest refresh rate supported for the resolution
same as the fixed_mode.
It also checks the VBT fields to see if panel supports seamless DRRS or not.
Based on above data it marks whether eDP panel supports seamless DRRS or not.
This information is n
On Thu, Apr 03, 2014 at 01:28:33PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Print the enable_mask and status_mask from
> __i915_{enable,disable}_pipestat() when the caller has messed them up
> somehow.
>
> v2: Use pipe_name() (Damien)
> Fix a typo in the commit m
On Thu, Apr 03, 2014 at 01:36:25PM +0300, Mika Kuoppala wrote:
> Chris Wilson writes:
> > + if (to->obj == NULL) { /* We have the fake context */
> > + if (to != ring->last_context) {
> > + if (to)
> > + i915_gem_context_reference(to);
>
Chris Wilson writes:
> If we always initialize kref for the context, even if we are using fake
> contexts for hangstats when there is no hw support, we can forgo the
> dance to dereference the ctx->obj and inspect whether we are permitted
> to use kref inside i915_gem_context_reference() and _unr
On Wed, Apr 02, 2014 at 10:08:52AM -0700, Jesse Barnes wrote:
> We also do a disable later when we write a specific infoframe, but here
> we do it to prevent sending a stale one before updating the infoframes.
>
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/intel_hdmi.c |4 ++--
On Wed, Apr 02, 2014 at 10:08:54AM -0700, Jesse Barnes wrote:
> Needs to happen after clock is running or it doesn't behave correctly.
Subject of the patch isn't correct. You enable it after the PLL, but
still before the port gets enabled. Which I believe is the order we
want. So you should just f
On Wed, Apr 02, 2014 at 10:08:53AM -0700, Jesse Barnes wrote:
> Allows sending of the null packets for conformance.
Just set it for all platforms? I'm not aware of any downside of setting
it always.
Anyways seems sane enough so even for just VLV:
Reviewed-by: Ville Syrjälä
>
> Signed-off-by: J
From: Ville Syrjälä
Print the enable_mask and status_mask from
__i915_{enable,disable}_pipestat() when the caller has messed them up
somehow.
v2: Use pipe_name() (Damien)
Fix a typo in the commit message
Reviewed-by: Jesse Barnes
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915
On Thu, Apr 03, 2014 at 08:05:35AM +0100, Chris Wilson wrote:
> On Wed, Apr 02, 2014 at 10:30:23PM -0700, Ben Widawsky wrote:
> > We have been setting the bit which was originally BIOS dependent since:
> > commit f05bb0c7b624252a5e768287e340e8e45df96e42
> > Author: Chris Wilson
> > Date: Sun Jan
On Thu, Apr 03, 2014 at 08:05:35AM +0100, Chris Wilson wrote:
> On Wed, Apr 02, 2014 at 10:30:23PM -0700, Ben Widawsky wrote:
> > We have been setting the bit which was originally BIOS dependent since:
> > commit f05bb0c7b624252a5e768287e340e8e45df96e42
> > Author: Chris Wilson
> > Date: Sun Jan
On Wed, Apr 02, 2014 at 07:21:01PM +0100, oscar.ma...@intel.com wrote:
> From: Oscar Mateo
>
> Otherwise, we do a NULL pointer dereference.
>
> I've seen this happen while handling an error in
> i915_gem_object_pin_to_display_plane():
>
> If i915_gem_object_set_cache_level() fails, we call is_p
On Wed, Apr 02, 2014 at 08:26:23AM -0700, Randy Dunlap wrote:
> On 04/02/2014 01:24 AM, Jani Nikula wrote:
> > Drop the cast from the pointer diff to fix:
> >
> > drivers/gpu/drm/i915/i915_cmd_parser.c:405:4: warning: format '%td' expects
> > argument of type 'ptrdiff_t', but argument 5 has type '
On Wed, Apr 02, 2014 at 05:08:34PM +0100, Damien Lespiau wrote:
> On Wed, Apr 02, 2014 at 04:28:06PM +0100, Chris Wilson wrote:
> > On Wed, Apr 02, 2014 at 11:14:58AM -0300, Paulo Zanoni wrote:
> > > 2014-04-02 8:27 GMT-03:00 Chris Wilson :
> > > > On Wed, Apr 02, 2014 at 12:23:51PM +0100, Chris Wi
On Wed, Apr 02, 2014 at 10:29:08AM -0700, Jesse Barnes wrote:
> On Mon, 31 Mar 2014 18:21:29 +0300
> ville.syrj...@linux.intel.com wrote:
>
> > From: Rafael Barbalho
> >
> > The framecount register was still using the old PIPE macro instead
> > of the new PIPE2 macro
> >
> > Signed-off-by: Rafa
On Mon, Mar 31, 2014 at 06:21:27PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> DPIO reads from groups/broadcast register offsets for PCS and
> TX return all 1's. If that result gets used for something
> we'll probably end up doing something wrong. So warn when that
> hap
On Wed, Apr 02, 2014 at 10:28:05AM -0700, Ben Widawsky wrote:
> On Mon, Mar 31, 2014 at 06:17:16PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Iterate over all the PDP registers instead of just printing PDP0 four
> > times in gen8 PPGTT debugfs info.
> >
> > Signe
On Tue, Apr 01, 2014 at 11:14:08AM +0300, Jani Nikula wrote:
> On Tue, 01 Apr 2014, Daniel Vetter wrote:
> > VTd has a few too many "outright disable the damn thing" workarounds
> > accumulated and for validation we want a simple knob to make sure we
> > disable them all.
> >
> > Since this is for
On Wed, 2014-03-26 at 13:20 +0530, sourab gupta wrote:
> Hi Ville/Damien,
> Can you please review the below patch(v3) for mmio flips.
> Thanks,
> Sourab
>
> On Sun, 2014-03-23 at 09:01 +, Gupta, Sourab wrote:
> > From: Sourab Gupta
> >
> > Using MMIO based flips on VLV for Media power well r
On Wed, 02 Apr 2014, Jesse Barnes wrote:
> Needs to happen after clock is running or it doesn't behave correctly.
Do you think this might fix some HDMI audio related bugs we have?
Jani.
>
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/intel_hdmi.c |6 --
> 1 file changed,
If we always initialize kref for the context, even if we are using fake
contexts for hangstats when there is no hw support, we can forgo the
dance to dereference the ctx->obj and inspect whether we are permitted
to use kref inside i915_gem_context_reference() and _unreference().
My ulterior motive
On Thu, 03 Apr 2014, James Hogan wrote:
> Hi,
>
> I've noticed that v3.14 breaks the backlight on Dell XPS13. Reverting the
> following commit fixes the issue for me (i.e. the GUI brightness controls
> work
> again):
>
> bc0bb9fd1c78 drm/i915: remove QUIRK_NO_PCH_PWM_ENABLE
>
> It appears that
On Wed, Apr 02, 2014 at 10:30:23PM -0700, Ben Widawsky wrote:
> We have been setting the bit which was originally BIOS dependent since:
> commit f05bb0c7b624252a5e768287e340e8e45df96e42
> Author: Chris Wilson
> Date: Sun Jan 20 16:33:32 2013 +
>
> drm/i915: GFX_MODE Flush TLB Invalidate
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