On Thu, Mar 20, 2014 at 03:11:21PM +, Chris Wilson wrote:
> The computation of required framebuffer size in
>
> commit d978ef14456a38034f6c0e94a794129501f89200
> Author: Jesse Barnes
> Date: Fri Mar 7 08:57:51 2014 -0800
>
> drm/i915: Wrap the preallocated BIOS framebuffer and preserve
Reminder for review :)
On Tue, 2014-04-01 at 10:21 +0530, Sagar Arun Kamble wrote:
> Gentle Reminder for reviewing this and related patches:
> http://lists.freedesktop.org/archives/intel-gfx/2014-March/042350.html
> http://lists.freedesktop.org/archives/intel-gfx/2014-March/042351.html
> http://li
On Apr-01-2014 6:55 PM, Jani Nikula wrote:
> On Fri, 28 Mar 2014, Vandana Kannan wrote:
>> From: Pradeep Bhat
>>
>> This patch computes and stored 2nd M/N/TU for switching to different
>> refresh rate dynamically. PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle
>> between alternate refresh rates pro
On Tue, Apr 01, 2014 at 07:39:48PM -0300, Paulo Zanoni wrote:
> From: Zhenyu Wang
>
> Signed-off-by: Zhenyu Wang
Reviewed-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
On Tue, Apr 01, 2014 at 07:39:49PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> If I boot my Broadwell machine to X on a system with Mesa Gallium
> llvmpipe instead of i965, then kill X and try to run pm_pc8.c, when we
> disable PC8 and call gen6_update_ring_freq(), we will get stuck on an
On Mon, Mar 31, 2014 at 06:17:18PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> BSpec seems to tell us we need the MI_ARB_ON_OFF w/a around
> MI_SET_CONTEXT on gen8.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_gem_con
On Tue, Apr 01, 2014 at 10:05:12PM +0100, Damien Lespiau wrote:
> On Tue, Apr 01, 2014 at 12:18:24PM -0700, Ben Widawsky wrote:
> > On Tue, Apr 01, 2014 at 02:51:27PM +0100, Damien Lespiau wrote:
> > > On Tue, Apr 01, 2014 at 02:47:19PM +0100, Mateo Lozano, Oscar wrote:
> > > > > > --- a/drivers/gp
On Tue, Apr 01, 2014 at 05:43:06PM -0700, Ben Widawsky wrote:
> So let's not do it every time we switch.
>
> v2: v1 skipped the switch for all gens. We still need it pre-gen8.
>
> Signed-off-by: Ben Widawsky
Please ignore this patch. I actually need to rework some stuff. 1 and 3
are still good
So let's not do it every time we switch.
v2: v1 skipped the switch for all gens. We still need it pre-gen8.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_context.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/dr
So let's not do it every time we switch.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 0e8fd1e..743fc42 100644
--
Broadwell is perfectly capable of full PPGTT. I've been using it for
some time, and seen no especially ill effects.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/
On GEN8 the PDPs are saved and restored with context, which means we
must set them after the context switch has occurred. If we do not do
this, we end up saving the new PDPs for the old context.
The next patch will go one step further and actually only load the PDPs
once.
Example of a problem
LRI
For error state, like the recent modification to ACTHD, FADD also gets
an upper dword. This is useful for debug to make sure the fetch address
and head are similar.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 7 +--
dr
On Tue, Apr 01, 2014 at 08:55:14AM -0700, Ben Widawsky wrote:
> Broadwell is perfectly capable of full PPGTT. I've been using it for
> some time, and seen no especially ill effects.
>
> Signed-off-by: Ben Widawsky
Nak. I spoke too soon. 1 context + default works fine. More than that
gets ugly.
From: Paulo Zanoni
Because if we keep the current code, we'll get tons of WARNs on
Broadwell, since the code is Haswell-specific.
We could have also added a Broadwell-specific code there, but it's not
really needed since we never disable LCPLL with the hotplug interrupts
still enabled. So keep t
From: Paulo Zanoni
Hi
I got a little surprised to see the BDW patches merged so fast, I thought I was
going to have time to resend the last series with these last patches in.
The first patch replaces a HSW-specific WARN that was happening all the time on
BDW with a gen-agnostic WARN. The second
From: Zhenyu Wang
Signed-off-by: Zhenyu Wang
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 41da286..8d18455 100644
--- a/drivers/gpu/drm/i915/i915_debug
From: Paulo Zanoni
If I boot my Broadwell machine to X on a system with Mesa Gallium
llvmpipe instead of i965, then kill X and try to run pm_pc8.c, when we
disable PC8 and call gen6_update_ring_freq(), we will get stuck on an
infinite loop because the frequencies are zero and the variables are
un
On Wed, 2014-04-02 at 00:07 +0200, Daniel Vetter wrote:
> On Wed, Apr 02, 2014 at 12:42:50AM +0300, Imre Deak wrote:
> > On Wed, 2014-04-02 at 00:36 +0300, Imre Deak wrote:
> > > On Tue, 2014-04-01 at 18:04 -0300, Paulo Zanoni wrote:
> > > > 2014-04-01 17:52 GMT-03:00 Daniel Vetter :
> > > > > On T
Ensure that existing driver loops over all planes do not change behavior
when we begin adding new types of planes (primary and cursor) to the DRM
plane list in future patches.
v2: Switch to using drm_for_each_legacy_plane()
Cc: Intel Graphics Development
Signed-off-by: Matt Roper
---
drivers/g
On Wed, Apr 02, 2014 at 12:42:50AM +0300, Imre Deak wrote:
> On Wed, 2014-04-02 at 00:36 +0300, Imre Deak wrote:
> > On Tue, 2014-04-01 at 18:04 -0300, Paulo Zanoni wrote:
> > > 2014-04-01 17:52 GMT-03:00 Daniel Vetter :
> > > > On Tue, Apr 01, 2014 at 05:48:15PM -0300, Paulo Zanoni wrote:
> > > >>
On Wed, 2014-04-02 at 00:36 +0300, Imre Deak wrote:
> On Tue, 2014-04-01 at 18:04 -0300, Paulo Zanoni wrote:
> > 2014-04-01 17:52 GMT-03:00 Daniel Vetter :
> > > On Tue, Apr 01, 2014 at 05:48:15PM -0300, Paulo Zanoni wrote:
> > >> 2014-04-01 17:37 GMT-03:00 Daniel Vetter :
> > >> > On Tue, Apr 01,
On Tue, 2014-04-01 at 18:04 -0300, Paulo Zanoni wrote:
> 2014-04-01 17:52 GMT-03:00 Daniel Vetter :
> > On Tue, Apr 01, 2014 at 05:48:15PM -0300, Paulo Zanoni wrote:
> >> 2014-04-01 17:37 GMT-03:00 Daniel Vetter :
> >> > On Tue, Apr 01, 2014 at 02:55:09PM -0300, Paulo Zanoni wrote:
> >> >> From: Pa
On Tue, Apr 01, 2014 at 06:51:39PM +0300, Imre Deak wrote:
> On Fri, 2014-03-07 at 20:12 -0300, Paulo Zanoni wrote:
> > From: Paulo Zanoni
> >
> > This sould be enough.
> >
> > v2: BDW should also run hsw_runtime_resume (Ben).
> >
> > Signed-off-by: Paulo Zanoni
>
> Looks good,
> Reviewed-by:
On Tue, Apr 01, 2014 at 03:37:27PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> We should only enable interrupts at postinstall.
>
> And now on ILK/SNB/IVB/HSW the irq_preinstall and irq_postinstall
> functions leave the hardware in the same state.
>
> Signed-off-by: Paulo Zanoni
> ---
2014-04-01 12:34 GMT-03:00 Imre Deak :
> On Fri, 2014-03-07 at 20:12 -0300, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> Just because I have a SNB machine and I can easily test it.
>>
>> Signed-off-by: Paulo Zanoni
>> ---
>> drivers/gpu/drm/i915/i915_drv.c | 27 +-
On Tue, Apr 01, 2014 at 12:18:24PM -0700, Ben Widawsky wrote:
> On Tue, Apr 01, 2014 at 02:51:27PM +0100, Damien Lespiau wrote:
> > On Tue, Apr 01, 2014 at 02:47:19PM +0100, Mateo Lozano, Oscar wrote:
> > > > > --- a/drivers/gpu/drm/i915/i915_lrc.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_lrc.c
>
2014-04-01 17:52 GMT-03:00 Daniel Vetter :
> On Tue, Apr 01, 2014 at 05:48:15PM -0300, Paulo Zanoni wrote:
>> 2014-04-01 17:37 GMT-03:00 Daniel Vetter :
>> > On Tue, Apr 01, 2014 at 02:55:09PM -0300, Paulo Zanoni wrote:
>> >> From: Paulo Zanoni
>> >>
>> >> ... at edp_have_panel_vdd. Just return fa
2014-03-20 9:58 GMT-03:00 Imre Deak :
> On Fri, 2014-03-07 at 20:12 -0300, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> Now that we don't keep the hotplug interrupts enabled anymore, we can
>> kill the regsave struct and just cal the normal IRQ preinstall,
>> postinstall and uninstall functions
On Tue, Apr 01, 2014 at 05:48:15PM -0300, Paulo Zanoni wrote:
> 2014-04-01 17:37 GMT-03:00 Daniel Vetter :
> > On Tue, Apr 01, 2014 at 02:55:09PM -0300, Paulo Zanoni wrote:
> >> From: Paulo Zanoni
> >>
> >> ... at edp_have_panel_vdd. Just return false, saying we don't have the
> >> panel VDD since
2014-04-01 17:37 GMT-03:00 Daniel Vetter :
> On Tue, Apr 01, 2014 at 02:55:09PM -0300, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> ... at edp_have_panel_vdd. Just return false, saying we don't have the
>> panel VDD since the device is suspended.
>>
>> We started getting WARNs about this proble
On Tue, Apr 01, 2014 at 02:55:06PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Hi
>
> This is a resend of the patches I have that fix the runtime PM WARNs we get
> while running IGT's pm_pc8 test on Haswell.
>
> Right now, runtime PM is completely broken and these patches should put it
On Tue, Apr 01, 2014 at 02:55:09PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> ... at edp_have_panel_vdd. Just return false, saying we don't have the
> panel VDD since the device is suspended.
>
> We started getting WARNs about this problem since the patch that
> started checking if we'r
On Tue, Apr 01, 2014 at 08:11:22PM +0300, Ville Syrjälä wrote:
> On Mon, Mar 31, 2014 at 03:10:44PM +0300, Imre Deak wrote:
> > Atm we reserve/allocate and free the power context during GT power
> > enable/disable time. There is no need to do this, we can reserve/allocate
> > the buffer once during
On Tue, Apr 01, 2014 at 09:50:43PM +0300, Imre Deak wrote:
> On Tue, 2014-04-01 at 19:48 +0200, Daniel Vetter wrote:
> > On Tue, Apr 01, 2014 at 07:55:22PM +0300, Imre Deak wrote:
> > > During resume the intel hda audio driver depends on the i915 driver
> > > reinitializing the audio power domain.
On Tue, Apr 01, 2014 at 02:51:27PM +0100, Damien Lespiau wrote:
> On Tue, Apr 01, 2014 at 02:47:19PM +0100, Mateo Lozano, Oscar wrote:
> > > > --- a/drivers/gpu/drm/i915/i915_lrc.c
> > > > +++ b/drivers/gpu/drm/i915/i915_lrc.c
> > > > @@ -41,7 +41,45 @@
> > > > #include
> > > > #include "i915_dr
On 04/01/2014 12:39 AM, Stephen Rothwell wrote:
> Hi all,
>
> Please do not add material intended for v3.16 to your linux-next included
> branches until after v3.15-rc1 is released.
>
> This tree still fails (more than usual) the powerpc allyesconfig build.
>
> Changes since 20140331:
>
for li
On Tue, 2014-04-01 at 19:48 +0200, Daniel Vetter wrote:
> On Tue, Apr 01, 2014 at 07:55:22PM +0300, Imre Deak wrote:
> > During resume the intel hda audio driver depends on the i915 driver
> > reinitializing the audio power domain. Since the order of calling the
> > i915 resume handler wrt. that of
From: Paulo Zanoni
So we can merge all the common code from postinstall and uninstall.
v2: - Rebase.
- While at it, remove useless { and }.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 27 ---
1 file changed, 8 insertions(+), 19 deletions(-)
d
From: Paulo Zanoni
It should already be masked and disabled and zeroed at the preinstall
and uninstall stages. Also, the current code just writes to IIR once,
and this is not a guarantee that it will be cleared, so it's wrong
anyway.
The whole reason for the paranoia is that we're going to start
From: Paulo Zanoni
This interrupt gets initialized with a different IER value, so it was
not using the macro. The problem is that we plan to modify the macro
to make it do additional things, and we want the SDE interrupts
updated too. So let's make sure we call the macro, then, after it, we
do th
From: Paulo Zanoni
And rename it to GEN5_IRQ_INIT.
We have discussed doing equivalent changes on July 2013, and I even
sent a patch series for this: "[PATCH 00/15] Unify interrupt register
init/reset". Now that the BDW code was merged, I have one more
argument in favor of these changes.
Here's
From: Paulo Zanoni
After the latest changes, ibx_irq_preinstall and ibx_irq_uninstall are
the same, so remove one of the copies and rename the other to
ibx_irq_reset (since we're using the "reset" name for things which are
called both at preinstall and uninstall).
v2: - Rebase.
Signed-off-by: P
From: Paulo Zanoni
Missing from gen8_irq_uninstall.
Reviewed-by: Ben Widawsky
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b69b7b2..ee89a25 100644
-
From: Paulo Zanoni
Just like ibx_irq_preinstall. We'll call this from somewhere else in
the next patch.
Reviewed-by: Ben Widawsky
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/
From: Paulo Zanoni
The IRQ_INIT and IRQ_FINI macros are basically the same thing, with
the exception that IRQ_FINI doesn't properly clear IIR twice and
doesn't have as many POSTING_READs as IRQ_INIT. So rename the INIT
macro to IRQ_RESET and use it everywhere.
v2: - Fix error in the commit messa
From: Paulo Zanoni
The goal is to reuse the GEN8 macros, but a few changes are needed, so
let's make things easier to review.
I could also use these macros on older code, but since I plan to
change how the interrupts are initialized, we'll risk breaking the
older code in the next commits, so I'l
From: Paulo Zanoni
It's the only thing missing, apparently.
v2: - Fix typo (Ben).
Reviewed-by: Ben Widawsky
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
From: Paulo Zanoni
We should only enable interrupts at postinstall.
And now on ILK/SNB/IVB/HSW the irq_preinstall and irq_postinstall
functions leave the hardware in the same state.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 10 --
1 file changed, 4 insertions(+
From: Paulo Zanoni
Same as the _INIT macro: the goal is to reuse the GEN8 macros, but
there are still some slight differences.
v2: - Rebase.
Reviewed-by: Ben Widawsky
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 18 +-
1 file changed, 9 insertions(+), 9 d
From: Paulo Zanoni
The duplicate was at an _uninstall function, so rename it to
gen5_gt_irq_reset.
v2: - Rebase.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/dri
From: Paulo Zanoni
Same as SERR_INT and the other IIR registers: reset on
preinstall/uninstall and WARN for non-zero values at postinstall. This
one also doesn't need double-clear.
v2: - Remove the is_zero assertion (Ben).
Reviewed-by: Ben Widawsky
Signed-off-by: Paulo Zanoni
---
drivers/gpu
From: Paulo Zanoni
To merge the common code of ironlake_irq_preinstall and
ironlake_irq_uninstall.
We should also probably do something about that HSWSTAM write on a
later commit.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 21 +++--
1 file changed, 11 in
From: Paulo Zanoni
After all, we call ibx_irq_preinstall from gen8_irq_preinstall.
v2: - Rebase.
Reviewed-by: Ben Widawsky
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i
From: Paulo Zanoni
And the equivalent GEN8_IRQ_INIT_NDX macro. These macros are for the
postinstall functions. The next patch will improve this macro.
v2: - Adjust to the new POSTING_READ scheme (Ben).
Reviewed-by: Ben Widawsky (v1)
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_i
From: Paulo Zanoni
Hi
This is a follow up to "ILK+ interrupt improvements, v3", which was reveiwed by
Ben.
The biggest difference is that patch 20 was squashed into the previous patch, so
different patches received different chunks of patch 20. This caused the need to
rebase pretty much every p
From: Paulo Zanoni
The SERR_INT register is very similar to the other IIR registers, so
let's zero it at preinstall/uninstall and WARN for a non-zero value at
postinstall, just like we do with the other IIR registers. For this
one, there's no need to double-clear since it can't store more than
on
From: Paulo Zanoni
On the preinstall stage we should just disable all the interrupts, but
we currently enable all the south display interrupts due to the way we
touch SDEIER at the IRQ handlers (note: they are still masked and our
IRQ handler is disabled). Instead of doing that, let's make the
pr
From: Paulo Zanoni
To avoid WARNs when we call it.
Testcase: igt/pm_pc8/reg-read-ioctl
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75693
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_uncore.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git
From: Paulo Zanoni
Hi
This is a resend of the patches I have that fix the runtime PM WARNs we get
while running IGT's pm_pc8 test on Haswell.
Right now, runtime PM is completely broken and these patches should put it back
to the state where it was before. The issue fixed by the first patch comp
From: Paulo Zanoni
If runtime PM is enabled and we unset all modes, we will runtime
suspend after __intel_set_mode() , then function
intel_modeset_check_state() will try to read the HW state while it is
suspended and trigger lots of WARNs because it shouldn't be reading
registers.
So on this pat
From: Paulo Zanoni
At i915_display_info, don't call cursor_position() for a disabled
CRTC, since the CRTC may be on a powered down pipe, and this will
cause "Unclaimed register before interrupt" error messages.
Testcase: igt/pm_pc8/debugfs-read
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i
From: Paulo Zanoni
... at edp_have_panel_vdd. Just return false, saying we don't have the
panel VDD since the device is suspended.
We started getting WARNs about this problem since the patch that
started checking if we're suspended while reading registers.
Testcase: igt/pm_pc8
Signed-off-by: Pa
From: Paulo Zanoni
Otherwise we may get some WARNs complaining that we're reading a
register while we're suspended.
Testcase: igt/pm_pc8/debugfs-read
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/
From: Paulo Zanoni
So far force_wake_timer was only used by gen6_gt_force_wake_put. Since
we always had balanced gen6_gt_force_wake_get/put calls, we could
guarantee balanced calls to intel_runtime_pm_get/put.
Commit 8232644ccf099548710843e97360a3fcd6d28e04, "drm/i915: Convert
the forcewake work
From: Paulo Zanoni
Because gen6_gt_force_wake_{get,put} should already be responsible for
getting/putting runtime PM. If we keep these calls, debugfs will not
be testing the get/put calls of the forcewake functions.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 --
1
On Tue, Apr 01, 2014 at 07:55:22PM +0300, Imre Deak wrote:
> During resume the intel hda audio driver depends on the i915 driver
> reinitializing the audio power domain. Since the order of calling the
> i915 resume handler wrt. that of the audio driver is not guaranteed,
> move the power domain rei
On Tue, Apr 01, 2014 at 09:07:50PM +0530, Vandana Kannan wrote:
> Populate PAR in infoframe structure. PAR is taken from CEA mode list if
> VIC is found. Else, PAR is NONE as per initialization.
>
> v2: Removed the part which sets PAR according to user input, based on
> Daniel's review comments.
>
On Mon, Mar 31, 2014 at 03:10:44PM +0300, Imre Deak wrote:
> Atm we reserve/allocate and free the power context during GT power
> enable/disable time. There is no need to do this, we can reserve/allocate
> the buffer once during driver loading and free it during driver cleanup.
> The re-reservation
On Tue, Apr 01, 2014 at 04:04:44PM +0300, Jani Nikula wrote:
> On Fri, 28 Mar 2014, Vandana Kannan wrote:
> > From: Pradeep Bhat
> >
> > This patch reads the DRRS support and Mode type from VBT fields.
> > The read information will be stored in VBT struct during BIOS
> > parsing. The above functi
On Tue, Apr 01, 2014 at 07:52:21PM +0530, Vandana Kannan wrote:
> Populate PAR in infoframe structure. If there is a user setting for PAR, then
> that value is set. Else, value is taken from CEA mode list if VIC is found.
> Else, PAR is calculated from resolution. If none of these conditions are
>
During resume the intel hda audio driver depends on the i915 driver
reinitializing the audio power domain. Since the order of calling the
i915 resume handler wrt. that of the audio driver is not guaranteed,
move the power domain reinitialization step to the resume_early
handler. This is guaranteed
On Tue, Apr 1, 2014 at 2:42 PM, Chris Wilson wrote:
> On Tue, Apr 01, 2014 at 09:32:50AM -0300, Paulo Zanoni wrote:
>> 2014-04-01 5:14 GMT-03:00 Chris Wilson :
>> > On Mon, Mar 31, 2014 at 08:59:29PM +0200, Daniel Vetter wrote:
>> >> On that topic, qa has finally found the drv_suspend/forcewake is
On Fri, 2014-03-07 at 20:12 -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Hi
>
> This series depends on:
> - [PATCH 0/6] More runtime PM fixes
> - [PATCH 00/16] Merge PC8 with runtime PM, v3
> - [PATCH 00/20] ILK+ interrupt improvements, v2
>
> Patches 1 and 2 are the last pieces of my
On Tue, 01 Apr 2014 11:08:13 +0300
Jani Nikula wrote:
> On Mon, 31 Mar 2014, Jesse Barnes wrote:
> > Going below the minimum value may affect the BLC_EN line, so try to use
> > the VBT provided minimum where possible, otherwise use an experimentally
> > derived value to prevent the panel from co
On Tue, 01 Apr 2014 12:27:43 +0300
Jani Nikula wrote:
> On Tue, 01 Apr 2014, Jani Nikula wrote:
> > On Mon, 31 Mar 2014, Jesse Barnes wrote:
> >> To make sure we properly follow the enable/disable sequences.
> >>
> >> Signed-off-by: Jesse Barnes
> >> ---
> >> drivers/gpu/drm/i915/intel_dp.c
On Tue, 01 Apr 2014 10:19:29 +0300
Jani Nikula wrote:
> On Mon, 31 Mar 2014, Jesse Barnes wrote:
> > To make sure we properly follow the enable/disable sequences.
> >
> > Signed-off-by: Jesse Barnes
> > ---
> > drivers/gpu/drm/i915/intel_dp.c| 62
> > --
Broadwell is perfectly capable of full PPGTT. I've been using it for
some time, and seen no especially ill effects.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/
On Fri, 2014-03-07 at 20:12 -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> This sould be enough.
>
> v2: BDW should also run hsw_runtime_resume (Ben).
>
> Signed-off-by: Paulo Zanoni
Looks good,
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/i915_drv.c | 8 ++--
> drivers/gpu
On Fri, 2014-03-07 at 20:12 -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> That's what the spec said! And HSW needs it through pcode (you can
> only read it through MCHBAR), so create hsw_write_dcomp to abstract
> the weirdness.
>
> Signed-off-by: Paulo Zanoni
Reviewed-by: Imre Deak
> -
On Fri, 2014-03-07 at 20:12 -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Just because I have a SNB machine and I can easily test it.
>
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/i915_drv.c | 27 +--
> drivers/gpu/drm/i915/i915_drv.h | 2
Populate PAR in infoframe structure. PAR is taken from CEA mode list if
VIC is found. Else, PAR is NONE as per initialization.
v2: Removed the part which sets PAR according to user input, based on
Daniel's review comments.
v3: Removed calculation of PAR for non-CEA modes as per discussion with
Vi
Populate PAR in infoframe structure. If there is a user setting for PAR, then
that value is set. Else, value is taken from CEA mode list if VIC is found.
Else, PAR is calculated from resolution. If none of these conditions are
satisfied, PAR is NONE as per initialization.
v2: Removed the part whic
On Tue, Apr 01, 2014 at 06:43:42PM +0530, Vandana Kannan wrote:
> On Apr-01-2014 5:04 PM, Ville Syrjälä wrote:
> > On Tue, Apr 01, 2014 at 04:26:59PM +0530, Vandana Kannan wrote:
> >> Populate PAR in infoframe structure. If there is a user setting for PAR,
> >> then
> >> that value is set. Else, v
On Tue, Apr 01, 2014 at 02:47:19PM +0100, Mateo Lozano, Oscar wrote:
> > > --- a/drivers/gpu/drm/i915/i915_lrc.c
> > > +++ b/drivers/gpu/drm/i915/i915_lrc.c
> > > @@ -41,7 +41,45 @@
> > > #include
> > > #include "i915_drv.h"
> > >
> > > +#define GEN8_LR_CONTEXT_SIZE (21 * PAGE_SIZE)
> >
> > I'm
> > --- a/drivers/gpu/drm/i915/i915_lrc.c
> > +++ b/drivers/gpu/drm/i915/i915_lrc.c
> > @@ -41,7 +41,45 @@
> > #include
> > #include "i915_drv.h"
> >
> > +#define GEN8_LR_CONTEXT_SIZE (21 * PAGE_SIZE)
>
> I'm a bit puzzled by that number:
> - I found a sentence saying: "the Context Image for
Bummer. I´ll fix it on the next version.
Thanks!
Oscar
> -Original Message-
> From: Lespiau, Damien
> Sent: Monday, March 31, 2014 5:43 PM
> To: Mateo Lozano, Oscar
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 39/49] drm/i915/bdw: Swap the PPGTT PDPs,
> LRC sty
On Fri, 28 Mar 2014, Vandana Kannan wrote:
> Definition of VLV RR switch bit and corresponding toggling in
> set_drrs function.
Reviewed-by: Jani Nikula
> Signed-off-by: Vandana Kannan
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/i915_reg.h |1 +
> drivers/gpu/drm/i915/intel
On Fri, 28 Mar 2014, Vandana Kannan wrote:
> For Broadwell, there is one instance of Transcoder MN values per transcoder.
> For dynamic switching between multiple refreshr rates, M/N values may be
> reprogrammed on the fly. Link N programming triggers update of all data and
> link M & N registers
On Fri, 28 Mar 2014, Vandana Kannan wrote:
> Adding support to detect display idleness by tracking page flip from
> user space. Switch to low refresh rate is triggered after 2 seconds of
> idleness. The delay is configurable. If there is a page flip or call to
> update the plane, then high refresh
You are right on the money: it looks like I am missing the "Force Posted" bit.
I´ll add in the next patch series version.
Thanks,
Oscar
> -Original Message-
> From: Lespiau, Damien
> Sent: Tuesday, April 01, 2014 1:01 AM
> To: Mateo Lozano, Oscar
> Cc: intel-gfx@lists.freedesktop.org; Be
On Fri, 28 Mar 2014, Vandana Kannan wrote:
> From: Pradeep Bhat
>
> This patch computes and stored 2nd M/N/TU for switching to different
> refresh rate dynamically. PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle
> between alternate refresh rates programmed in 2nd M/N/TU registers.
>
> v2: Daniel's
On Fri, 28 Mar 2014, Vandana Kannan wrote:
> From: Pradeep Bhat
>
> This patch and finds out the lowest refresh rate supported for the resolution
> same as the fixed_mode.
> It also checks the VBT fields to see if panel supports seamless DRRS or not.
> Based on above data it marks whether eDP pan
On Apr-01-2014 5:04 PM, Ville Syrjälä wrote:
> On Tue, Apr 01, 2014 at 04:26:59PM +0530, Vandana Kannan wrote:
>> Populate PAR in infoframe structure. If there is a user setting for PAR, then
>> that value is set. Else, value is taken from CEA mode list if VIC is found.
>> Else, PAR is calculated f
On Fri, 28 Mar 2014, Vandana Kannan wrote:
> From: Pradeep Bhat
>
> This patch reads the DRRS support and Mode type from VBT fields.
> The read information will be stored in VBT struct during BIOS
> parsing. The above functionality is needed for decision making
> whether DRRS feature is supported
On Tue, Apr 01, 2014 at 09:32:50AM -0300, Paulo Zanoni wrote:
> 2014-04-01 5:14 GMT-03:00 Chris Wilson :
> > On Mon, Mar 31, 2014 at 08:59:29PM +0200, Daniel Vetter wrote:
> >> On that topic, qa has finally found the drv_suspend/forcewake issue. Chris
> >> can you please pick out the minimal fix fo
2014-04-01 5:14 GMT-03:00 Chris Wilson :
> On Mon, Mar 31, 2014 at 08:59:29PM +0200, Daniel Vetter wrote:
>> On that topic, qa has finally found the drv_suspend/forcewake issue. Chris
>> can you please pick out the minimal fix for that out of your tree? Maybe
>> on top of Paulo's fixes so that I do
On Tue, Apr 01, 2014 at 04:26:59PM +0530, Vandana Kannan wrote:
> Populate PAR in infoframe structure. If there is a user setting for PAR, then
> that value is set. Else, value is taken from CEA mode list if VIC is found.
> Else, PAR is calculated from resolution. If none of these conditions are
>
On 2014-03-31 10:05 (GMT+0200) Janus composed:
I have the same problem as the one described by Michael bellow: the
Intel Graphic card produces eye strain and headache after some minutes
of using it. I found a lot of people complaining on the same problem,
but no solution. I tried lowering the re
On Mon, Mar 24, 2014 at 11:00:06PM +0530, sourab.gu...@intel.com wrote:
> From: Akash Goel
>
> In Valleyview, Operational flush cannot be enabled on
> BWG A0 [Errata BWT006]
Apparently this has been busted ever since gen4. So I think either we
should disable it for all gen4+ platforms or we shou
1 - 100 of 123 matches
Mail list logo
