On Fri, 28 Mar 2014, Vandana Kannan <vandana.kan...@intel.com> wrote:
> For Broadwell, there is one instance of Transcoder MN values per transcoder.
> For dynamic switching between multiple refreshr rates, M/N values may be
> reprogrammed on the fly. Link N programming triggers update of all data and
> link M & N registers and the new M/N values will be used in the next frame
> that is output.
>
> v2: Incorporated Chris's review comments
> Changed to check for gen >=8 or gen > 5 before setting M/N registers
>
> v3: Incorporated Jani's review comments
> Re-use cpu_transcoder_set_m_n for BDW.
Reviewed-by: Jani Nikula <jani.nik...@intel.com>
>
> Signed-off-by: Vandana Kannan <vandana.kan...@intel.com>
> Signed-off-by: Pradeep Bhat <pradeep.b...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/i915/intel_dp.c | 25 +++++++++++++++++++------
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 3 files changed, 22 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index c309561..f492b51 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5120,7 +5120,7 @@ static void intel_pch_transcoder_set_m_n(struct
> intel_crtc *crtc,
> I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
> }
>
> -static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> +void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> struct intel_link_m_n *m_n)
> {
> struct drm_device *dev = crtc->base.dev;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 4f0281a..6cdbb38 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -743,11 +743,15 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct
> intel_link_m_n *m_n)
> struct drm_i915_private *dev_priv = dev->dev_private;
> enum transcoder transcoder = crtc->config.cpu_transcoder;
>
> - I915_WRITE(PIPE_DATA_M2(transcoder),
> - TU_SIZE(m_n->tu) | m_n->gmch_m);
> - I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
> - I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
> - I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
> + if (INTEL_INFO(dev)->gen >= 8) {
> + intel_cpu_transcoder_set_m_n(crtc, m_n);
> + } else if (INTEL_INFO(dev)->gen > 6) {
> + I915_WRITE(PIPE_DATA_M2(transcoder),
> + TU_SIZE(m_n->tu) | m_n->gmch_m);
> + I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
> + I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
> + I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
> + }
> }
>
> bool
> @@ -3704,7 +3708,16 @@ void intel_dp_set_drrs_state(struct drm_device *dev,
> int refresh_rate)
> return;
> }
>
> - if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
> + if (INTEL_INFO(dev)->gen >= 8) {
> + switch (index) {
> + case DRRS_HIGH_RR:
> + intel_dp_set_m2_n2(intel_crtc, &config->dp_m_n);
> + break;
> + case DRRS_LOW_RR:
> + intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
> + break;
> + };
> + } else if (INTEL_INFO(dev)->gen > 6) {
> reg = PIPECONF(intel_crtc->config.cpu_transcoder);
> val = I915_READ(reg);
> if (index > DRRS_HIGH_RR) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 570cc47..e4b479e 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -770,6 +770,8 @@ int valleyview_get_vco(struct drm_i915_private *dev_priv);
> void intel_mode_from_pipe_config(struct drm_display_mode *mode,
> struct intel_crtc_config *pipe_config);
> int intel_format_to_fourcc(int format);
> +void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> + struct intel_link_m_n *m_n);
>
> /* intel_dp.c */
> void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
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