On Sat, Jun 01, 2013 at 07:45:56PM +0200, Daniel Vetter wrote:
> We always limited the link bw calculations to 24bpp. Tested with
> my shiny new high-bpc screen, seems to work as advertised.
>
> Signed-off-by: Daniel Vetter
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65280
Tested-by:
On Thu, Jun 06, 2013 at 10:45:42AM +0100, Chris Wilson wrote:
> After kicking a ring, it should be free to make progress again and so
> should not be accused of being stuck until hangcheck fires once more. In
> order to catch a denial-of-service within a batch or across multiple
> batches, we still
On Thu, Jun 06, 2013 at 02:51:37PM +0100, Chris Wilson wrote:
> On Thu, Jun 06, 2013 at 02:55:52PM +0200, Daniel Vetter wrote:
> > For various reasons the hw state readout might not be able to
> > faithfully match the hw state:
> > - broken hw (like the case which motivated this patch here where th
Nowadays (i.e. with Valleyview) we also have edp on non-PCH_SPLIT
platforms, so just checking for LVDS is not good enough.
Secondly we have full pfit pipe config tracking, so we'll correctly
disable the pfit as part of the initial modeset.
For fastboot we need a bit of work here to correctly kill
WaFbcNukeOn3DBlt for IVB, HSW.
According BSPec: "Workaround: Do not enable Render Command Streamer tracking
for FBC.
Instead insert a LRI to address 0x50380 with data 0x0004 after the
PIPE_CONTROL that
follows each render submission."
v2: Chris noticed that flush_domains check was missing h
WaFbcNukeOn3DBlt for IVB, HSW.
According BSPec: "Workaround: Do not enable Render Command Streamer tracking
for FBC.
Instead insert a LRI to address 0x50380 with data 0x0004 after the
PIPE_CONTROL that
follows each render submission."
v2: Chris noticed that flush_domains check was missing h
From: Chris Wilson
This is required for tracking render damage for use with FBC and will be
used in subsequent patches.
Signed-off-by: Chris Wilson
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 13 +
From: Chris Wilson
This is required for tracking render damage for use with FBC and will be
used in subsequent patches.
Signed-off-by: Chris Wilson
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 13 +
On Thu, Jun 06, 2013 at 06:30:52PM +0200, Egbert Eich wrote:
> On Tue, May 21, 2013 at 05:17:27PM +0200, Egbert Eich wrote:
> > On Wed, May 08, 2013 at 12:50:24PM +0300, ville.syrj...@linux.intel.com
> > wrote:
> > > From: Ville Syrjälä
> > >
> > > Follow the same sequence when enabling the curs
On Tue, May 21, 2013 at 05:17:27PM +0200, Egbert Eich wrote:
> On Wed, May 08, 2013 at 12:50:24PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Follow the same sequence when enabling the cursor plane during
> > modeset. No point in doing this stuff in different order
On Thu, May 30, 2013 at 10:07:07PM +0800, Wang Xingchao wrote:
> Hi all,
>
>This is V7 and here're some changes notes:
>change from V6-->V7:
>- rename variable
>- use HAS_POWER_WELL instead of IS_HASWELL
>- put structure inside drm_i915_private
>- use WARN_ON for global poi
please just ignore this version...
going to try fbc_dirty and other changes here...
On Thu, Jun 6, 2013 at 12:00 PM, Chris Wilson wrote:
> On Thu, Jun 06, 2013 at 11:49:56AM -0300, Rodrigo Vivi wrote:
>> WaFbcNukeOn3DBlt for IVB, HSW.
>>
>> According BSPec: "Workaround: Do not enable Render Comma
On Thu, Jun 06, 2013 at 11:49:56AM -0300, Rodrigo Vivi wrote:
> WaFbcNukeOn3DBlt for IVB, HSW.
>
> According BSPec: "Workaround: Do not enable Render Command Streamer tracking
> for FBC.
> Instead insert a LRI to address 0x50380 with data 0x0004 after the
> PIPE_CONTROL that
> follows each r
WaFbcNukeOn3DBlt for IVB, HSW.
According BSPec: "Workaround: Do not enable Render Command Streamer tracking
for FBC.
Instead insert a LRI to address 0x50380 with data 0x0004 after the
PIPE_CONTROL that
follows each render submission."
v2: Chris noticed that flush_domains check was missing h
On Thu, Jun 06, 2013 at 11:35:15AM -0300, Paulo Zanoni wrote:
> 2013/6/6 Ville Syrjälä :
> > On Wed, Jun 05, 2013 at 06:05:51PM -0300, Paulo Zanoni wrote:
> >> From: Paulo Zanoni
> >>
> >> So add a power domain and check for it before we try to read
> >> VGA_CONTROL.
> >>
> >> This fixes unclaimed
Chris Wilson writes:
> After kicking a ring, it should be free to make progress again and so
> should not be accused of being stuck until hangcheck fires once more. In
> order to catch a denial-of-service within a batch or across multiple
> batches, we still do increment the hangcheck score - jus
As getting error state doesn't anymore require big kmallocs,
make error state accessible also from sysfs.
v2: - error state clearing (Chris Wilson)
- user hint, proper access mode bits and name (Daniel Vetter)
v3: release resources in proper order (Chris Wilson)
Suggested-by: Daniel Vetter
2013/6/6 Ville Syrjälä :
> On Wed, Jun 05, 2013 at 06:05:51PM -0300, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> So add a power domain and check for it before we try to read
>> VGA_CONTROL.
>>
>> This fixes unclaimed register messages that happen on suspend/resume.
>>
>> Signed-off-by: Paulo Z
On Thu, Jun 06, 2013 at 04:53:01PM +0300, Jani Nikula wrote:
> Hi Greg, Andrew -
>
> Patch 1 is for DMI, bugfixes in patches 2-3 for i915 and included for
> completeness. After a tested-by they should be good for stable. I'll
> leave it to Daniel to sort out how the last two get in.
I'd prefer al
With Greg's address fixed. Please drop the old one from any
replies. Sorry for the noise.
On Thu, 06 Jun 2013, Jani Nikula wrote:
> Hi Greg, Andrew -
>
> Patch 1 is for DMI, bugfixes in patches 2-3 for i915 and included for
> completeness. After a tested-by they should be good for stable. I'll
>
This replaceable mainboard only has a VGA-out, yet it claims to also
have a connected LVDS header.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65256
Reported-by: Cornel Panceac
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_lvds.c |8
1 file changed, 8 inserti
dmi_match() considers a substring match to be a successful match. This
is not always sufficient to distinguish between DMI data for different
systems. Add support for exact string matching using strcmp() in
addition to the substring matching using strstr().
The specific use case in the i915 driver
From: Chris Wilson
This replaceable mainboard only has a VGA-out, yet it claims to also
have a connected LVDS header.
Reported-by: annndd...@gmail.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63860
Signed-off-by: Chris Wilson
[Jani: Use DMI_EXACT_MATCH for board name.]
Signed-off-
Hi Greg, Andrew -
Patch 1 is for DMI, bugfixes in patches 2-3 for i915 and included for
completeness. After a tested-by they should be good for stable. I'll
leave it to Daniel to sort out how the last two get in.
BR,
Jani.
Chris Wilson (1):
drm/i915: Quirk away phantom LVDS on Intel's D510MO m
On Thu, Jun 06, 2013 at 02:55:52PM +0200, Daniel Vetter wrote:
> For various reasons the hw state readout might not be able to
> faithfully match the hw state:
> - broken hw (like the case which motivated this patch here where the
> sdvo encoder does not implemented mandatory functionality
> co
On Thu, Jun 06, 2013 at 04:33:06PM +0300, Mika Kuoppala wrote:
> As getting error state doesn't anymore require big kmallocs,
> make error state accessible also from sysfs.
>
> v2: - error state clearing (Chris Wilson)
> - user hint, proper access mode bits and name (Daniel Vetter)
>
> Sugges
As getting error state doesn't anymore require big kmallocs,
make error state accessible also from sysfs.
v2: - error state clearing (Chris Wilson)
- user hint, proper access mode bits and name (Daniel Vetter)
Suggested-by: Daniel Vetter
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i91
On Tue, Jun 04, 2013 at 04:53:39PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> CTG/ILK/SNB/IVB support 4kx2k surfaces. HSW supports 4kx4k, but
> without proper front buffer invalidation on the last 2k lines, so
> don't enable FBC on these cases for now.
>
> v2: Use gen >= 5, not gen > 4
For various reasons the hw state readout might not be able to
faithfully match the hw state:
- broken hw (like the case which motivated this patch here where the
sdvo encoder does not implemented mandatory functionality
correctly).
- platforms which are not supported fully with the pipe config
On Thu, Jun 06, 2013 at 02:50:15PM +0300, Imre Deak wrote:
> On Thu, 2013-06-06 at 12:45 +0200, Daniel Vetter wrote:
> > Incomplete since ilk+ support needs proper pch dpll tracking first.
> > SDVO get_config parts based on a patch from Jesse Barnes, but fixed up
> > to actually work.
> >
> > v2:
Release 2.21.9 (2013-06-06)
===
Consolidating the copy-on-write support, hopefully cleaning up the last of
the regressions.
* Restore vsync on textured videos.
[regression from 2.21.8]
https://bugs.freedesktop.org/show_bug.cgi?id=65048
* Fix incorrect ordering of p
On Thu, Jun 6, 2013 at 3:49 AM, Chris Wilson wrote:
> On Thu, Jun 06, 2013 at 12:17:26AM +0200, Daniel Vetter wrote:
>> On some chipset we try to avoid possibly invasive output detection
>> methods (like load detect which can cause flickering elsewhere) in the
>> output poll work. Drivers could he
On Thu, Jun 06, 2013 at 03:18:42PM +0300, Mika Kuoppala wrote:
> As getting error state doesn't anymore require big kmallocs,
> make error state accessible also from sysfs.
>
> Suggested-by: Daniel Vetter
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_sysfs.c | 49
> +++
On Thu, Jun 06, 2013 at 03:18:42PM +0300, Mika Kuoppala wrote:
> As getting error state doesn't anymore require big kmallocs,
> make error state accessible also from sysfs.
>
> Suggested-by: Daniel Vetter
> Signed-off-by: Mika Kuoppala
Don't forget the ability to clear an error-state in order t
Make function for struct i915_error_state_buf initialization
and export it, for sysfs and debugfs.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_debugfs.c | 50 +--
drivers/gpu/drm/i915/i915_drv.h |7 +
2 files changed, 37 insertions(+),
In preparation for sysfs error state access,
export ref error state ref counting interface.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_debugfs.c | 31 ++-
drivers/gpu/drm/i915/i915_drv.h |3 +++
2 files changed, 25 insertions(+), 9 deletions(
As getting error state doesn't anymore require big kmallocs,
make error state accessible also from sysfs.
Suggested-by: Daniel Vetter
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_sysfs.c | 49 +
1 file changed, 49 insertions(+)
diff --git a/d
In preparation for accessing error state from sysfs, export
error state to string conversion function. Also tuck buffer
error handling inside the function.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_debugfs.c | 24
drivers/gpu/drm/i915/i915_drv.h |
On Wed, Jun 05, 2013 at 10:58:06PM +0300, Ville Syrjälä wrote:
> On Wed, Jun 05, 2013 at 04:41:54PM -0300, Rodrigo Vivi wrote:
> > why is this needed?
>
> The spec says that on some hardware you need to PLL running before you
> can poke at the palette registers. I didn't actually try to anger the
On Wed, Jun 05, 2013 at 04:39:58PM -0300, Rodrigo Vivi wrote:
> Reviewed-by: Rodrigo Vivi
>
> On Tue, Jun 4, 2013 at 7:49 AM, wrote:
> > From: Ville Syrjälä
> >
> > Make assert_sprites_disabled() operational on all platforms where
> > we currently have sprite support enabled.
> >
> > Signed-of
On Thu, 2013-06-06 at 12:45 +0200, Daniel Vetter wrote:
> Incomplete since ilk+ support needs proper pch dpll tracking first.
> SDVO get_config parts based on a patch from Jesse Barnes, but fixed up
> to actually work.
>
> v2: Make sure that we call encoder->get_config _after_ we
> get_pipe_config
On Wed, Jun 05, 2013 at 02:21:51PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> So we can remove some duplicate code. All the PCHs are very similar
> and right now the code is the same. I plan to add more code, so we
> would have more duplicated code.
>
> Signed-off-by: Paulo Zanoni
Que
On Thu, Jun 06, 2013 at 01:09:32PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> We use port I/O for VGA register access, so adding display_mmio_offset
> is just wrong.
>
> This reverts commit 56a12a509296c87d6f149be86c6694d312b21d35.
>
> Signed-off-by: Ville Syrjälä
Q
Incomplete since ilk+ support needs proper pch dpll tracking first.
SDVO get_config parts based on a patch from Jesse Barnes, but fixed up
to actually work.
v2: Make sure that we call encoder->get_config _after_ we
get_pipe_config to be consistent in both setup_hw_state and the
modeset state check
On Wed, 2013-06-05 at 15:28 -0300, Rodrigo Vivi wrote:
> nice tests, only now I understood why Daniel "randomly" volunteered me
> to review this series ;)
> Reviewed-by: Rodrigo Vivi
Thanks for the review, the patchset is pushed now to igt.
--Imre
__
From: Ville Syrjälä
We use port I/O for VGA register access, so adding display_mmio_offset
is just wrong.
This reverts commit 56a12a509296c87d6f149be86c6694d312b21d35.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 10 ++
1 file changed, 2 insertions(+), 8 deletion
After kicking a ring, it should be free to make progress again and so
should not be accused of being stuck until hangcheck fires once more. In
order to catch a denial-of-service within a batch or across multiple
batches, we still do increment the hangcheck score - just not as
severely so that it ta
If we detect a ring is in a valid wait for another, just let it be.
Eventually it will either begin to progress again, or the entire system
will come grinding to a halt and then hangcheck will fire as soon as the
deadlock is detected.
This error was foretold by Ben in
commit 05407ff889ceebe383aa59
On Tue, Jun 04, 2013 at 04:24:48PM -0700, Ben Widawsky wrote:
> On Tue, Jun 04, 2013 at 11:49:08PM +0100, Chris Wilson wrote:
> > By stashing a pointer of who opened the device and keeping a list of
> > open fd, we can then walk each client and inspect how many objects they
> > have open. For examp
On Wed, Jun 05, 2013 at 06:05:51PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> So add a power domain and check for it before we try to read
> VGA_CONTROL.
>
> This fixes unclaimed register messages that happen on suspend/resume.
>
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/
After kicking a ring, it should be free to make progress again and so
should not be accused of being stuck until hangcheck fires once more.
This should address part of Ben's justified criticism of
commit 05407ff889ceebe383aa5907219f86582ef96b72
Author: Mika Kuoppala
Date: Thu May 30 09:04:29 2
If we detect a ring is in a valid wait for another, just let it be.
Eventually it will either begin to progress again, or the entire system
will come grinding to a halt and then hangcheck will fire as soon as the
deadlock is detected.
This error was foretold by Ben in
commit 05407ff889ceebe383aa59
No need to call the ->pre_pll_enable hook twice if we don't enable the
dpll too early. This should make Jani a bit less grumpy.
v2: Rebase on top of the newly-colored BUG_ONs.
Cc: Jani Nikula
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_display.c | 45 +++
Now that we have the proper pipe config to track this, we don't need
to write any registers any more.
v2: Drop a few now unnecessary local variables and switch the enable
function to take a struct intel_crtc * to simply arguments.
v3: Rebase on top of the newly-colored BUG_ON.
Cc: Jani Nikula
S
On Thu, Jun 6, 2013 at 9:49 AM, Chris Wilson wrote:
> On Thu, Jun 06, 2013 at 12:17:26AM +0200, Daniel Vetter wrote:
>> On some chipset we try to avoid possibly invasive output detection
>> methods (like load detect which can cause flickering elsewhere) in the
>> output poll work. Drivers could he
On Thu, Jun 06, 2013 at 12:17:26AM +0200, Daniel Vetter wrote:
> On some chipset we try to avoid possibly invasive output detection
> methods (like load detect which can cause flickering elsewhere) in the
> output poll work. Drivers could hence return unknown when a previous
> full ->detect call re
On Thu, Jun 06, 2013 at 07:49:49AM +0100, Chris Wilson wrote:
> On Wed, Jun 05, 2013 at 02:21:56PM -0300, Paulo Zanoni wrote:
> > From: Paulo Zanoni
> >
> > This patch implements "Display Sequences for Package C8", from the
> > "Display Mode Set Sequence" section from the Haswell documentation.
>
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