At DDX commit Chris mentioned the tendency we have of finding out more
PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
This patch also fix GT3 names. I'no not sending in separated patche because
names are only in few comments and not in variable names.
v2: Fix some mobi
On 05/13/2013 01:53 PM, Rodrigo Vivi wrote:
Signed-off-by: Rodrigo Vivi
---
src/mesa/drivers/dri/intel/intel_chipset.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h
b/src/mesa/drivers/dri/intel/intel_chipset.h
index df025ac
On 05/13/2013 01:53 PM, Rodrigo Vivi wrote:
At DDX commit Chris mentioned the tendency we have of finding out more
PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
References: http://bugs.freedesktop.org/show_bug.cgi?id=63701
Signed-off-by: Rodrigo Vivi
Paulo sent me
Hi
2013/5/13 Rodrigo Vivi :
> At DDX commit Chris mentioned the tendency we have of finding out more
> PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
>
> This patch also fix GT3 names. I'no not sending in separated patche because
> names are only in few comments and not
good question. I'm going to check that.
Please accept this add "reserved" ids patch for now. I send more
patches above this with market names if I find out the correct
association.
On Mon, May 13, 2013 at 6:39 PM, Chris Wilson wrote:
> On Mon, May 13, 2013 at 05:56:29PM -0300, Rodrigo Vivi wrote
On Mon, May 13, 2013 at 05:56:29PM -0300, Rodrigo Vivi wrote:
> When publishing first HSW ids we weren't allowed to use "GT3" codname.
> But this is the correct codname and Mesa is using it already.
> So to avoid people getting confused why in Mesa it is called GT3 and here
> it is called GT2_PLUS
As Chris mentioned there is a tendency we finding out more
PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
I didn't have better names for this reserved ids and didn't want to use rsvd1
and rsvd2 groups, so I decided to use "B" and "E" that stands for the latest
id digit.
When publishing first HSW ids we weren't allowed to use "GT3" codname.
But this is the correct codname and Mesa is using it already.
So to avoid people getting confused why in Mesa it is called GT3 and here
it is called GT2_PLUS let's fix this name in a standard and correct way.
Signed-off-by: Rod
At DDX commit Chris mentioned the tendency we have of finding out more
PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
References: http://bugs.freedesktop.org/show_bug.cgi?id=63701
Signed-off-by: Rodrigo Vivi
---
lib/intel_chipset.h | 55 +++
When publishing first HSW ids we weren't allowed to use "GT3" codname.
But this is the correct codname and Mesa is using it already.
So to avoid people getting confused why in Mesa it is called GT3 and here
it is called GT2_PLUS let's fix this name in a standard and correct way.
Signed-off-by: Rod
At DDX commit Chris mentioned the tendency we have of finding out more
PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
References: http://bugs.freedesktop.org/show_bug.cgi?id=63701
Signed-off-by: Rodrigo Vivi
---
include/pci_ids/i965_pci_ids.h | 24
Signed-off-by: Rodrigo Vivi
---
src/mesa/drivers/dri/intel/intel_chipset.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h
b/src/mesa/drivers/dri/intel/intel_chipset.h
index df025ac..ee735bb 100644
--- a/src/mesa/drivers/dri/inte
At DDX commit Chris mentioned the tendency we have of finding out more
PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
References: http://bugs.freedesktop.org/show_bug.cgi?id=63701
Signed-off-by: Rodrigo Vivi
---
intel/intel_chipset.h | 54 +
When publishing first HSW ids we weren't allowed to use "GT3" codname.
But this is the correct codname and Mesa is using it already.
So to avoid people getting confused why in Mesa it is called GT3 and here
it is called GT2_PLUS let's fix this name in a standard and correct way.
Signed-off-by: Rod
At DDX commit Chris mentioned the tendency we have of finding out more
PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
This patch also fix GT3 names. I'no not sending in separated patche because
names are only in few comments and not in variable names.
References: http:
From: Paulo Zanoni
It just prints whether it's supported/enabled/disabled. Feature
requested by the power management team.
Requested-by: Kristen Accardi
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_debugfs.c | 20
1 file changed, 20 insertions(+)
diff --gi
From: Paulo Zanoni
IPS is still enabled by default. Feature requested by the power
management team.
This should also help testing the feature on some early pre-production
hardware where there were relationship problems between IPS and PSR.
Requested-by: Kristen Accardi
Signed-off-by: Paulo Zan
From: Paulo Zanoni
Intermediate Pixel Storage is a feature that should reduce the number
of times the display engine wakes up memory to read pixels, so it
should allow deeper PC states. IPS can only be enabled on ULT port A
with 8:8:8 pipe pixel formats.
With eDP 1920x1080 and correct watermarks
On 05/13/2013 03:50 PM, Wang, Xingchao wrote:
-Original Message-
From: David Henningsson [mailto:david.hennings...@canonical.com]
Sent: Monday, May 13, 2013 8:13 PM
To: Wang, Xingchao
Cc: Wang Xingchao; alsa-de...@alsa-project.org; dan...@ffwll.ch;
ti...@suse.de; Lin, Mengdong; intel-gfx@
> -Original Message-
> From: David Henningsson [mailto:david.hennings...@canonical.com]
> Sent: Monday, May 13, 2013 8:13 PM
> To: Wang, Xingchao
> Cc: Wang Xingchao; alsa-de...@alsa-project.org; dan...@ffwll.ch;
> ti...@suse.de; Lin, Mengdong; intel-gfx@lists.freedesktop.org; Li, Jocelyn;
Hi Takashi,
> -Original Message-
> From: Takashi Iwai [mailto:ti...@suse.de]
> Sent: Monday, May 13, 2013 8:17 PM
> To: Wang, Xingchao
> Cc: David Henningsson; Wang Xingchao; alsa-de...@alsa-project.org;
> dan...@ffwll.ch; Lin, Mengdong; intel-gfx@lists.freedesktop.org; Li, Jocelyn;
> Bar
Instead of relying in acthd, track ring seqno progression
to detect if ring has hung.
v2: put hangcheck stuff inside struct (Chris Wilson)
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h |2 --
drivers/gpu/drm/i915/i915_irq.c | 30 +
In preparation to track per ring progress in hangcheck,
add i915_hangcheck_ring_hung.
v2: omit dev parameter (Ben Widawsky)
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 29 +
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/driv
Rework of per ring hangcheck made this obsolete.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h |1 -
drivers/gpu/drm/i915/i915_irq.c | 21 -
2 files changed, 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv
In preparation for next commit, pass seqno as a parameter
to i915_hangcheck_ring_idle as it will be used inside
i915_hangcheck_elapsed.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/d
Keep track of ring seqno progress and if there are no
progress detected, declare hang. Use actual head (acthd)
to distinguish between ring stuck and batchbuffer looping
situation. Stuck ring will be kicked to trigger progress.
v2: use atchd to detect stuck ring from loop (Ben Widawsky)
v3: Use ac
Chris Wilson writes:
> There is an unlikely corner case whereby a lockless wait may not notice
> a GPU hang and reset, and so continue to wait for the device to advance
> beyond the chosen seqno. This of course may never happen as the waiter
> may be the only user. Instead, we can explicitly adva
At Mon, 13 May 2013 15:37:28 +0800,
Wang Xingchao wrote:
>
> I915 module maybe loaded after snd_hda_intel, the power-well
> API doesnot exist in such case. This patch intended to avoid
> loading dependency between snd-hda-intel and i915 module.
>
> Signed-off-by: Wang Xingchao
Hm somehow th
At Mon, 13 May 2013 15:37:27 +0800,
Wang Xingchao wrote:
>
> hda_i915 has dependency on i915 module, this patch check whether
> symbol exist before calling API there. If i915 module not loaded it
> will try to load before use.
>
> Signed-off-by: Wang Xingchao
You need to manage the symbols more
At Mon, 13 May 2013 15:37:25 +0800,
Wang Xingchao wrote:
>
> This new added external module hda_i915 only built in when
> gfx i915 module built in. It includes hda_display_power()
> api implementation for hda controller driver, which will
> ask gfx driver for reqeust/release power well on Intel Ha
At Mon, 13 May 2013 15:37:24 +0800,
Wang Xingchao wrote:
>
> Haswell Display audio depends on power well in graphic side, it should
> request power well before use it and release power well after use.
> I915 will not shutdown power well if it detects audio is using.
> This patch protects display a
At Mon, 13 May 2013 11:55:14 +,
Wang, Xingchao wrote:
>
> Hi David,
>
>
> > -Original Message-
> > From: alsa-devel-boun...@alsa-project.org
> > [mailto:alsa-devel-boun...@alsa-project.org] On Behalf Of David Henningsson
> > Sent: Monday, May 13, 2013 4:29 PM
> > To: Wang Xingchao
>
On 05/13/2013 01:55 PM, Wang, Xingchao wrote:
Hi David,
-Original Message-
From: alsa-devel-boun...@alsa-project.org
[mailto:alsa-devel-boun...@alsa-project.org] On Behalf Of David Henningsson
Sent: Monday, May 13, 2013 4:29 PM
To: Wang Xingchao
Cc: alsa-de...@alsa-project.org; dan...@
Hi Jaroslav,
> -Original Message-
> From: alsa-devel-boun...@alsa-project.org
> [mailto:alsa-devel-boun...@alsa-project.org] On Behalf Of Jaroslav Kysela
> Sent: Monday, May 13, 2013 4:56 PM
> To: David Henningsson
> Cc: alsa-de...@alsa-project.org; Girdwood, Liam R; ti...@suse.de; Lin,
>
Hi David,
> -Original Message-
> From: alsa-devel-boun...@alsa-project.org
> [mailto:alsa-devel-boun...@alsa-project.org] On Behalf Of David Henningsson
> Sent: Monday, May 13, 2013 4:29 PM
> To: Wang Xingchao
> Cc: alsa-de...@alsa-project.org; dan...@ffwll.ch; ti...@suse.de; Lin,
> Mengd
At Mon, 13 May 2013 10:55:46 +0200,
Jaroslav Kysela wrote:
>
> Date 13.5.2013 10:28, David Henningsson wrote:
> > On 05/13/2013 09:37 AM, Wang Xingchao wrote:
> >> I915 module maybe loaded after snd_hda_intel, the power-well
> >> API doesnot exist in such case. This patch intended to avoid
> >> lo
On 05/13/2013 09:37 AM, Wang Xingchao wrote:
I915 module maybe loaded after snd_hda_intel, the power-well
API doesnot exist in such case. This patch intended to avoid
loading dependency between snd-hda-intel and i915 module.
Hi Xingchao and thanks for working on this.
This patch seems to re-do
I915 module maybe loaded after snd_hda_intel, the power-well
API doesnot exist in such case. This patch intended to avoid
loading dependency between snd-hda-intel and i915 module.
Signed-off-by: Wang Xingchao
---
drivers/gpu/drm/i915/i915_dma.c |3 ++
drivers/gpu/drm/i915/intel_drv.h |2
hda_i915 has dependency on i915 module, this patch check whether
symbol exist before calling API there. If i915 module not loaded it
will try to load before use.
Signed-off-by: Wang Xingchao
---
sound/pci/hda/hda_i915.c | 42 --
1 file changed, 40 insert
Display HDA need reqeust power well in case it's shut down by gfx.
Currently "hda" is the only user in audio side, even though the codecs
depends on same power well too, it's safe to share the same power well
with hda controller. If gfx power well could shut down only for codecs,
it can be added as
This new added external module hda_i915 only built in when
gfx i915 module built in. It includes hda_display_power()
api implementation for hda controller driver, which will
ask gfx driver for reqeust/release power well on Intel Haswell.
Signed-off-by: Wang Xingchao
---
sound/pci/hda/Kconfig
Haswell Display audio depends on power well in graphic side, it should
request power well before use it and release power well after use.
I915 will not shutdown power well if it detects audio is using.
This patch protects display audio crash for Intel Haswell mobile
C3 stepping board.
Signed-off-b
This patchset intended to Add power-well api support for Haswell.
For Intel Haswell , “power well” in GPU has impact for both Display HD-A
controller and codecs. Gfx driver has power well feature enaled but donot
think much about audio side. The issue is if gfx driver disabled power well,
audio s
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