Re: [Intel-gfx] [PATCH 10/12] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op

s/MI_FLUSH_SW/MI_FLUSH_DW/ On Tue, 2 Oct 2012 17:43:44 -0500 Jesse Barnes wrote: > So store into the scratch space of the HWS to make sure the invalidate > occurs. > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/i915_reg.h |6 -- > drivers/gpu/drm/i915/intel_ring

Re: [Intel-gfx] [PATCH 08/12] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB

On Tue, 2 Oct 2012 16:51:39 -0700 Ben Widawsky wrote: > On Tue, 2 Oct 2012 17:43:42 -0500 > Jesse Barnes wrote: > > > Workaround for dual port PS dispatch on GT1. > > > > Signed-off-by: Jesse Barnes > > --- > > drivers/gpu/drm/i915/intel_pm.c | 10 ++ > > 1 file changed, 10 insert

Re: [Intel-gfx] [PATCH 09/12] drm/i915: limit VLV IRQ enables to those we use

On Tue, 2 Oct 2012 17:43:43 -0500 Jesse Barnes wrote: > To match IVB. > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/i915_irq.c | 18 +- > 1 file changed, 5 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/

Re: [Intel-gfx] [PATCH 08/12] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB

On Tue, 2 Oct 2012 17:43:42 -0500 Jesse Barnes wrote: > Workaround for dual port PS dispatch on GT1. > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/intel_pm.c | 10 ++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/dr

Re: [Intel-gfx] [PATCH 07/12] drm/i915: implement WaDisableEarlyCull for VLV and IVB

On Tue, 2 Oct 2012 17:43:41 -0500 Jesse Barnes wrote: > Workaround for a culling optimization. > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/i915_reg.h |1 + > drivers/gpu/drm/i915/intel_pm.c |8 > 2 files changed, 9 insertions(+) > > diff --git a/drivers/gpu/

Re: [Intel-gfx] [PATCH 06/12] drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLV

On Tue, 2 Oct 2012 17:43:40 -0500 Jesse Barnes wrote: > This allows us to get the right vblank interrupt frequency. > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/intel_pm.c |7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/dri

Re: [Intel-gfx] [PATCH 05/12] drm/i915: implement WaGTEnableMiFlush on VLV

On Tue, 2 Oct 2012 17:43:39 -0500 Jesse Barnes wrote: > We don't generally use MI_FLUSH these days, but this bit may affect > other flushing logic, so set it to be safe. > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/intel_ringbuffer.c |3 +++ > 1 file changed, 3 insertions(

Re: [Intel-gfx] [PATCH 04/12] drm/i915: implement WaForceL3Serialization on VLV and IVB

On Tue, 2 Oct 2012 17:43:38 -0500 Jesse Barnes wrote: > References: https://bugs.freedesktop.org/show_bug.cgi?id=50250 > Signed-off-by: Jesse Barnes Reviewed-by: Ben Widawsky > --- > drivers/gpu/drm/i915/i915_reg.h |3 +++ > drivers/gpu/drm/i915/intel_pm.c |8 > 2 files cha

Re: [Intel-gfx] [PATCH 03/12] drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB

On Tue, 2 Oct 2012 17:43:37 -0500 Jesse Barnes wrote: > v2: use correct register > > References: https://bugs.freedesktop.org/show_bug.cgi?id=50233 > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/i915_reg.h |1 + > drivers/gpu/drm/i915/intel_pm.c |8 +++- > 2 files chan

Re: [Intel-gfx] [PATCH 01/12] drm/i915: add more clock gating regs for gen7, make sure writes happen

On Tue, 2 Oct 2012 17:43:35 -0500 Jesse Barnes wrote: > Add a few regs needed for various clock gating init purposes and make > sure they don't fall into the display offset range on VLV. > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/i915_drv.c | 17 + > driver

Re: [Intel-gfx] [PATCH 02/12] drm/i915: implement WaDisableL3CacheAging on VLV

On Tue, 2 Oct 2012 16:09:19 -0700 Ben Widawsky wrote: > On Wed, 3 Oct 2012 01:01:07 +0200 > Daniel Vetter wrote: > > > On Tue, Oct 02, 2012 at 05:43:36PM -0500, Jesse Barnes wrote: > > > Needs to be set on every context restore as well, so set it as > > > part of the initial state so we can sav

Re: [Intel-gfx] [PATCH 02/12] drm/i915: implement WaDisableL3CacheAging on VLV

On Wed, 3 Oct 2012 01:01:07 +0200 Daniel Vetter wrote: > On Tue, Oct 02, 2012 at 05:43:36PM -0500, Jesse Barnes wrote: > > Needs to be set on every context restore as well, so set it as part > > of the initial state so we can save/restore it. > > > > Signed-off-by: Jesse Barnes > > --- > > dri

[Intel-gfx] [PATCH 10/12] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op

So store into the scratch space of the HWS to make sure the invalidate occurs. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h |6 -- drivers/gpu/drm/i915/intel_ringbuffer.c | 22 ++ 2 files changed, 22 insertions(+), 6 deletions(-) diff --g

[Intel-gfx] [PATCH 11/12] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall

"If ENABLED, PIPE_CONTROL command will flush the in flight data written out by render engine to Global Observation point on flush done. Also Requires stall bit ([20] of DW1) set." So set the stall bit to ensure proper invalidation. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_rin

[Intel-gfx] [PATCH 12/12] drm/i915: set swizzling to none on VLV

We don't have bit 6 swizzling on VLV, so this function is easy. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_gem_tiling.c |5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index

Re: [Intel-gfx] [PATCH 02/12] drm/i915: implement WaDisableL3CacheAging on VLV

On Tue, Oct 02, 2012 at 05:43:36PM -0500, Jesse Barnes wrote: > Needs to be set on every context restore as well, so set it as part of > the initial state so we can save/restore it. > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/i915_reg.h |1 + > drivers/gpu/drm/i915/intel_pm.

[Intel-gfx] [PATCH 09/12] drm/i915: limit VLV IRQ enables to those we use

To match IVB. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_irq.c | 18 +- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index d915126..096b387 100644 --- a/drivers/gpu/drm/i915/i915_

[Intel-gfx] [PATCH 08/12] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB

Workaround for dual port PS dispatch on GT1. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_pm.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 400dd05..ce8d7b2 100644 --- a/drivers/gpu/drm/i91

[Intel-gfx] [PATCH 07/12] drm/i915: implement WaDisableEarlyCull for VLV and IVB

Workaround for a culling optimization. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_pm.c |8 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c75539b..3ceeb6

[Intel-gfx] [PATCH 06/12] drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLV

This allows us to get the right vblank interrupt frequency. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_pm.c |7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 0659317..828629b 100644 --- a/drivers/

[Intel-gfx] [PATCH 05/12] drm/i915: implement WaGTEnableMiFlush on VLV

We don't generally use MI_FLUSH these days, but this bit may affect other flushing logic, so set it to be safe. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_ringbuffer.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu

[Intel-gfx] [PATCH 04/12] drm/i915: implement WaForceL3Serialization on VLV and IVB

References: https://bugs.freedesktop.org/show_bug.cgi?id=50250 Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h |3 +++ drivers/gpu/drm/i915/intel_pm.c |8 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_r

[Intel-gfx] [PATCH 03/12] drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB

v2: use correct register References: https://bugs.freedesktop.org/show_bug.cgi?id=50233 Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_pm.c |8 +++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i9

[Intel-gfx] [PATCH 02/12] drm/i915: implement WaDisableL3CacheAging on VLV

Needs to be set on every context restore as well, so set it as part of the initial state so we can save/restore it. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_pm.c |2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/d

[Intel-gfx] [PATCH 01/12] drm/i915: add more clock gating regs for gen7, make sure writes happen

Add a few regs needed for various clock gating init purposes and make sure they don't fall into the display offset range on VLV. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.c | 17 + drivers/gpu/drm/i915/i915_reg.h | 11 +++ 2 files changed, 28 inser

[Intel-gfx] Updated workaround & VLV fixes

I still need to rework the dual dispatch and store dw workarounds based on comments, but I think the others are ok now, and I included a couple of fixes for VLV stuff in the bomb here too. Thanks, Jesse ___ Intel-gfx mailing list Intel-gfx@lists.freedes

Re: [Intel-gfx] Intel-gfx Digest, Vol 57, Issue 7

On 02.10.12 20:08, Daniel Vetter wrote: On Tue, Oct 2, 2012 at 7:45 PM, Mario Kleiner wrote: I'm fine with removing the hack and fixing this properly, especially if you say that it didn't work realiably in some cases. But i hope this means that timestamping sanity tests via flip_test are a par

[Intel-gfx] [PATCH 47/47] drm/i915: create the DDI encoder

From: Paulo Zanoni Now intel_ddi_init is just like intel_hdmi_init and intel_dp_init: it inits the encoder and then calls the proper init_connector functions. Notice that for non-eDP ports we call both HDMI and DP connector init, so we have 2 connectors attached to each DDI encoder. After this c

[Intel-gfx] [PATCH 46/47] drm/i915: add intel_ddi_connector_get_hw_state

From: Paulo Zanoni We need this since now on DDI we will have 2 connectors on each encoder. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ddi.c | 40 + drivers/gpu/drm/i915/intel_dp.c |6 +- drivers/gpu/drm/i915/intel_drv.h |1

[Intel-gfx] [PATCH 45/47] drm/i915: reset intel_encoder->type when DP or HDMI is detected

From: Paulo Zanoni When intel_hdmi_detect detects a monitor, set intel_encoder->type with INTEL_OUTPUT_HDMI. Same for DP. This should not break the current code because these variables never change. This will be used after we create the DDI encoder because it will have both DP and HDMI connector

[Intel-gfx] [PATCH 44/47] drm/i915: split intel_dp_init into encoder and connector pieces

From: Paulo Zanoni Same reason as the previous HDMI commit: the DDI code will have its own encoder init function but still use the DP and HDMI connectors. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_dp.c | 127 +-- 1 file changed, 69 insertio

[Intel-gfx] [PATCH 43/47] drm/i915: split intel_hdmi_init into encoder and connector pieces

From: Paulo Zanoni We want to split the HDMI connector and encoder initialization because in the future the DDI code will have its own "encoder init" function, but it will still call intel_hdmi_init_connector. The DDI encoder will actually have two connectors attached to it: HDMI and DP. The bes

[Intel-gfx] [PATCH 42/47] drm/i915: remove encoder args from intel_{dp, hdmi}_add_properties

From: Paulo Zanoni They were unused. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_dp.c |4 ++-- drivers/gpu/drm/i915/intel_hdmi.c |4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c in

[Intel-gfx] [PATCH 41/47] drm/i915: create intel_digital_port and use it

From: Paulo Zanoni The goal is to have one single encoder capable of controlling both DP and HDMI outputs. This patch just adds the initial infrastructure, no functional changes. Previously, both intel_dp and intel_hdmi were intel_encoders. Now, these 2 structs do not have intel_encoder as membe

[Intel-gfx] [PATCH 40/47] drm/i915: add intel_dp_to_dev and intel_hdmi_to_dev

From: Paulo Zanoni When we add struct intel_digital_port, there will be no direct way of going from intel_{dp,hdmi} to drm_device: we will need to call container_of(). This patch adds functions to go from intel_{dp,hdmi} to drm_device. The main goal here is to greatly reduce the size of the next

[Intel-gfx] [PATCH 39/47] drm/i915: simplify assignments inside intel_dp.c

From: Paulo Zanoni Replace container_of with enc_to_intel_dp. Walk through less structures when making assignments. Rename some variables to keep our naming standards. As a bonus, this will reduce the usage of "struct intel_dp", making the future patch that introduces intel_digital_port smaller

[Intel-gfx] [PATCH 38/47] drm/i915: enable DDI eDP

From: Paulo Zanoni Now that all the eDP enablement bits are there, we can actually try to use the eDP. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ddi.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 37/47] drm/i915: turn the eDP DDI panel on/off

From: Paulo Zanoni It's an important step :) Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ddi.c | 18 -- drivers/gpu/drm/i915/intel_dp.c | 11 --- drivers/gpu/drm/i915/intel_drv.h |4 3 files changed, 24 insertions(+), 9 deletions(-) diff --

[Intel-gfx] [PATCH 36/47] drm/i915: set/unset the DDI eDP backlight

From: Paulo Zanoni Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ddi.c | 15 +-- drivers/gpu/drm/i915/intel_dp.c |4 ++-- drivers/gpu/drm/i915/intel_drv.h |6 -- 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dd

[Intel-gfx] [PATCH 35/47] drm/i915: set the correct eDP aux channel clock divider on DDI

From: Paulo Zanoni The cdclk frequency is not always the same, so the value here should be adjusted to match it. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_dp.c |7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drive

[Intel-gfx] [PATCH 34/47] drm/i915: select the correct pipe when using TRANSCODER_EDP

From: Paulo Zanoni Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ddi.c | 17 + 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 980a591..7bcc85d 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +

[Intel-gfx] [PATCH 33/47] drm/i915: implement workaround for VTOTAL when using TRANSCODER_EDP

From: Paulo Zanoni See the documentation for the DDI_FUNC_CTL register, EDP Input Select bits: when the EDP input selection is B, the VTOTAL_B must be programmed with the VTOTAL_EDP value, same thing for selection C. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 11 +

[Intel-gfx] [PATCH 32/47] drm/i915: convert pipe timing definitions to transcoder

From: Paulo Zanoni Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_irq.c |7 +++-- drivers/gpu/drm/i915/i915_reg.h | 14 +- drivers/gpu/drm/i915/intel_crt.c |6 ++-- drivers/gpu/drm/i915/intel_display.c | 51 +- 4 files

[Intel-gfx] [PATCH 31/47] drm/i915: convert CPU M/N timings to transcoder

From: Paulo Zanoni Same thing as the previous commits. Not renaming this one since it exists since way before Haswell. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 16 drivers/gpu/drm/i915/intel_display.c | 12 ++-- drivers/gpu/drm/i915/in

[Intel-gfx] [PATCH 30/47] drm/i915: convert PIPE_MSA_MISC to transcoder

From: Paulo Zanoni Same as the other registers. This one also appeared on Haswell for the first time, so that's why we are renaming it. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 19 ++- drivers/gpu/drm/i915/intel_ddi.c | 16 2 files

[Intel-gfx] [PATCH 29/47] drm/i915: convert PIPECONF to use transcoder instead of pipe

From: Paulo Zanoni Because the PIPECONF register is actually part of the CPU transcoder, not the CPU pipe. Ideally we would also rename PIPECONF to TRANSCONF to remind people that they should use the transcoder instead of the pipe, but let's keep it like this for now since most Gens still name i

[Intel-gfx] [PATCH 28/47] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state

From: Paulo Zanoni We need to check if any of the pipes is using TRANSCODER_EDP. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 25 + 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/in

[Intel-gfx] [PATCH 27/47] drm/i915: convert DDI_FUNC_CTL to transcoder

From: Paulo Zanoni Because there's one instance of the register per CPU transcoder and not per CPU pipe. This is another register that appeared for the first time on Haswell, and even though its Haswell name is PIPE_DDI_FUNC_CTL, it will be renamed to TRANS_DDI_FUNC_CTL, so let's just use the new

[Intel-gfx] [PATCH 26/47] drm/i915: convert PIPE_CLK_SEL to transcoder

From: Paulo Zanoni This register appeared in Haswell. It does not have an EDP version because the EDP transcoder is always tied to the DDIA clock. Notice that if we call PIPE_CLK_SEL(pipe) when pipe is PIPE_A and transcoder is TRANSCODER_EDP we might introduce a bug, that's why this is a transcod

[Intel-gfx] [PATCH 25/47] drm/i915: add TRANSCODER_EDP

From: Paulo Zanoni Before Haswell we used to have 3 pipes (A, B and C) and 3 transcoders (A, B and C), and there was an 1:1 mapping on then. Because of this mapping, every register that was actually part of the transcoder was called PIPE_SOMETHING instead of TRANSCODER_SOMETHING and its definitio

[Intel-gfx] [PATCH 24/47] drm/i915: set the correct function pointers for Haswell DP

From: Paulo Zanoni This is the final remaining piece of Haswell DP enablement. After this patch, just calling intel_dp_init on any port will make DP work. We still do not do this because we're currently initializing HDMI on all the ports, so if we replace intel_hdmi_init with intel_dp_init, we wi

[Intel-gfx] [PATCH 23/47] drm/i915: implement Haswell DP link train sequence

From: Paulo Zanoni Previous patch "drm/i915: add basic Haswell DP link train bits" implemented the basic structure to set the voltage levels and training patterns. This patch adds the higher-level bits that are part of the mode set sequence and hot plug. Signed-off-by: Paulo Zanoni --- drivers

[Intel-gfx] [PATCH 22/47] drm/i915: add DP support to intel_enable_ddi

From: Paulo Zanoni We should only write the DDI_BUF_CTL at this point for HDMI/DVI. For DP we need to do this earlier, and the values written to the register are also different. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ddi.c | 23 +-- 1 file changed, 13

[Intel-gfx] [PATCH 21/47] drm/i915: add DP support to intel_ddi_get_hw_state

From: Paulo Zanoni Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ddi.c |8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 60e089c..57dd975 100644 --- a/drivers/gpu/drm/i915/intel_d

[Intel-gfx] [PATCH 20/47] drm/i915: add DP support to intel_ddi_get_encoder_port

From: Paulo Zanoni Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ddi.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 7f30992..60e089c 100644 --- a/drivers/gpu/drm/i915/int

[Intel-gfx] [PATCH 19/47] drm/i915: fix DP AUX register definitions on Haswell

From: Paulo Zanoni The old rule that the AUX registers are just an offset (+4 and +10) from output_reg is not true anymore, since output_reg in on the CPU and some AUX regs are on the PCH. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h |8 drivers/gpu/drm/i915/int

[Intel-gfx] [PATCH 18/47] drm/i915: fix Haswell DP M/N registers

From: Paulo Zanoni We have to write the correct values inside intel_dp_set_m_n and then prevent these values from being overwritten later. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c |3 ++- drivers/gpu/drm/i915/intel_dp.c |7 ++- 2 files changed, 8 in

[Intel-gfx] [PATCH 17/47] drm/i915: use TU_SIZE macro at intel_dp_set_m_n

From: Paulo Zanoni Much simpler and looks more like the M/N code inside intel_display.c. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_dp.c |7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp

[Intel-gfx] [PATCH 16/47] drm/i915: add basic Haswell DP link train bits

From: Paulo Zanoni Previously, the DP register was used for everything. On Haswell, it was split into DDI_BUF_CTL (which is the new intel_dp->DP register) and DP_TP_CTL. The logic behind this patch is based on a patch written by Shobhit Kumar, but the way the code was written is very different.

[Intel-gfx] [PATCH 15/47] drm/i915: add DP support to intel_ddi_mode_set

From: Paulo Zanoni Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ddi.c | 61 +++--- drivers/gpu/drm/i915/intel_dp.c | 28 ++--- drivers/gpu/drm/i915/intel_drv.h |1 + 3 files changed, 62 insertions(+), 28 deletions(-) diff --git

[Intel-gfx] [PATCH 14/47] drm/i915: add DP support to intel_ddi_disable_port

From: Paulo Zanoni Just a missing register. There is no problem to run this code when the output is HDMI. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ddi.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/driver

[Intel-gfx] [PATCH 13/47] drm/i915: add DP support to intel_ddi_pll_mode_set

From: Paulo Zanoni Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ddi.c | 25 - 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index fc6679c..ad3ecd6 100644 --- a/drivers/gpu

[Intel-gfx] [PATCH 12/47] drm/i915: add intel_ddi_set_pipe_settings

From: Paulo Zanoni In theory, all the DDI pipe settings should be set here, including timing and M/N registers. For now, let's just set the DP MSA attributes. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 10 ++ drivers/gpu/drm/i915/intel_ddi.c | 33 +++

[Intel-gfx] [PATCH 11/47] drm/i915: add DP support to intel_ddi_enable_pipe_func

From: Paulo Zanoni Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ddi.c | 33 + drivers/gpu/drm/i915/intel_dp.c |5 - drivers/gpu/drm/i915/intel_drv.h |5 + 3 files changed, 34 insertions(+), 9 deletions(-) diff --git a/drivers/gpu

[Intel-gfx] [PATCH 10/47] drm/i915: pipe and planes should be disabled on haswell_crtc_mode_set

From: Paulo Zanoni So WARN in case they're not. It also does not make any sense to wait_for_vblank at this point. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c |7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_displa

[Intel-gfx] [PATCH 09/47] drm/i915: add haswell_set_pipeconf

From: Paulo Zanoni It's a copy of ironlake_set_pipeconf with 2 differences: - There is no BPC field to set. - The interlaced mask is now 2 bits instead of 3. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_display.c | 27 +

[Intel-gfx] [PATCH 08/47] drm/i915: add proper CPU/PCH checks to crtc_mode_set functions

From: Paulo Zanoni On ironlake_crtc_mode_set, WARN if not using IBX or CPT. On haswell_crtc_mode_set, only run IBX/CPT code on IBX/CPT. I am still not sure whether IBX/CPT will be possible with a Haswell CPU, so leave the code there for now and put a WARN in case we spot it. Signed-off-by: Paul

[Intel-gfx] [PATCH 07/47] drm/i915: add haswell_crtc_mode_set

From: Paulo Zanoni It's just a copy of ironlake_crtc_mode_set. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 196 +- 1 file changed, 191 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm

[Intel-gfx] [PATCH 06/47] drm/i915: disable DDI_BUF_CTL at the correct time

From: Paulo Zanoni And also properly wait for its idle bit. You may notice that DDI_BUF_CTL is enabled in .enable but disabled in .post_disable instead of .disable. Yes, the mode set sequence is not exactly symmetrical, but let's assume the spec is correct unless we can prove it's wrong. Signed

[Intel-gfx] [PATCH 05/47] drm/i915: don't rely on previous values set on DDI_BUF_CTL

From: Paulo Zanoni Just set the only bit we need, everything else is either ignored on HDMI or should be set to zero. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ddi.c |6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/

[Intel-gfx] [PATCH 04/47] drm/i915: completely rewrite the Haswell PLL handling code

From: Paulo Zanoni Problems with the previous code: - HDMI just uses WRPLL1 for everything, so dual head cases might not work sometimes. - At encoder->mode_set we just write the PLL register without doing any kind of check (e.g., check if the PLL is already being used). - There is n

[Intel-gfx] [PATCH 03/47] drm/i915: enable and disable PIPE_CLK_SEL at the right time

From: Paulo Zanoni Previously we were enabling it at mode_set but never disabling. Let's follow the mode set sequence. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ddi.c | 37 ++ drivers/gpu/drm/i915/intel_display.c |6 ++ drivers/gpu

[Intel-gfx] [PATCH 02/47] drm/i915: enable and disable DDI_FUNC_CTL at the right time

From: Paulo Zanoni And the right time is exactly after/before changing PIPE_CONF. See the documentation about the mode set sequence. This code is not inside any encoder-specific callback because DDI_FUNC_CTL is part of the pipe, so it is used by all encoders. Signed-off-by: Paulo Zanoni --- d

[Intel-gfx] [PATCH 01/47] drm/i915: rewrite the LCPLL code

From: Paulo Zanoni Right now, we're trying to enable LCPLL at every mode set, but we're never disabling it. Also, we really don't want to be disabling LCPLL since it requires a very complex disable sequence. So instead of enabling it at every mode set, enable it once. Also, we are currently not

[Intel-gfx] [PATCH 00/47] Haswell clocking and HDMI fixes, DP and eDP support

From: Paulo Zanoni Hi Some time ago I sent an RFC containing 30 patches fixing Haswell display. This is a new version of that series. The main difference is that those patches were on the pre-modeset-rework world and these are now on the post-modeset-rework world. I have to say that the modeset-

[Intel-gfx] [PATCH] drm/i915: don't frob the vblank ts in finish_page_flip

Now that we correctly generate it, this hack is no longer required (and might actually paper over a serious bug). pageflip timestamps are sanity check in the latest version of the flip-test in intel-gpu-tools. v2: Also remove the gettimeofday(&now) which is no longer used. Noticed by Mario Kleine

Re: [Intel-gfx] Intel-gfx Digest, Vol 57, Issue 7

On Tue, Oct 2, 2012 at 7:45 PM, Mario Kleiner wrote: > > I'm fine with removing the hack and fixing this properly, especially if you > say that it didn't work realiably in some cases. But i hope this means that > timestamping sanity tests via flip_test are a part of your regular QA > testing befor

Re: [Intel-gfx] Intel-gfx Digest, Vol 57, Issue 7

-- Message: 5 Date: Tue, 2 Oct 2012 17:54:35 +0200 From: Daniel Vetter To: Intel Graphics Development Cc: Daniel Vetter , sta...@vger.kernel.org Subject: [Intel-gfx] [PATCH 1/2] drm/i915: call drm_handle_vblank before finish_page_flip Message-ID: <134919327

Re: [Intel-gfx] [PATCH] drm/i915: s/DRM_IRQ_ARSG/int irq, void *arg

On Tue, Oct 02, 2012 at 04:42:14PM +0300, Jani Nikula wrote: > On Tue, 02 Oct 2012, Daniel Vetter wrote: > > Subject: [Intel-gfx] [PATCH] drm/i915: s/DRM_IRQ_ARSG/int irq, void *arg > > sed: -e expression #1, char 33: unterminated `s' command > > also s/ARSG/ARGS/ > > > I'm official fed up with

[Intel-gfx] [PATCH 2/2] drm/i915: don't frob the vblank ts in finish_page_flip

Now that we correctly generate it, this hack is no longer required (and might actually paper over a serious bug). pageflip timestamps are sanity check in the latest version of the flip-test in intel-gpu-tools. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 19

[Intel-gfx] [PATCH 1/2] drm/i915: call drm_handle_vblank before finish_page_flip

... since finish_page_flip needs the vblank timestamp generated in drm_handle_vblank. Somehow all the gmch platforms get it right, but all the pch platform irq handlers get is wrong. Hooray for copy& pasting! Currently this gets papered over by a gross hack in finish_page_flip. A second patch will

Re: [Intel-gfx] [regression] 3.6-rc6, gpu hang with vaapi

> Hi, > > I get a GPU hang every time i play an mkv using mplayer -vo vaapi with 3.6- > rc6. > With 3.5.4 no GPU hang at all. > > I'm using xf86-video-intel 2.20.8, xorg-server 1.12.4 and libva-1.1.0 on Intel(R) > Sandybridge Mobile (GT2+). > I have a SandyBridge 2600K and had problems running

Re: [Intel-gfx] [PATCH] drm/i915: extract intel_set_pipe_timings from crtc_mode_set

Reviewed-by: Rodrigo Vivi On Mon, Oct 1, 2012 at 6:10 PM, Paulo Zanoni wrote: > From: Paulo Zanoni > > Version 2: call intel_set_pipe_timings from both i9xx_crtc_mode_set > and ironlake_crtc_mode_set, instead of just ironlake, as requested by > Daniel Vetter. > > The problem caused by calling t

Re: [Intel-gfx] [PATCH] console: implement lockdep support for console_lock

On Tue, Oct 2, 2012 at 3:28 PM, Greg KH wrote: > No, as it hasn't been in linux-next already, I can't send it in for 3.7, > sorry, you know that. I'll be glad to queue it up for 3.8 if you want me to. Hey, was worth a shot ;-) Yeah, if you can pick it up for 3.8, that would be nice, since the pa

Re: [Intel-gfx] [PATCH] console: implement lockdep support for console_lock

On Tue, Oct 02, 2012 at 02:56:48PM +0200, Daniel Vetter wrote: > On Sat, Sep 22, 2012 at 10:06 PM, Greg KH wrote: > > On Sat, Sep 22, 2012 at 07:52:11PM +0200, Daniel Vetter wrote: > >> Dave Airlie recently discovered a locking bug in the fbcon layer, > >> where a timer_del_sync (for the blinking

[Intel-gfx] [PATCH] drm/i915: s/DRM_IRQ_ARSG/int irq, void *arg

I'm official fed up with the yelling and useless indirection. Let if burn! Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_irq.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index

Re: [Intel-gfx] [PATCH] console: implement lockdep support for console_lock

On Sat, Sep 22, 2012 at 10:06 PM, Greg KH wrote: > On Sat, Sep 22, 2012 at 07:52:11PM +0200, Daniel Vetter wrote: >> Dave Airlie recently discovered a locking bug in the fbcon layer, >> where a timer_del_sync (for the blinking cursor) deadlocks with the >> timer itself, since both (want to) hold t

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Re: [Intel-gfx] [PATCH] drm/i915: Flush the pending flips on the CRTC before modification

On Fri, Sep 28, 2012 at 01:04:03PM +0100, Chris Wilson wrote: > On Fri, 28 Sep 2012 08:37:20 +0200, Daniel Vetter wrote: > > On Thu, Sep 27, 2012 at 09:25:58PM +0100, Chris Wilson wrote: > > > This was meant to be the purpose of the > > > intel_crtc_wait_for_pending_flips() function which is calle

Re: [Intel-gfx] [PATCH] drm/i915: Actually invalidate the TLB for the SandyBridge HW contexts w/a

On Mon, Oct 01, 2012 at 02:27:04PM +0100, Chris Wilson wrote: > A side-effect of commit 7d54a904285b6e780291b91a518267bec5591913 > Author: Chris Wilson > Date: Fri Aug 10 10:18:10 2012 +0100 > > drm/i915: Apply post-sync write for pipe control invalidates > > was that only a request to emi

Re: [Intel-gfx] A simple driver question

On Tue, Oct 02, 2012 at 06:01:03PM +1000, Dave Airlie wrote: > On Mon, Oct 1, 2012 at 4:45 PM, Nikolskiy Alexey > wrote: > > Good time of day! > > > > My name is Alexey Nikolskiy. I am a student in the St.Petersburg State > > Polytechnical University. Now I am doing my research arond operating sy

Re: [Intel-gfx] A simple driver question

On Mon, Oct 1, 2012 at 4:45 PM, Nikolskiy Alexey wrote: > Good time of day! > > My name is Alexey Nikolskiy. I am a student in the St.Petersburg State > Polytechnical University. Now I am doing my research arond operating system > we are developing in our university. So I am looking for creating