s/MI_FLUSH_SW/MI_FLUSH_DW/ On Tue, 2 Oct 2012 17:43:44 -0500 Jesse Barnes <jbar...@virtuousgeek.org> wrote:
> So store into the scratch space of the HWS to make sure the invalidate > occurs. > > Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org> > --- > drivers/gpu/drm/i915/i915_reg.h | 6 ++++-- > drivers/gpu/drm/i915/intel_ringbuffer.c | 22 ++++++++++++++++++---- > 2 files changed, 22 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 3ceeb68..d98c989 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -241,8 +241,10 @@ > */ > #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) > #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ > -#define MI_INVALIDATE_TLB (1<<18) > -#define MI_INVALIDATE_BSD (1<<7) > +#define MI_FLUSH_DW_STORE_INDEX (1<<21) > +#define MI_INVALIDATE_TLB (1<<18) > +#define MI_FLUSH_DW_OP_STOREDW (1<<14) > +#define MI_INVALIDATE_BSD (1<<7) > #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) > #define MI_BATCH_NON_SECURE (1) > #define MI_BATCH_NON_SECURE_I965 (1<<8) > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 1718c54..d3b7129 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -1395,10 +1395,17 @@ static int gen6_ring_flush(struct intel_ring_buffer > *ring, > return ret; > > cmd = MI_FLUSH_DW; > + /* > + * Bspec vol 1c.5 - video engine command streamer: > + * "If ENABLED, all TLBs will be invalidated once the flush > + * operation is complete. This bit is only valid when the > + * Post-Sync Operation field is a value of 1h or 3h." > + */ > if (invalidate & I915_GEM_GPU_DOMAINS) > - cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; > + cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | > + MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; > intel_ring_emit(ring, cmd); > - intel_ring_emit(ring, 0); > + intel_ring_emit(ring, I915_GEM_SCRATCH_INDEX << 3); > intel_ring_emit(ring, 0); > intel_ring_emit(ring, MI_NOOP); > intel_ring_advance(ring); > @@ -1436,10 +1443,17 @@ static int blt_ring_flush(struct intel_ring_buffer > *ring, > return ret; > > cmd = MI_FLUSH_DW; > + /* > + * Bspec vol 1c.3 - blitter engine command streamer: > + * "If ENABLED, all TLBs will be invalidated once the flush > + * operation is complete. This bit is only valid when the > + * Post-Sync Operation field is a value of 1h or 3h." > + */ > if (invalidate & I915_GEM_DOMAIN_RENDER) > - cmd |= MI_INVALIDATE_TLB; > + cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | > + MI_FLUSH_DW_OP_STOREDW; > intel_ring_emit(ring, cmd); > - intel_ring_emit(ring, 0); > + intel_ring_emit(ring, I915_GEM_SCRATCH_INDEX << 3); > intel_ring_emit(ring, 0); > intel_ring_emit(ring, MI_NOOP); > intel_ring_advance(ring); Reviewed-by: Ben Widawsky <b...@bwidawsk.net> -- Ben Widawsky, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
