Re: [Intel-gfx] [PATCH 14/16] intel: Add is_855ish for handling 855 and 865 specific lod clamping

On Tue, 07 Jun 2011 21:22:28 +0100, Chris Wilson wrote: > On Tue, 7 Jun 2011 15:34:19 -0400, Kristian Høgsberg > wrote: > > struct intel_chipset { > > int gen; > > - GLboolean is_945, is_g4x; > > + GLboolean is_855ish, is_945, is_g4x; > > > > /* WM maximum threads is number of E

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fix MI_DISPLAY_FLIP plane select offset on Ivybridge.

On Tue, 07 Jun 2011 17:55:05 -0700, Kenneth Graunke wrote: > In the latest version of the Render Engine Command Streamer chapter, > 18:8 are 'reserved' on IVB. Perhaps you have an old copy? Yeah, I haven't sync'd for a week or so. > Apparently MI_DISPLAY_FLIP also exists in the Blitter Engin

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fix MI_DISPLAY_FLIP plane select offset on Ivybridge.

On 06/07/2011 04:14 PM, Keith Packard wrote: On Tue, 7 Jun 2011 15:54:39 -0700, Kenneth Graunke wrote: According to BSpec volume 1c.4 section 3.2.9, Display (Plane) Select is now at bits 21:19 instead of 21:20. Signed-off-by: Kenneth Graunke I will note that the docs have an obvious bug --

Re: [Intel-gfx] [PATCH 01/16] intel: Use gen number instead of PCI ID in decoder

On Tue, 7 Jun 2011 15:34:06 -0400, Kristian Høgsberg wrote: > --- > src/mesa/drivers/dri/intel/intel_batchbuffer.c |2 +- > src/mesa/drivers/dri/intel/intel_chipset.h |3 -- > src/mesa/drivers/dri/intel/intel_decode.c | 42 > > src/mesa/drivers/dri/i

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Enable GPU reset on Ivybridge.

On Tue, 7 Jun 2011 15:54:41 -0700, Kenneth Graunke wrote: > According to the hardware documentation, GDRST is exactly the same as on > Sandybridge. So simply enable the existing code. Reviewed-by: Keith Packard -- keith.pack...@intel.com pgpVnIstJxu8Z.pgp Description: PGP signature _

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Remove HAS_BLT/HAS_BSD checks from ivybridge_irq_postinstall.

On Tue, 7 Jun 2011 15:54:40 -0700, Kenneth Graunke wrote: > Ivybridge has BLT and BSD rings, so there's no need to check. Reviewed-by: Keith Packard -- keith.pack...@intel.com pgpdirl6C8HQ7.pgp Description: PGP signature ___ Intel-gfx mailing lis

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fix MI_DISPLAY_FLIP plane select offset on Ivybridge.

On Tue, 7 Jun 2011 15:54:39 -0700, Kenneth Graunke wrote: > According to BSpec volume 1c.4 section 3.2.9, Display (Plane) Select is > now at bits 21:19 instead of 21:20. > > Signed-off-by: Kenneth Graunke I will note that the docs have an obvious bug -- 21:8 are 'reserved' on IVB while 21:19

[Intel-gfx] [PATCH 3/3] drm/i915: Enable GPU reset on Ivybridge.

According to the hardware documentation, GDRST is exactly the same as on Sandybridge. So simply enable the existing code. Signed-off-by: Kenneth Graunke --- drivers/gpu/drm/i915/i915_drv.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b

[Intel-gfx] [PATCH 2/3] drm/i915: Remove HAS_BLT/HAS_BSD checks from ivybridge_irq_postinstall.

Ivybridge has BLT and BSD rings, so there's no need to check. Signed-off-by: Kenneth Graunke --- drivers/gpu/drm/i915/i915_irq.c |6 ++ 1 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b9fafe3..6a2b7f4

[Intel-gfx] [PATCH 1/3] drm/i915: Fix MI_DISPLAY_FLIP plane select offset on Ivybridge.

According to BSpec volume 1c.4 section 3.2.9, Display (Plane) Select is now at bits 21:19 instead of 21:20. Signed-off-by: Kenneth Graunke --- drivers/gpu/drm/i915/intel_display.c | 11 ++- 1 files changed, 10 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_displ

Re: [Intel-gfx] [PATCH 1/4] drm: add plane support

On Tue, 7 Jun 2011 13:07:39 -0700 Jesse Barnes wrote: > +#define DRM_MODE_PLANE_FORMAT_YUV422 1 /* YUV 4:2:2 packed */ > +#define DRM_MODE_PLANE_FORMAT_RGBX101010 2 /* RGB 10bpc, ign. alpha */ > +#define DRM_MODE_PLANE_FORMAT_RGBX8883 /* Standard x:8:8:8 > RGB */ > +

Re: [Intel-gfx] [PATCH 1/4] drm: add plane support

On Tue, 7 Jun 2011 13:07:39 -0700 Jesse Barnes wrote: > +/* Planes blend with or override other bits on the CRTC */ > +struct drm_mode_set_plane { > + __u32 plane_id; > + __u32 crtc_id; > + __u32 fb_id; /* contains surface format type */ > + > + __u32 crtc_x, crtc_y; > + __u3

Re: [Intel-gfx] [PATCH 4/4] drm/i915: add SNB video sprite support

On Tue, 7 Jun 2011 13:07:42 -0700, Jesse Barnes wrote: > The video sprites support video surface formats natively and can handle > scaling well. So add support for them using the new DRM core overlay > support functions. > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/Makefile

Re: [Intel-gfx] [PATCH 3/4] drm/i915: rename existing overlay support to "legacy"

On Tue, 7 Jun 2011 13:07:41 -0700, Jesse Barnes wrote: > The old overlay block has all sorts of quirks and is very different than > ILK+ video sprites. So rename it to legacy to make that clear and clash > less with core overlay support. > > Signed-off-by: Jesse Barnes > --- > @@ -191,7 +191,

Re: [Intel-gfx] [PATCH 14/16] intel: Add is_855ish for handling 855 and 865 specific lod clamping

On Tue, 7 Jun 2011 15:34:19 -0400, Kristian Høgsberg wrote: > struct intel_chipset { > int gen; > - GLboolean is_945, is_g4x; > + GLboolean is_855ish, is_945, is_g4x; > > /* WM maximum threads is number of EUs times number of threads per EU. */ > int wm_max_threads; This can

[Intel-gfx] [PATCH 3/4] drm/i915: rename existing overlay support to "legacy"

The old overlay block has all sorts of quirks and is very different than ILK+ video sprites. So rename it to legacy to make that clear and clash less with core overlay support. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_debugfs.c |2 +- drivers/gpu/drm/i915/i915_drv.h |

[Intel-gfx] [PATCH 4/4] drm/i915: add SNB video sprite support

The video sprites support video surface formats natively and can handle scaling well. So add support for them using the new DRM core overlay support functions. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/Makefile |1 + drivers/gpu/drm/i915/i915_reg.h | 52 ++

[Intel-gfx] [PATCH 2/4] drm: add an fb creation ioctl that takes a pixel format

To properly support the various plane formats supported by different hardware, the kernel must know the pixel format of a framebuffer object. So add a new ioctl taking a format argument corresponding to a fourcc name from videodev2.h. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/drm_crtc.c

[Intel-gfx] [PATCH 1/4] drm: add plane support

Planes are a bit like half-CRTCs. They have a location and fb, but don't drive outputs directly. Add support for handling them to the core KMS code. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/drm_crtc.c | 230 drivers/gpu/drm/drm_drv.c |3

[Intel-gfx] [RFC] Updated DRM plane handling patches

This patchset updates the previous one, incorporating the feedback I received: 1) uses the v4l fourcc codes to communicate pixel format 2) adds a new addfb ioctl that takes a format 3) adds working SNB support for the new code Comments welcome. I'll be pushing intel-gpu-tools testdisplay su

[Intel-gfx] [PATCH 16/16] intel: Remove intel_chipsets.h

--- src/mesa/drivers/dri/i915/i830_texstate.c |1 - src/mesa/drivers/dri/i965/brw_defines.h |2 - src/mesa/drivers/dri/intel/intel_chipset.h| 83 - src/mesa/drivers/dri/intel/intel_context.c|1 - src/mesa/drivers/dri/intel/intel_decode.c

[Intel-gfx] [PATCH 15/16] intel: Get chipset name from PCI ID list

--- include/pci_ids/i915_pci_ids.h | 30 include/pci_ids/i965_pci_ids.h | 54 +++--- include/pci_ids/pci_id_driver_map.h|4 +- src/mesa/drivers/dri/intel/intel_context.c | 117 ++-- src/mesa/drivers/dri/intel/intel_s

[Intel-gfx] [PATCH 14/16] intel: Add is_855ish for handling 855 and 865 specific lod clamping

--- include/pci_ids/i915_pci_ids.h|4 ++-- src/mesa/drivers/dri/i915/i830_texstate.c |3 +-- src/mesa/drivers/dri/intel/intel_screen.c |4 src/mesa/drivers/dri/intel/intel_screen.h |2 +- 4 files changed, 8 insertions(+), 5 deletions(-) diff --git a/include/pci_id

[Intel-gfx] [PATCH 13/16] intel: Replace IS_G4X macro with an is_g4x bit in the chipset struct

--- src/mesa/drivers/dri/intel/intel_chipset.h |9 - src/mesa/drivers/dri/intel/intel_context.c |2 +- src/mesa/drivers/dri/intel/intel_screen.c |1 + src/mesa/drivers/dri/intel/intel_screen.h |2 +- 4 files changed, 3 insertions(+), 11 deletions(-) diff --git a/src/mesa

[Intel-gfx] [PATCH 12/16] intel: Drop unused IS_SNB/IVB_GT1/2 macros

--- src/mesa/drivers/dri/intel/intel_chipset.h | 16 1 files changed, 0 insertions(+), 16 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index 979cd0b..e8bb3fe 100644 --- a/src/mesa/drivers/dri/intel/intel_chip

[Intel-gfx] [PATCH 11/16] intel: Put urb and thread limits into the chipset struct

--- src/mesa/drivers/dri/i965/brw_context.c | 53 - src/mesa/drivers/dri/intel/intel_screen.c | 46 + src/mesa/drivers/dri/intel/intel_screen.h |7 3 files changed, 53 insertions(+), 53 deletions(-) diff --git a/src/mesa/drivers/d

[Intel-gfx] [PATCH 10/16] intel: Drop unused IS_GEN5-7 macros

--- src/mesa/drivers/dri/intel/intel_chipset.h | 10 -- src/mesa/drivers/dri/intel/intel_context.c |6 +++--- 2 files changed, 3 insertions(+), 13 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index 3e11f64..979cd0

[Intel-gfx] [PATCH 09/16] intel: Drop unused IS_GEN4 macro

--- src/mesa/drivers/dri/intel/intel_chipset.h |8 1 files changed, 0 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index ca386b5..3e11f64 100644 --- a/src/mesa/drivers/dri/intel/intel_chipset.h +++

[Intel-gfx] [PATCH 08/16] intel: Replace single use of IS_965 with gen check

--- src/mesa/drivers/dri/intel/intel_chipset.h |6 -- src/mesa/drivers/dri/intel/intel_context.c |2 +- 2 files changed, 1 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index 37239fc..ca386b5 100644

[Intel-gfx] [PATCH 06/16] intel: Add a is_945 bit to chipinfo and use that instead of IS_945

--- src/mesa/drivers/dri/intel/intel_chipset.h |7 --- src/mesa/drivers/dri/intel/intel_context.c |8 +++- src/mesa/drivers/dri/intel/intel_screen.c |2 +- src/mesa/drivers/dri/intel/intel_screen.h |1 + 4 files changed, 5 insertions(+), 13 deletions(-) diff --git a/src/

[Intel-gfx] [PATCH 07/16] intel: Remove unused IS_MOBILE and IS_IGD* macros

--- src/mesa/drivers/dri/intel/intel_chipset.h | 14 -- 1 files changed, 0 insertions(+), 14 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index 66f14fd..37239fc 100644 --- a/src/mesa/drivers/dri/intel/intel_chipse

[Intel-gfx] [PATCH 05/16] intel: Replace intel_screen::gen with the chipset struct

--- src/mesa/drivers/dri/intel/intel_context.c |2 +- src/mesa/drivers/dri/intel/intel_screen.c | 14 +- src/mesa/drivers/dri/intel/intel_screen.h |6 +- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/m

[Intel-gfx] [PATCH 04/16] intel: Remove unused IS_915 macro

--- src/mesa/drivers/dri/intel/intel_chipset.h |4 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index 6c82e4d..5d4aaab 100644 --- a/src/mesa/drivers/dri/intel/intel_chipset.h +++ b/s

[Intel-gfx] [PATCH 03/16] intel: IS_9XX is just gen >= 3

--- src/mesa/drivers/dri/intel/intel_chipset.h |4 src/mesa/drivers/dri/intel/intel_context.c |2 +- src/mesa/drivers/dri/intel/intel_screen.c | 10 -- 3 files changed, 5 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/dri

[Intel-gfx] [PATCH 02/16] intel: Use the PCI ID map for determining chipset gen

--- src/mesa/drivers/dri/i915/Makefile|2 +- src/mesa/drivers/dri/i965/Makefile|2 +- src/mesa/drivers/dri/intel/intel_screen.c | 96 +++-- 3 files changed, 80 insertions(+), 20 deletions(-) diff --git a/src/mesa/drivers/dri/i915/Makefile b/src/m

[Intel-gfx] [PATCH 01/16] intel: Use gen number instead of PCI ID in decoder

--- src/mesa/drivers/dri/intel/intel_batchbuffer.c |2 +- src/mesa/drivers/dri/intel/intel_chipset.h |3 -- src/mesa/drivers/dri/intel/intel_decode.c | 42 src/mesa/drivers/dri/intel/intel_decode.h |2 +- 4 files changed, 23 insertions(+), 26 de

[Intel-gfx] [PATCH 00/16] Move chipset specific stuff to struct intel_chipset

Hi, Here's a handful of patches that try to replace most of our chipset feature checking with data in a new struct intel_chipset. It uses the new PCI ID list infrastructure and eliminates all IS_FOO macros in favor of a per-family chipset info struct. Actually, I was surprised how much in the dr

Re: [Intel-gfx] [PATCH] drm/i915: Revert i915.semaphore=1 default from 47ae63e0

On Thu, 19 May 2011 16:50:00 -0400, Andrew Lutomirski wrote: > On Thu, May 19, 2011 at 3:56 PM, Keith Packard wrote: > > On Fri, 13 May 2011 12:14:54 -0400, Andy Lutomirski wrote: > > > >> My Q67 / i7-2600 box has rev09 Sandy Bridge graphics.  It hangs > >> instantly when GNOME loads and it hang