I think you don't need libva for drive , you need for players like
mplayer or vlc .
http://intellinuxgraphics.org/vaapi.html
On Fri, 2011-06-03 at 13:57 +0530, Thirunavukkarasu S wrote:
> Thanks Hai & Sergio, the package got installed.
> FYI, I am using Ubuntu 11.04
>
>
> But after installat
On Sat, 04 Jun 2011 00:09:29 +0100, Chris Wilson
wrote:
> I need to address the broader concerns raised by Jean Delvare first.
> Once I have our i2c adapter to his liking, I can then get the code to
> yours.
Sounds good.
--
keith.pack...@intel.com
pgpKkPpmnhIG5.pgp
Description: PGP signatur
On Fri, 03 Jun 2011 13:55:10 -0700, Keith Packard wrote:
> On Fri, 13 May 2011 08:00:40 -0700, Keith Packard wrote:
> Non-text part: multipart/signed
> > On Fri, 13 May 2011 10:28:34 +0100, Chris Wilson
> > wrote:
> >
> > > And how about something like:
> > >
> > > #define I915_GMBUS_WRITE(re
On Fri, 3 Jun 2011 12:20:18 -0700
Eric Anholt wrote:
> Here's what I've been talking about on IRC today. Patch 3 appears to
> make things work. Patch 4 should work, but re-breaks things (hangs
> but no dmesg complaints). I want to understand why, but I'm running
> out of theories. Perhaps th
On Thu, 12 May 2011 22:17:22 +0100, Chris Wilson
wrote:
> ... as they only had a single PCI-ID each, and so using the pci-id is
> easier than using a capability bit.
This patch no longer applies; do you want to update it?
--
keith.pack...@intel.com
pgpo9QUs6APPl.pgp
Description: PGP signatu
On Thu, 12 May 2011 22:17:17 +0100, Chris Wilson
wrote:
> Toggle the Software Clear Interrupt bit which resets the controller to
> clear any prior BUS_ERROR condition before we begin to use the
> controller in earnest.
I don't have a new patch with corrected register referencing yet...
--
kei
On Fri, 13 May 2011 08:00:40 -0700, Keith Packard wrote:
Non-text part: multipart/signed
> On Fri, 13 May 2011 10:28:34 +0100, Chris Wilson
> wrote:
>
> > And how about something like:
> >
> > #define I915_GMBUS_WRITE(reg, val) \
> >I915_WRITE(intel_gmbus_reg(dev_priv->dev, reg), val)
> >
Our wait-on-interrupts path goes:
I915_WRITE(IMR, enabled_val)
POSTING_READ(IMR);
if (!i915_gem_seqno_passed())
sleep();
However, the IMR write can still be queued in the GT FIFO even after
the POSTING_READ, since the GT FIFO isn't implementing PCI semantics.
Yay. So, when we're doing a POSTI
This reintroduces the IRQ misses, with 2 events in 1874 runs.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/i915/i915_drv.c | 16 +++-
1 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index eabf82c..5
The BSpec says that the GTIMR is not to be used for masking
interrupts. Regardless, writing one register should be better than
writing two registers.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/i915/i915_irq.c | 19 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 32 +
We have forcewake in the interrupt handler in the following commit, so
we have to use a spinlock instead of a mutex.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/i915/i915_debugfs.c |3 +--
drivers/gpu/drm/i915/i915_dma.c |1 +
drivers/gpu/drm/i915/i915_drv.c | 17 +++
Here's what I've been talking about on IRC today. Patch 3 appears to
make things work. Patch 4 should work, but re-breaks things (hangs
but no dmesg complaints). I want to understand why, but I'm running
out of theories. Perhaps there's some period of time where a write
has been PCI write poste
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