Here's what I've been talking about on IRC today. Patch 3 appears to make things work. Patch 4 should work, but re-breaks things (hangs but no dmesg complaints). I want to understand why, but I'm running out of theories. Perhaps there's some period of time where a write has been PCI write posted but has not yet appeared in the GT FIFO? Or perhaps there's some time after GT FIFO but before it's really handled by hardware? Note that I was also able to fix the problem without this series by just POSTING_READing 4 times instead of 1.
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