Hi,
I want to include a file only if it is existed. Is there something in gmake
that can do this?
Thanks,
Peng
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#else
VAR1 = bla bla
VAR2 = bla bla
#endif
Thanks,
Peng
On Tue, May 20, 2008 at 5:28 PM, Peng Yu <[EMAIL PROTECTED]> wrote:
> Hi Philip,
>
> I missed that part. Now I see that I should use -include.
>
> Thanks,
> Peng
>
>
> On Tue, May 20, 2008 at 5:24 PM, Philip Gue
Hi,
For a file named as abc+=.cc, how do I refer to such name in Makefile?
I tried to abc\+\=.cc, but it seems not working.
Thanks,
Peng
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On Wed, Jun 4, 2008 at 6:50 AM, John Graham-Cumming <[EMAIL PROTECTED]> wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> Peng Yu wrote:
> | For a file named as abc+=.cc, how do I refer to such name in Makefile?
> | I tried to abc\+\=.cc, but it seems not
Hi,
I want to include a file only once use the technique that is commonly
used in any C++ include files, such as
#ifndef FILENAME_H
#define FILENAME_H
#endif
Could you let me know how to do the similar thing in gnu make?
Thanks,
Peng
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Hi,
I have the following Makefile. The execution result is shown below.
CXX_SOURCE_FILES is an empty string. I think that the top branch
should be taken. But in fact, the bottom one is taken.
Would you please let me know what I'm wrong?
Thanks,
Peng
$ cat Makefile
.PHONY: all
CXX_SOURCE_FILE
Hi,
Suppose I have the following Makefiles.
Makefile_leaf1, Makefile_node1, Makefile_node2, Makefile_node3
Makefile_leaf1 is included by Makefile_node1 and Makefile_node2. Both
Makefile_node1 and Makefile_node2 are included by Makefile_node3.
Is there an automatically way to know that Makefile_
Hi,
I used the following to test if the the goal is 'all'. Now, I want to
test whether it is either 'all' or 'o'. I'm wondering how to do it in
makefile.
ifeq ($(MAKECMDGOALS), all)
Thanks,
Peng
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Hi,
The code in the attachment won't compile. If I use g++ directly as in
the following command, I would end up with some error output.
g++ -Wall -W -pedantic -g -c -o main-g.o main.cc
But if I use make which calls g++, cc1plus would take much more
resource to almost halt the system. Can someb
Hi,
I want to use the uncommented line rather than the commented line.
#SUBDIRS = $(shell find . -mindepth 1 -maxdepth 1 -type d ! -name
'backup' ! -name 'bash')
SUBDIRS = $(shell compgen -d -X 'backup' -X 'bash')
But make gives me "make: compgen: Command not found". I'm wondering
how to use she
On Wed, Oct 22, 2008 at 8:13 AM, Paul Smith <[EMAIL PROTECTED]> wrote:
> On Wed, 2008-10-22 at 07:57 -0500, Peng Yu wrote:
>> I want to use the uncommented line rather than the commented line.
>>
>> #SUBDIRS = $(shell find . -mindepth 1 -maxdepth 1 -type d ! -nam
On Wed, Oct 22, 2008 at 8:48 AM, Paul Smith <[EMAIL PROTECTED]> wrote:
> On Wed, 2008-10-22 at 08:24 -0500, Peng Yu wrote:
>> The reason that I want to use 'compgen' rather than 'find' is that I
>> think it is faster than 'find', since it's a
> It probably is marginally faster. I doubt, for this situation, whether
> it will make a noticeable difference (especially if you change the =
> to := as I suggested... that will make MUCH more difference to
> performance). Of course there's only one way to know: measure it. In
> general it's q
Hi,
I have the following files in a directory.
main.cpp Makefile print.hpp
The content of each file is listed below this message.
After I run make, I will get main.cpp compiled and the file '.dep'
will be generated. The content of .dep will be
main.o: main.cpp print.hpp
Now, I change .dep ma
On Thu, Oct 23, 2008 at 8:59 PM, Greg Chicares <[EMAIL PROTECTED]> wrote:
> On 2008-10-23 23:49Z, Peng Yu wrote:
> [...issues with generating dependency files]
>
> http://make.paulandlesley.org/autodep.html
Are you referring to this section?
Avoiding ``No rule to make target ...
On Fri, Oct 24, 2008 at 12:53 PM, Philip Guenther <[EMAIL PROTECTED]> wrote:
> On Thu, Oct 23, 2008 at 10:45 PM, Peng Yu <[EMAIL PROTECTED]> wrote:
> ...
>> I'm not sure how to adapt it to my problem, as my problem arises when
>> the dependence file is modified
On Fri, Oct 24, 2008 at 2:29 PM, Peng Yu <[EMAIL PROTECTED]> wrote:
> On Fri, Oct 24, 2008 at 12:53 PM, Philip Guenther <[EMAIL PROTECTED]> wrote:
>> On Thu, Oct 23, 2008 at 10:45 PM, Peng Yu <[EMAIL PROTECTED]> wrote:
>> ...
>>> I'm not sure how
On Fri, Oct 24, 2008 at 12:45 AM, Peng Yu <[EMAIL PROTECTED]> wrote:
> On Thu, Oct 23, 2008 at 8:59 PM, Greg Chicares <[EMAIL PROTECTED]> wrote:
>> On 2008-10-23 23:49Z, Peng Yu wrote:
>> [...issues with generating dependency files]
>>
>> http://make.pau
Hi,
I have the following code. I'm wondering how to put them together into
one if statement?
ifeq ($(MAKECMDGOALS), all)
-include .dep
endif
ifeq ($(MAKECMDGOALS), )
-include .dep
endif
Thanks,
Peng
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On Fri, Oct 24, 2008 at 4:37 PM, Philip Guenther <[EMAIL PROTECTED]> wrote:
> On Fri, Oct 24, 2008 at 1:59 PM, Peng Yu <[EMAIL PROTECTED]> wrote:
>> I have the following code. I'm wondering how to put them together into
>> one if statement?
>>
>>
On Fri, Oct 24, 2008 at 4:58 PM, Philip Guenther <[EMAIL PROTECTED]> wrote:
> On Fri, Oct 24, 2008 at 1:45 PM, Peng Yu <[EMAIL PROTECTED]> wrote:
> ...
>> I guess. I figure out how to use it. See below for the source code and
>> the Makefile. After running make
On Sat, Oct 25, 2008 at 2:29 AM, Sam Ravnborg <[EMAIL PROTECTED]> wrote:
> On Fri, Oct 24, 2008 at 07:00:41PM -0500, Peng Yu wrote:
>> On Fri, Oct 24, 2008 at 4:37 PM, Philip Guenther <[EMAIL PROTECTED]> wrote:
>> > On Fri, Oct 24, 2008 at 1:59 PM, Peng Yu <[EMAI
> Here's a correct, *tested* makefile:
>
> .PHONY: all clean
>
> SRC = main.cpp
> COMPILE.cpp += -MMD -MP
>
> all: main.exe
>
> main.exe : main.o
>$(LINK.cpp) $< $(LOADLIBES) $(LDLIBS) -o $@
>
> -include $(SRC:.cpp=.d)
>
> clean:
>@$(RM) *.o *.exe *.d
>
This works
Hi,
Suppose there are many subdirectories in a directory. The sub dirs all
have working makefiles.
'make -j3' in the parent dir would parallel make all directories. But
'make clean -j3' could not. The problem is that I don't know how to
clean each directory as well as deleting the file '.d'.
Can
- Hide quoted text -
On Sat, Oct 25, 2008 at 11:23 AM, Sam Ravnborg <[EMAIL PROTECTED]> wrote:
> On Sat, Oct 25, 2008 at 11:06:45AM -0500, Peng Yu wrote:
>> On Sat, Oct 25, 2008 at 10:43 AM, Sam Ravnborg <[EMAIL PROTECTED]> wrote:
>> > On Sat, Oct 25, 2008 at 0
Hi,
In parallel mode (with -j option), the outputs from different rules
are intermixed. I'm wondering if there is a way to order the outputs
as if make is run in serial mode, but it should still achieve the
speed of parallel mode.
Thanks,
Peng
___
Hel
Hi,
I am wondering if there is a way to get the path of the directory
where a makefile is in (either the absolute path or the relative path
to the current directory). Can somebody help me?
Regards,
Peng
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htt
On Sun, May 3, 2009 at 7:03 PM, Philip Guenther wrote:
> On Sun, May 3, 2009 at 9:52 AM, Peng Yu wrote:
>> I am wondering if there is a way to get the path of the directory
>> where a makefile is in (either the absolute path or the relative path
>> to the current directory).
Suppose that I have the following Makefile, I have to have the first
rule in order to update all the other rules in the Makefile. Since I
want execute all the rules in the Makefile, I'm wondering if it is
possible to make the first rule implicit, so that I don't have to
write it in the Makefile.
.
Is there way to specify a dependence on a directory?
directory: somefile
some_command
If any file in 'directory' is older than 'somefile', then I want to
run 'some_command'. I'm wondering how to do this.
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On Fri, Nov 20, 2009 at 5:11 PM, David Boyce wrote:
> On Fri, Nov 20, 2009 at 5:42 PM, Peng Yu wrote:
>> Is there way to specify a dependence on a directory?
>>
>> directory: somefile
>> some_command
>>
>> If any file in 'directory' is older tha
On Fri, Nov 20, 2009 at 6:15 PM, John Calcote wrote:
> On 11/20/2009 4:18 PM, Peng Yu wrote:
>>
>> On Fri, Nov 20, 2009 at 5:11 PM, David Boyce wrote:
>>
>>>
>>> On Fri, Nov 20, 2009 at 5:42 PM, Peng Yu wrote:
>>>
>>>&
On Fri, Nov 20, 2009 at 8:26 PM, Paul Smith wrote:
> On Fri, 2009-11-20 at 18:50 -0600, Peng Yu wrote:
>> But I don't want to explicitly specify the files, because I might
>> change 'some_command' to generate different files. I don't want to
>> modify M
$< refers to the first prerequisite. How to refer to the first target?
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$(wildcard *.py)
Suppose that I have the above list of file names. I want to replace
any .py file by the coresponding .sh file if it exists.
That is,
If I have the following files,
a.py a.sh b.py
I want to get the following files
a.sh b.py
Could somebody show me how to do it?
_
I have the following makefile. I thought that 'a.y' and 'b.y' should
be printed. But it is not. What is the problem?
$ ls
a.x b.x Makefile
$ cat Makefile
.PHONY: all
Y_FILES=$(patsubst %x,%y,$(wildcard *.x))
.PHONY: $(Y_FILES)
all: $(Y_FILES)
%.y: %.x
echo $@
$ make
make: Nothing to
$< gives the first prerequisite. I'm wondering how to get the 2nd,
3rd, ..., prerequisite.
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On Mon, Nov 23, 2009 at 10:58 PM, Paul Smith wrote:
> On Mon, 2009-11-23 at 22:13 -0600, Peng Yu wrote:
>> $< refers to the first prerequisite. How to refer to the first target?
>
> Not sure what you mean: generally there is only one target.
>
> If you mean in a pattern r
On Wed, Nov 25, 2009 at 11:01 PM, Paul Smith wrote:
> On Wed, 2009-11-25 at 19:59 -0600, Peng Yu wrote:
>> Suppose I have 'command.sh' that generate files 'a' and 'b'.
>>
>> If either of 'a' or 'b' is older than 'comm
Supposed I have some makefile is included in my Makefile.
include something.makefile
There is a directory called 'some_dir' in the current directory.
I want to 'make -C some_dir' after all the rules in something.Makefile
has been executed. Is there a way to added this information in the
Makefile
On Thu, Nov 26, 2009 at 10:03 AM, Eli Zaretskii wrote:
>> Date: Thu, 26 Nov 2009 07:42:33 -0600
>> From: Peng Yu
>>
>> > a: command.sh
>> > ./command.sh
>> > b: command.sh
>> > ./command.sh
>>
On Thu, Nov 26, 2009 at 3:44 PM, Allan Odgaard
<682e7718-3533-4fed-af3b-cd0d7e604...@uuid-mail.com> wrote:
> On 26 Nov 2009, at 22:29, Peng Yu wrote:
>
>>> [...]
>>
>> This solution seems awkward to me. There maybe not be a good pattern that
>> catch bo
Suppose I want to download the file http://some_website/some_file
whenever it is newer than the local file. This needs the specification
of the dependency on URLs. I'm wondering if it is possible to do so in
gnu make.
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On Fri, Dec 4, 2009 at 8:37 AM, Allan Odgaard
<682e7718-3533-4fed-af3b-cd0d7e604...@uuid-mail.com> wrote:
> On 4 Dec 2009, at 14:19, Peng Yu wrote:
>
>> Suppose I want to download the file http://some_website/some_file
>> whenever it is newer than the local file. This needs
GraphViz can be used to plot a graph. I'm wondering if there is a easy
way to generate dependency graph (exported to a figure that can be
visualized) for a Makefile.
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On Fri, Dec 4, 2009 at 10:00 AM, Peng Yu wrote:
> On Fri, Dec 4, 2009 at 8:37 AM, Allan Odgaard
> <682e7718-3533-4fed-af3b-cd0d7e604...@uuid-mail.com> wrote:
>> On 4 Dec 2009, at 14:19, Peng Yu wrote:
>>
>>> Suppose I want to download the file http://some_web
I have the following two files. Whenever I call 'make', 'gzip' will be
called again. I'm wondering what is the correct way to write the
makefile such that gzip will not be called as long as test.txt.gz is
newer than test.sh.
$ cat Makefile
.PHONY: all
all: test.txt.gz
test.txt.gz: test.txt
On Sat, Dec 26, 2009 at 9:53 PM, Philip Guenther wrote:
> On Sat, Dec 26, 2009 at 6:59 PM, Peng Yu wrote:
>> I have the following two files. Whenever I call 'make', 'gzip' will be
>> called again. I'm wondering what is the correct way to write the
>>
Suppose that I have the following two variables A and B. I want to
compute the union and the intersection of them, which are 'a b c d'
and 'b c' respectively.
A = a b c
B = b c d
I don't find 'union' and 'intersection' in the manual. Could somebody
let me know how to do it in gnu make?
On Wed, Dec 30, 2009 at 5:50 PM, Sam Ravnborg wrote:
> On Thu, Dec 31, 2009 at 02:17:53PM +1800, Peng Yu wrote:
>> Suppose that I have the following two variables A and B. I want to
>> compute the union and the intersection of them, which are 'a b c d'
>> and
On Thu, Dec 31, 2009 at 10:51 AM, David Boyce wrote:
> On Thu, Dec 31, 2009 at 10:14 AM, Peng Yu wrote:
>> On Wed, Dec 30, 2009 at 5:50 PM, Sam Ravnborg wrote:
>>> union = $(sort $(A) $(B))
>>> intersection = $(filter $(A), $(B))
>>>
>>> I did not t
Is a way to define functions in gnu make? Some operations might need
multiple functions. It might be better to define user functions for
these operations.
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I don't find where in the R document the discussion of nested
namespace is. If there is nested namespace supported in R, could
somebody let me know whether the document is?
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Suppose I have multiple rules for a target. For example, I have
all: file1.txt
all: file2.txt
all: filen.txt
Is there a way to get all the dependences (i.e., file1.txt ...
filen.txt) in gnu make? For example, to delete all the dependent
files.
clean:
rm
___
I run $(filter ) with each argument of thousands of strings. It runs
slow. I'm wondering what the run time complexity of $(filter ) is.
Suppose I have n strings for each argument. Is the run time complexity
n*n or log(n)?
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On Fri, Jan 8, 2010 at 12:34 PM, Paul Smith wrote:
> On Sat, 2010-01-09 at 11:33 +1800, Peng Yu wrote:
>> I run $(filter ) with each argument of thousands of strings. It runs
>> slow. I'm wondering what the run time complexity of $(filter ) is.
>> Suppose I have n str
On Mon, Nov 23, 2009 at 11:01 PM, Paul Smith wrote:
> On Fri, 2009-11-20 at 22:10 -0600, Peng Yu wrote:
>> I want the rule to run if there is no such a directory, or there are
>> no files in the directory, or there is any file that is older than the
>> dependent files.
>
&
On Sun, Jan 10, 2010 at 11:02 AM, Paul Smith wrote:
> On Sun, 2010-01-10 at 10:22 -0600, Peng Yu wrote:
>> The code that you suggested is not working properly, when make is
>> called the second time. Would you please take a look at how to fix it?
>
>> $ cat Makefile
On Sun, Jan 10, 2010 at 2:59 PM, Peng Yu wrote:
> On Sun, Jan 10, 2010 at 11:02 AM, Paul Smith wrote:
>> On Sun, 2010-01-10 at 10:22 -0600, Peng Yu wrote:
>>> The code that you suggested is not working properly, when make is
>>> called the second time. Would you pleas
target: a b c d
some_command_whose_argument_order_mattters a b c d
Suppose I have the above rule, I want to reduce it to the following.
But I'm wondering if $^ preserve the order of the prerequisites.
Could somebody let me know?
target: a b c d
some_command_whose_argument_order_mattters $^
On Wed, Jan 27, 2010 at 3:30 AM, Oleksandr Gavenko wrote:
> On 2010.01.25 17:41, Peng Yu wrote:
>>
>> target: a b c d
>> some_command_whose_argument_order_mattters a b c d
>>
>> Suppose I have the above rule, I want to reduce it to the following.
>> But
I can use 'find' to get all the files with certain suffix recursively.
Would you please let me know if there is a buildin way to do so with
$(wildcard)?
find . -name '*.txt'
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Suppose that I use the following rule pattern a lot in my makefile,
where has to be the same in each block of the three rules.
... can be any files.
all: .RData
clean: .RData
$(RM) $^
.RData: .R ...
Rscript $<
For example, I might have a makefile that has the following r
I have the following makefile, by which I want it to touch the current
directory if the file 'a' is changed. It seems to be working. But I
want to make sure if '.' has some special meaning in make (by simply
looking though the index, I don't find any special meaning). Could
somebody let me know?
$
On Tue, Feb 2, 2010 at 1:13 AM, Philip Guenther wrote:
> On Monday, February 1, 2010, Paul Smith wrote:
> ...
>> define special-rule
>> all: $1.RData
>>
>> clean $1.RData
>> $$(RM) $$^
>>
>> $1.RData: $1.R $2 $3 $4 $5 $6 $7 $8 $9
>> Rscript $$<
>> enddef
>>
>> $(eval $(call specia
On Thu, Feb 4, 2010 at 7:29 PM, Philip Guenther wrote:
> On Tue, Feb 2, 2010 at 5:58 AM, Peng Yu wrote:
>> On Tue, Feb 2, 2010 at 1:13 AM, Philip Guenther wrote:
> ...
>>> Why do the dependencies need to be separate arguments to the macro and
>>> not just one
On Thu, Feb 4, 2010 at 11:34 PM, Paul Smith wrote:
> On Tue, 2010-02-02 at 07:58 -0600, Peng Yu wrote:
>> That is because I want to keep everything related to a RData file
>> close to each other. Otherwise, I have changed multiple distant places
>> in a Makefile. When t
Suppose I have file2 that is newer than file1, and file4 is older than
file3. In the trials that I did, both rules in the makefile are always
executed. I'm wonder if this is always true. Or I just happen to
observer this behavior?
.PHONY: all
all: file1 file2
file3: file4
touch file3
f
On Thu, Mar 4, 2010 at 6:39 PM, Paul Smith wrote:
> On Thu, 2010-03-04 at 17:41 -0600, Peng Yu wrote:
>> Suppose I have file2 that is newer than file1, and file4 is older than
>> file3. In the trials that I did, both rules in the makefile are always
>> executed. I'm won
I can call 'make -C directory' to update the directory 'directory'.
However, the makefile in 'directory' might in turn call 'make -C
subdirectory', which calls 'make -C subsubdirectory' and so on. I'm
wondering if there is a straight-forward and automatic way to get
whether there is any file that h
TXT:=a b c
Suppose I have the above set of strings, could somebody show me how to
convert it to the string a,b,c?
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Hi,
I have the following makefile. The first echo statement doesn't print
anything (just an empty line), the second echo print the path
correctly. Could you let me know what is the correct way to get
$HOSTNAME in a makefile?
$ cat Makefile
.PHONY: all
TMP:=$(HOSTNAME)
TMP1:=$(PWD)
all:
I want to add something to a number of string in the middle but not at
the ends. I made the following example (doesn't work). Could you
please let me know what is the most convenient to add something to the
middle of a number strings?
.PHONY: all
PDF=uuu/vvv.pdf xxx/yyy.pdf
TMP=$(patsubst %/%.pdf
I want assigned the variable something in shell some value and then echo it.
.PHONY: all
all:
something=$(shell basename abc.txt .txt)
echo $(something)
echo $$(something)
But the above code doesn't work. Would you please let me know what the
cor
On Thu, Nov 26, 2009 at 3:44 PM, Allan Odgaard
<682e7718-3533-4fed-af3b-cd0d7e604...@uuid-mail.com> wrote:
> On 26 Nov 2009, at 22:29, Peng Yu wrote:
>
>>> [...]
>>
>> This solution seems awkward to me. There maybe not be a good pattern that
>> catch bo
Hi,
I have the following two Makefiles. The difference between them are
that the commands are not the same. I don't understand why both rules
are executed in /tmp/double_targets_different_command and why only one
rule (always a, no matter what the order between a and b) is executed
in /tmp/double_
On Mon, Apr 26, 2010 at 6:40 AM, Paul Smith wrote:
> On Sun, 2010-04-25 at 15:13 -0500, Peng Yu wrote:
>
>> /tmp/double_targets_same_command$ make
>> a
>> echo 'a' > a; sleep 1; echo 'b' > b
>
> Here one command (the one for building "
I need to define many rules like RData_rule, png_rule, csv_rule,
Is there a way to define a macro that can define these rules (with the
parameter like RData and png)?
define RData_rule
TARGET:=$(patsubst %.R,%.RData,$1)
all: $$(TARGET)
$$(TARGET): $1 $2 $3 $4 $5 $6 $7 $8
Rscript $$<
On Sat, May 1, 2010 at 5:52 PM, Stephan Beal wrote:
> On Sun, May 2, 2010 at 12:08 AM, Peng Yu wrote:
>>
>> I need to define many rules like RData_rule, png_rule, csv_rule,
>>
>> Is there a way to define a macro that can define these rules (with the
>
On Sat, May 1, 2010 at 8:20 PM, Stephan Beal wrote:
> On Sun, May 2, 2010 at 2:11 AM, Peng Yu wrote:
>>
>> I don't understand the above code. Would you give me the minimal code
>> for the scenario that mentioned in my first email?
>
> Sorry, but i thought that
Hi,
-I can be used to specify where to search for included file. Could you
please let me know if there is an environment variable that I can
specify such that make will search in the paths specified in that
environment variable?
--
Regards,
Peng
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TXT=a b c
I have the above variable. I want convert $(TXT) to the string "a,b,c"
(without the quote). Would you please let me know if it is possible in
make?
--
Regards,
Peng
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I have the following Makefile to extract tar files. However, it will
always extract all the tar files. I could add touch $@ after tar xzvf
$<. But I prefer not to do so. Because I don't want change the date of
the extracted package.
I'm wondering if there is any walkaround to not to update these r
Hi,
I want to get all the directories. But $(wildcard ) only doesn't work.
I have to use $(filter) to filter the result. Is there any better way
in doing this?
$ ll -go
total 4
-rw--- 1 0 2010-06-09 11:27 a.txt
-rw--- 1 85 2010-06-09 11:29 Makefile
drwx-- 2 6 2010-06-09 11:28 x.txt
Hi,
I have the same make file in two directories. One directory has files
with long file names (with '_' and '-' in the file name). The other
directory has files with short files names. The makefile works in the
latter directory but not the former. I have no clue what is wrong.
Would you please he
On Wed, Jun 9, 2010 at 2:08 PM, Stephan Beal wrote:
> On Wed, Jun 9, 2010 at 6:48 PM, Peng Yu wrote:
>
> $(DIFF_BL2SEQ): %.diff.bl2seq: %.megablast.bl2seq %.blastn.bl2seq
> diff $^ > $@
>
>>
>> -rw--- 1 807 2010-06-09 11:34
>> HWI-EAS11X_10097
On Wed, Jun 9, 2010 at 3:28 PM, Paul Smith wrote:
> On Wed, 2010-06-09 at 11:32 -0500, Peng Yu wrote:
>> I want to get all the directories. But $(wildcard ) only doesn't work.
>> I have to use $(filter) to filter the result. Is there any better way
>> in doing this?
On Wed, Jun 9, 2010 at 6:57 PM, Paul Smith wrote:
> On Wed, 2010-06-09 at 17:25 -0500, Peng Yu wrote:
>> No. It doesn't work.
>> $ make
>> echo ./ *.txt/
>> ./ x.txt/
>> $ cat Makefile
>> .PHONY: all
>>
>> all:
>> echo $(dir (w
Hello,
By the test that I run, I think that $(CPP_FILES:.cpp=.d) is
equivalent to $(patsubst %.cpp,%.d,$(CPP_FILES)). But I don't find
where it is documented. Would you please point me where the document
is?
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Regards,
Peng
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Hello,
I don't find these two variables defined in the manual. Could you let
me know where they are documented?
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Peng
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-s will suppress all the output. But I still want to see what command
are executed. Is there a way to suppress only Entering directory...
and Leaving directories? (make -C is used).
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Peng
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Hi,
I have some makefile that should not be run with multiple process even
if -j or -j option is specified. Is there a way to disable -j or
-j in a makefile?
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Peng
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My problem is that I have a number of files to be splitted. Then I
want to add a suffix to each file.
According to the manual, targets are always immediate. I think that
probably secondexpansion may help in this case. But I'm not clear how
to apply it to my case below. Would you please show me?
On Tue, Jun 15, 2010 at 10:58 PM, Peng Yu wrote:
> My problem is that I have a number of files to be splitted. Then I
> want to add a suffix to each file.
>
> According to the manual, targets are always immediate. I think that
> probably secondexpansion may help in this case. Bu
Hi,
I don't get the what strip is for. In particular how "Replacing the
variable reference `$(needs_made)' with the function call `$(strip
$(needs_made))' in the ifneq directive would make it more robust"
(from the manual). I tries to add two consecutive spaces in a
variable. But I failed. Could
On Thu, Jul 8, 2010 at 5:10 PM, Paul Smith wrote:
> On Thu, 2010-07-08 at 16:49 -0500, Peng Yu wrote:
>> I don't get the what strip is for. In particular how "Replacing the
>> variable reference `$(needs_made)' with the function call `$(strip
>> $(needs_made))
Hi,
I want to have filenames with ':' in Makefile. Simply adding '\'
before ':' doesn't work. I have grepped the manual by ':'. But there
are two many ':'s, I can't see where it mentiones how ':' is escaped.
Could you please let me know how to escape ':' in a Makefile?
.PHONY: all
all: a\:b.txt
Hi,
GNU Make use time stamp to determine whether target should be updated
or not. But SCons has some other way (say MD5) to determine if a
target should be updated. I don't see a way to customize GNU Make in
this aspect. But I may miss something. Could anybody confirm with me
if this is customizab
Hi
$(dir somevariable) gives the directory but with a trailing '/'. I
could use $(patsubst ) to remove the trailing '/'. But I'm wondering
what is the best way to get the dir without the trailing character in
GNU Make?
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Peng
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Hi,
My questions is how to more efficiently run make in hierarchy of
directories. Let me give the following example to demonstrate what I
mean.
I have the following two directories leaf/ and internal/, each of
which has a Makefile as shown below. Note that the targets in leaf/
don't depend any fi
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