On Thu, Nov 26, 2009 at 10:03 AM, Eli Zaretskii <e...@gnu.org> wrote: >> Date: Thu, 26 Nov 2009 07:42:33 -0600 >> From: Peng Yu <pengyu...@gmail.com> >> >> > a: command.sh >> > ./command.sh >> > b: command.sh >> > ./command.sh >> > >> > So, in this case, there is only one target file each time command.sh is >> > invoked, and the name of that target will be stored in $...@. So the first >> > time command.sh is invoked, $@ will be set to "a" and the second time it >> > will be set to "b". >> >> I don't understand the following case. If there are two rules, why >> command.sh is only executed once. >> >> $ touch command.sh >> $ make >> ./command.sh > > Because by default, Make only builds the first target in the Makefile, > in this case a. Try this, and you should see 2 invocations of > command.sh: > > $ touch command.sh > $ make a b > >> If there are multiple files that are generated by command.sh, are you >> suggesting to write a single rule for an arbitrarily chosen single >> file? But if I only have a rule for 'a' but not for 'b', when the file >> 'b' is deleted, 'command.sh' will not called by make. But I do want >> make to updated 'b'. How do you deal with this case? > > The only way AFAIK is to use static pattern rules, and come up with a > pattern that will catch both a and b, but nothing else.
This solution seems awkward to me. There maybe not be a good pattern that catch both a and b. Should gnu make have a more natural solution to this problem? _______________________________________________ Help-make mailing list Help-make@gnu.org http://lists.gnu.org/mailman/listinfo/help-make
