Hi All,
I've a question that I am not too clear about. When the simulation
first starts, are all the initial memory operations (load and stores)
treated as misses because the cache is cold? for all levels of cache?
therefore it must access main memory?
Sorry for such a newbie question but
Hi All,
I am currently trying to understand the cache trace for L2. I don't
quite understand how the write request are handled. From the trace I
can see ReadReq and ReadExReq. They are either miss or hits. However,
I don't see any trace for 'writes' only see 'writebacks'. What are the
mea
Hi Nilay,
Thanks for your reply. So when L1 is replacing a dirty cache block, L2
receives a writeback request. Now if the cache block exists in L2,
then we have a writeback hit? and if not we have a writeback miss?
Then what is the meaning of "replacement: writeback" in the
trace. Wh
Hi,
I see, so what is the default write policy for default cache in gem5?
Is it write-allocate? or no write allocate? I'm assuming it's
write-allocate with writeback cache?
The gem5 site only says "The default cache is a non-blocking cache
with MSHR (miss status holding register) and WB (
Hi Everyone,
I am trying to run some SPEC2006 benchmarks in Gem5 with the X86_SE
mode. I have the compiled the spec binaries statically and I am
running it with the following command.
build/X86_SE/gem5.opt configs/example/se.py -c test/test-prog/bzip2
--caches --l2cache
However, this be
Thanks for the reply guys but I still can't figure out how this works
exactly. So let me elaborate more:
I tired putting the data files in the same directory as the binary
executable and running it in SE_Mode with the se.py config script
didn't open the files.
What I am confused about is
Hi everyone,
I am trying to run some SPEC06 benchmarks, specifically the bzip2
benchmark in gem5. I used the following command:
build/X86_SE/gem5.opt configs/example/se.py -c bzip2 --caches --l2cache
Notice I put the binary executable in the m5 root directory and all
the data files in the
Thanks for the reply Ali, but how do I reduce the input set? I am new
to all of this, sorry if it seem like a trivial question.
Also I doubt it takes that long to run. When I just execute the binary
by itself in the command line, it takes less than 5 minutes to finish
executing. Would it re
Hi all,
I tried to run the bwaves benchmark from SPEC 2006 in X86_SE mode and
i get the following error:
REAL SIMULATION
info: Entering event queue @ 0. Starting simulation...
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
fatal: syscall ioct
Hi Matt,
I am trying to run some SPEC2006 benchmarks as well and I've tried
running with the se.py method that you mentioned but it seems to work
for certain benchmarks but not others. For example, I was able to run
bzip2 fine but when I tired to run perlbench or bwaves, I get the
followi
Hi,
After changing the code as you described, I still get the same errors.
Do I need to rebuild the system with scons again?
Thanks
Quoting Mahmood Naderan :
For bwaves it is safe to ignore that.
change src/sim/syscall_emul.hh::ioctlFunc() to
switch (req) {
/*case OS::TIOCISATTY
Hi,
I am running some simulation in X86_SE mode and I am looking at the
stats.txt output file and I noticed that there is a difference between
the num_insts simulated in CPU vs num of Cycles simulated in CPU. I
thought that the simulator simulates 1 instruction every clock cycle,
so why i
Hi All,
I am running some SPEC06 benchmarks on X86_SE mode with atomic simple
CPU with L1 and L2 cache. I am trying to analyze the LLC behaviour and
I don't understand some of the statistics in the stat.txt file. I have
several questions:
1) What is the difference between ReadReq_miss and
Hi All,
I am running some simulation in X86_SE mode with atomic cpu model and
I am looking over the stats.txt file and I don't understand why there
is a difference between these two parameters. I thought that each op
would only take one clock cycle to execute in the atomic simple model,
s
Hi All,
I am running some SPEC06 benchmarks on X86_SE mode with atomic simple
CPU with L1 and L2 cache. I am trying to analyze the LLC behaviour and
I don't understand some of the statistics in the stat.txt file. I have
several questions:
1) What is the difference between ReadReq_miss and
Hi Everyone,
I've read some documentation and past archives and I understand that
in the classic memory model, gem5 uses the MOESI snooping protocol and
I also understand that this is always enabled even if there is only
ONE core.
I am running some benchmarks and trying to figure out the
Hi All,
How can I force writebacks of all the dirty cache lines after my
program have finished running in the simulator. What I mean is that
after the program finishes execution, the status of the last level
cache will have some dirty cache lines and I want to force those cache
lines to b
m was posted, but no one posted any solutions
(http://www.mail-archive.com/gem5-users@m5sim.org/msg03832.html).
Please help!!
The Error:
-
File "", line 1, in
File
"/home/zpwu/Documents/repo/Gem5/gem5-new/src/python/m5/main.py", line
3
;", line 1, in
File
"/home/zpwu/Documents/repo/Gem5/gem5-new/src/python/m5/main.py",
line 331, in main
filecode = compile(filedata, filename, 'exec')
File "configs/example/se.py", line 104
for num in xrange(4)
^
SyntaxError: invalid syntax
---
Hi Nilay,
Okay, if forcing the write back is not yet implemented. Then I want to
at least know the number of dirty lines in cache at the end of
simulation. How would I get this stat/parameter? Can you point me to
the right source file if I need to add this myself.
Many Thanks
Quoting Nil
Hi,
I am fairly new to gem5 as well but I managed to get this done by
reading through this thread
(http://www.digipedia.pl/usenet/thread/11778/1757/). You'll have to
change the se.py script to run different workloads in different cpu. I
am not sure what you mean by mesh technology though.
Hi All,
I want to configure a system with multiple CPUs with private L1 and L2
cache with classic memory (not RUBY). Also I don't want to have a
shared L3, so that means all L2 connect to the system memory bus. I've
read this thread
(http://www.mail-archive.com/gem5-users@gem5.org/msg0258
Hi Anthony,
Thanks for your quick reply. Okay so basically, I only need to create
a bus between the L1 and L2 for all cores and then connect all the L2
cache to the membus right? Do you mind sending me your CacheConfig.py
just to make sure I won't make any mistakes.
Thanks
Quoting Antho
Hi all,
I've read this problem in this thread
(http://www.mail-archive.com/gem5-users@gem5.org/msg00645.html).
Basically the problem is that my stats.txt file says that the number
of l2 overall miss is 3768.
But when I use grep on the trace file as follows:
$ cat cache.trc | grep -i -E
Hi All,
I am trying to understand writeback miss and hits. Right now, I only
have a single core with L1 and L2 in my simulation, so there is no
coherency b/w cores.
I want to extract from the simulation the traces for the last level
cache. More specifically the misses that leads to memory
Hi Marko,
I am not sure exactly what you're trying to do but based on your
question I am guessing your trying to run the ffmpeg in the simulator
and feed an input file with .avi extension to it? If thats the case
then you just need to specify the file with the -o option.
For example, when
Hi,
Okay, how did you compile ffmpeg.c to run on your physical machine
then? Is your physical machine x86 or something other than ARM? Ifso,
then you're doing a cross-compile and you need to download the
appropriate cross-compilers for ARM. I believe the gem5 website have
some suggestions
Quoting Marko Zivkovic :
Hello,
how to solve this problem:
root@debian:/home/marko/
Downloads/gem5# ./build/X86/gem5.opt
configs/example/se.py -c ffmpeg -o "--file AVIDemo.avi"
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 c
28 matches
Mail list logo
