Hi All,
I am running some SPEC06 benchmarks on X86_SE mode with atomic simple
CPU with L1 and L2 cache. I am trying to analyze the LLC behaviour and
I don't understand some of the statistics in the stat.txt file. I have
several questions:
1) What is the difference between ReadReq_miss and ReadExReq_miss? and
why does ReadReq_miss + ReadExReq_miss = demand_miss? Since demand is
(read+write) misses according to the comments, does that mean
ReadExReq is writebacks?
system.l2.ReadReq_misses 1032 # number of ReadReq misses
system.l2.ReadExReq_misses 2655 # number of ReadExReq misses
system.l2.demand_misses 3687 # number of demand (read+write) misses
2) What is the difference between Writeback_accesses and writebacks?
Also why is Writeback_hit equal to Writeback_accesses?
system.l2.Writeback_hits 4122 # number of Writeback hits
system.l2.Writeback_accesses 4122 # number of Writeback
accesses(hits+misses)
system.l2.writebacks 4 # number of writebacks
Any feedback is much appreciated! Thanks!!
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