Hi Nilay,
Thanks for your reply. So when L1 is replacing a dirty cache block, L2
receives a writeback request. Now if the cache block exists in L2,
then we have a writeback hit? and if not we have a writeback miss?
Then what is the meaning of "replacement: .... writeback" in the
trace. Why would we do a replacement of another block in L2? Don't we
simply write the dirty block back to main memory if it doesn't exist
in L2?
Best,
Zheng
Quoting Nilay Vaish <ni...@cs.wisc.edu>:
On Mon, 5 Nov 2012, z...@uwaterloo.ca wrote:
Hi All,
I am currently trying to understand the cache trace for L2. I don't
quite understand how the write request are handled. From the trace
I can see ReadReq and ReadExReq. They are either miss or hits.
However, I don't see any trace for 'writes' only see 'writebacks'.
What are the meaning for the following?
-writeback hits
-writeback miss
-writeback replacements
Assuming the caches are writeback and write allocate, the L2 cache should
not receive any write requests. When the L1 cache replaces a dirty
block, the L2 cache will receive a write back request.
--
Nilay
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