I imagine you mean something that can jump to a specific function or symbol
in the tree? I think the go to tool is cscope. It works for C++, but it's
not great since it can't understand namespaces or classes.
There is a tool called "silentbob" supposed to be better for C++, but it's
not maintained
You'll probably want to look at the config.log file (I can't quite remember
if this is what scons calls it) for more details on what is happening.
On Tue, Dec 18, 2012 at 9:45 AM, zhengchl wrote:
> I'm sorry for forgetting describe the building in detail. The building
> succeed except checkin
ystem and could
> reach DRAM by the normal mechanisms? Is it a true statement about lack of
> backpressure? It seems hard to believe because response latency is being
> modeled.
>
> Thanks
>
> Dave
>
>
> On Oct 23, 2012, at 12:49 PM, Paul Rosenfeld wrote:
>
&
Are you certain that the applications are actually using the extra cores
(i.e., are you setting flags for parsecmgmt like -n)? If a single thread
runs on more simulated cores, I'd imagine that the runtime would be
identical while the number of instructions would go up (due to idle threads
running o
assoc=2 --l2_size=4MB --l2_assoc=8 --cacheline_size=64
>> --ruby --garnet-network=flexible --topology=Mesh --mesh-rows=2
>>
>> Thanks,
>>
>> Jia
>>
>>
>> On Mon, Aug 12, 2013 at 9:00 PM, Paul Rosenfeld wrote:
>>
>>> Are you certain that
Hi Andreas,
Thanks for writing this patch. I'm in the process of making some changes to
the DRAMSim2 interface that will eventually be going into the master branch
and be breaking the current API. Since I'm already breaking the API, if you
have any ideas for changes that would make it easier to in
> the directory controller and memory controller model in Ruby so that the
> “normal” gem5 controllers (DRAMSim2 included) can be used in those
> configurations as well.
>
> Let me know if you want to discuss any of these topics further.
>
> Andreas
>
> From: Paul Rosen
Yes, Andreas is correct. Most things in DRAMSim2 happen in units of a DRAM
cycle.
On Wed, Feb 26, 2014 at 1:05 AM, yuhang liu <168liuyuh...@163.com> wrote:
>
> Thanks.
>
> Good answer.
>
> Yuhang
>
>
> At 2014-02-25 07:33:56,"Andreas Hansson" wrote:
>
> Hi Yuhang,
>
> I would imagine it is cou
I believe this is the kernel's address space.
On Tue, Mar 4, 2014 at 9:53 AM, Ahmad Hassan wrote:
> Hi,
>
> I am working with x86 Gem5 full system mode. I can see lot of traffic in
> DRAM controller where the virtual address of the request is equal to the
> (810 Physical_Address) For exampl
Hello all,
This post is not at all meant to discuss git or mercurial and their
relative merits or to turn into a flame war. This is a purely pragmatic
question.
I use git all the time and I'm very comfortable with it -- the hg+queues
workflow just requires a lot of cognitive load for me and I'd j
Thanks for posting this. I am going to be using gem5 on some machines that
I don't have root access on and this is going to be super helpful.
On Fri, Mar 28, 2014 at 10:56 AM, Matt Poremba wrote:
> Hi Christian,
>
>
> This probably isn't exactly the answer you are looking for, but I wrote a
> t
Natty is quite old so you'll need to re-point apt-get to an archive
repository. See here:
http://superuser.com/questions/339537/where-can-i-get-therepositories-for-old-ubuntu-versions
On Fri, Apr 11, 2014 at 7:57 PM, Kuk-Hwan Kim wrote:
>
> Dear Gem5 user community,
>
> I followed youtube examp
Hello,
I'm slowly starting to wrap my head around the way the ISA language works,
but I can't seem to figure out what certain parameters are to a format. For
example in the alpha ISA's decode blocks I see this:
888 0x1f: decode PALMODE {
889 0: OpcdecFault::hw_st_cond();
890
Looking at the code for the ALPHA ISA, I've run across something that's
either an outdated comment or something I don't quite understand.
In particular I'm looking at the code for LoadStoreBase in
src/arch/alpha/isa/mem.isa:
468 # Some CPU models execute the memory operation as an atomic unit
Have you tried the suggestions here:
http://www.mail-archive.com/gem5-users@m5sim.org/msg02886.html ?
On Mon, Jan 9, 2012 at 10:31 AM, Mehmet Burak Aykenar
wrote:
> Hi everyone,
>
> I built gem5 on another machine.. The build was successful, but when I
> tried to simply run "hello" binary I got
that it was no longer needed:
> http://repo.gem5.org/gem5/diff/6cd5f0282d8a/src/arch/alpha/isa/mem.isa
>
> Paul, if you're up for it, it would be great if you update any bad
> comments you find and then submit a patch to reviewboard. Even just
> deleting the bad comments would b
Being a newbie to mercurial (but having used 'quilt' back in the day), I'm
confused about the interaction between queues, the hg repo, and the code
review plugin.
Here's what I did:
hg clone
hg qinit
hg qnew my.patch
[ write some changes ]
hg qrefresh
Now at this point, I've got my series (with
Have you tried to fire up gdb and figure out where the segmentation fault
occurs? That might go a long way in trying to figure out if it's the
library itself or something underlying it (libc mismatch, system call
mismatch, etc).
On Thu, Jan 12, 2012 at 11:48 AM, Hamid Reza Khaleghzadeh <
khalegh
Well, you have to look at the complexity of the instructions in the binary
in terms of how they are simulated. If bzip2 uses some specific
instructions in ISA X which are then simulated in an inefficient way on
host machine Y, you could have a big discrepancy in how long each tick
takes to execute.
Hello,
I'm trying to add my library to the build system -- I've added a
checkLibWithHeader() call in the SConstruct file, but the configure check
returns "no". When I go to the scons_config.log, all I get in the way of an
error is:
288 scons: Configure: Building "build/.scons_config/conftest_12.o
Oh, it turns out the value was cached and didn't update when I fixed up my
header. Deleting the entire build/ directory and re-running scons seems to
have picked up the changes and configure goes through now.
On Tue, Jan 17, 2012 at 11:40 AM, Paul Rosenfeld wrote:
> Hello,
>
>
Hm, does --verbose work for the conftest files? I tried it and it didn't
seem to change the output in the build log.
I think my bigger issue was just the caching -- is there some way to
delete/ignore the cached without deleting the build/ directory?
On Tue, Jan 17, 2012 at 1:50 PM, nathan binke
Ah, great! Looks exactly like what I want, thanks for that.
On Tue, Jan 17, 2012 at 3:19 PM, Matt Poremba wrote:
> Hi Paul,
>
>
> I think this is what you're looking for:
>
> scons --config=force build/foo/gem5.bar
>
>
> For some reason scons seems to just check if the .o files exist, but
> does
I was perusing the code and I stumbled on this little tidbit:
#define M5_VAR_USED __attribute__((unused))
Does it seem confusing to anyone else that the macro name implies that the
variable is used, but then the definition tells gcc that probably the
variable will be unused?
I am just curious if
The other day I stumbled upon this code in tport.cc:
assert(when > curTick());
assert(when < curTick() + SimClock::Int::ms);
There's also a field called:
SimClock::Int::ns;
So perhaps this is what you're looking for.
On Mon, Jan 23, 2012 at 11:21 AM, Mahmood Naderan wrote:
> hi,
> Currently f
Erm, sorry I completely misread your question.
On Tue, Jan 24, 2012 at 2:57 PM, Paul Rosenfeld wrote:
> The other day I stumbled upon this code in tport.cc:
>
> assert(when > curTick());
> assert(when < curTick() + SimClock::Int::ms);
>
> There's also a field
/home/Desktop doesn't sound like the right path ... usually the home folder
is /home/USERNAME/ -- have you double checked to make sure the path is
correct?
On Tue, Jan 31, 2012 at 3:13 AM, Surya Narayanan
wrote:
> Hello,
> Its a basic doubt of how to run a manually compiled program in FS
> m
I presume you are using FS simulation? PARSEC has built in region of
interest hooks which start/stop the simulation at the interesting points in
the simulation. Are you already using these hooks to skip the
startup/boring part of the simulation?
On Fri, Feb 3, 2012 at 8:50 AM, Meeran Mohideeen w
Hello all,
After figuring out how to more or less bend the isa generation system to my
will, I've come across a bit of confusion.
I've written a new instruction format modeled after LoadOrNop. I have a
code block that I pass from the decoder.isa into my instruction format
which is then put into t
On Fri, Feb 3, 2012 at 4:14 PM, Gabriel Michael Black wrote:
> Quoting Paul Rosenfeld :
>
> Hello all,
>>
>> After figuring out how to more or less bend the isa generation system to
>> my
>> will, I've come across a bit of confusion.
>>
>> I
Ah I see. Thanks!
On Fri, Feb 3, 2012 at 10:33 PM, Gabriel Michael Black <
gbl...@eecs.umich.edu> wrote:
> The other confusing thing is I can't figure out if the code block {{ Mem =
Rb.uq + Rc.uq }} actually has any effect if I never substitute it (i.e.
I
never actually write %(cod
Hello all,
I'm trying to modify the TLB code for SimpleTimingCPU, but one thing I
can't seem to find is what the latency of a DTLB miss is. I found the code
in NDtbMissFault->invoke() for reading the page table mapping, but I can't
seem to figure out if there's any mechanism for stalling the CPU t
in
> hardware, then there's a TLB walker component which does memory accesses to
> look up the entry in the page tables, and the delay is determined by those
> accesses.
>
> Gabe
>
>
> Quoting Paul Rosenfeld :
>
> Hello all,
>>
>> I'm trying to m
ct.
>
>
> Gabe
>
> Quoting Paul Rosenfeld :
>
> I guess I forgot to mention in my original email that I was talking about
>> alpha I think in FS it will vector into a PAL routine, but in SE it
>> looks like it's all just faked ...
>>
>>
peline flush (in the simple CPU
> model then pretty much nothing happens). It should be reasonably easy to
> change the model to delay some number of ns on a TLB miss, but you'll get
> the best results by running in fs mode.
>
>
>
> Ali
>
>
>
> On 09.02.2012 0
th a hardware table walker is probably a bit easier to deal
> with.
>
>
>
> Ali
>
>
>
>
>
> On 09.02.2012 10:09, Paul Rosenfeld wrote:
>
> Thanks for the replies. I'm still trying to find my way around M5 and I
> thought the SE/TimingSimpleCPU would be a g
wever, you can probably work
> around this with your benchmark.
>
>
>
> Ali
>
>
>
>
>
>
>
> On 09.02.2012 11:27, Paul Rosenfeld wrote:
>
> Well that doesn't sound like fun. Perhaps I'll look at ARM as a potential
> target.
>
> On Thu, Feb 9, 201
I'm reading through the TLB/table walk code and I've stumbled on the
"walkTrickBoxCheck()" function which appears to be stubbed out (returns
NoFault). However, given that I'm having trouble finding this is any ARM
documentation, I'm intrigued. As far as I can tell it's some kind of
coprocessor? Can
You're talking about SE mode, right?
I think this is akin to a segmentation fault in a regular program.
Essentially you're trying to access a virtual memory page for which the
address is invalid. If there was a kernel running you'd take a page fault
and the kernel would decide if you were allowed
Greetings all,
Currently I'm testing some changes to the ARM model in SimpleTimingCPU. To
cut down on the compile time, I'm selecting only this CPU model by using
the flag CPU_MODELS=TimingSimpleCPU
However, when I go to run gem5 with this command line:
build/ARM/gem5.debug configs/example/se.py
Having made some changes to the Alpha decoder, I decided to make the same
changes to the ARM decoder to move my target there. The wiki talks about
bitfield definitions as being in the .isa files and everything was straight
forward in Alpha.
However, the ARM code does something completely different
Well, as far as I understand GEM5 removes simics and replaces it with M5,
so I think the answer to your question is no, GEM5 does not depend on
simics, but keep in mind that GEMS and GEM5 are different things.
As it says on the GEMS website:
"GEMS is no longer under active development. The effort
But if the address is not valid, what happens if you use it? I think it's
just a way to stop non-determinism before it spreads throughout the
simulation and the root cause of an error becomes obscured.
On Thu, Feb 23, 2012 at 6:41 AM, Mahmood Naderan wrote:
> Hi,
> The getAddr() in packet.hh fi
t; pushed in the vector are no longer valid. However I think this
> assertion should go to somewhere else when a manipulation is going to
> be done on a packet. getAddr() should only return addr.
>
>
> On 2/24/12, Paul Rosenfeld wrote:
> > But if the address is not valid, what
Reading through the ARM code I've come across something puzzling. Take for
example this code from my timing_simple_cpu_exec.cc file that is generated
by the ISA parser:
Fault LOAD_REG_AN_PN_SN_UN_WY_SZ4Acc::initiateAcc(TimingSimpleCPU *xc,
Trace::InstReco
Oh, Is it just assumed that the TLB flags will go into the lowest byte of
the Request flags since the actual request flags seem to start in the
second lowest byte?
On Fri, Feb 24, 2012 at 2:09 PM, Paul Rosenfeld wrote:
> Reading through the ARM code I've come across something puzzling.
I think the FS/SE build distinction has gone away in the development
branch, so if you're using the gem5 repo, then you don't have to do this.
FS/SE is picked by the .py file.
On Fri, Feb 24, 2012 at 3:06 PM, Heba Saadeldeen wrote:
> But in the build_opt there is only ALPHA, they do not differen
Yeah I've been able to compile x86 on our big servers (48gb memory), but
have had trouble on ordinary machines. I'd definitely keep a top window
open and monitor the memory usage. That decoder file is certainly a lot for
a compiler to chew on
On Fri, Feb 24, 2012 at 4:35 PM, Nilay Vaish wr
extra memory. I
> monitored the build with a top window, and I had two active processes: as,
> which used 2.1 GB, and cc1plus, which used 5.7 GB (out of 8 GB total).
>
> Has no one been able to compile gem5.opt for x86 on an ordinary machine?
>
> On Fri, Feb 24, 2012 at 4:46 PM, Paul Ro
I'm not sure such a thing exists (at least publicly). It's been on my todo
list. I have a patch that will hook up DRAMSim2 directly through
physical.cc, but I haven't had a chance to look at ruby at all to see how
to hook it through that.
I also think that probably to make it really conform to the
Were you interested in using full system or syscall emulation mode?
On Mon, Mar 12, 2012 at 11:06 AM, Jinchun Kim wrote:
> Hi, I'm trying to simulate PARSEC on gem5 with x86 machine.
>
> However, I was not able to find any document which discussed implementing
> PARSEC on gem5 with x86.
>
> I've
I think it isn't possible for anyone to give you a definitive answer with
only a GDB backtrace and no code/description. It looks like the 'this'
pointer is NULL for your map iterator. I kind of doubt that's a GCC error
though.
On Wed, Mar 14, 2012 at 8:23 AM, Iordan Alexandru wrote:
>
> Hello
>
Hello all,
I'm making some changes in M5 and I was hoping to add my own DPRINTF flag
to track them through the simulator. I saw that the flags were being
declared in the SConscript files and it looks like they should be
generating a corresponding .hh file in /build/*/debug/
So I've gone in and ad
It looks like the transaction queue in the DRAMSim2's system.ini file is
quite large (512 entries). I'd try to crank down the number of entries in
this queue to something significantly smaller (say 32) and see if you still
hit this assertion.
On Wed, Mar 14, 2012 at 2:10 PM, Ali Saidi wrote:
> *
Ah, I see. That worked. Thank you.
On Wed, Mar 14, 2012 at 2:23 PM, Anthony Gutierrez wrote:
> You need to add the header to the file in which it is being used. E.g.,
> foo.hh. It will be generated.
>
> On Wed, Mar 14, 2012 at 2:19 PM, Paul Rosenfeld wrote:
>
>> Hello all,
I'm sorry this isn't directly a GEM5 question, but my google fu is failing
me.
I have my gem5 repo that I've been working on and making commits directly
to my local repository, but I really should be adding these changes to a
mercurial queue and not straight to the repo. Right now all my changes a
Doesn't the SE mode typically give an error specifically saying the binary
needs to be statically linked? How come this binary slipped past that
check?
On Wed, Mar 28, 2012 at 3:44 PM, Gabe Black wrote:
> **
> Your binary has to be statically linked.
>
> Gabe
>
>
> On 03/28/12 06:01, Mohamed héd
http://www.m5sim.org/Debugging
http://www.m5sim.org/Debugging_M5
I just noticed that there are two pages about debugging M5 and they seem to
have some content overlap but it looks like "Debugging M5" is an outdated
version of the "Debugging" page. Should Debugging M5 just go away?
tting some kind of errors when trying to make wiki
modifications earlier today:
Internal error
Set *$wgShowExceptionDetails = true;* at the bottom of LocalSettings.php to
show detailed debugging information.
On Wed, Apr 4, 2012 at 3:22 PM, Gabe Black wrote:
> On 04/04/12 09:28, Paul R
Are you sure that the code with the arm_detailed model isn't just executing
a different code path that bypasses your couts? (since you didn't specify
where you added your print statements).
On Thu, Apr 5, 2012 at 5:34 PM, Tony Feng wrote:
> Hi,
>
> I plan to collect some data in timing accesses
I don't understand why you would post a thread and then proceed to ignore
the person who replies trying to get more information so they can help you
and then post a new thread asking the same question.
The people on the list aren't paid to answer questions so re-asking the
same question every day
Which directory are you running that command from?
And pardon the obvious question: did you check to make sure there is in
fact a SConstruct file in that folder?
On Fri, May 4, 2012 at 12:03 AM, Bojun Ma wrote:
> Hi,all
> I met some problem when build gem5.
>
> scons build/ARM/gem5.op
For ubuntu, you might have to install the -dev package that matches your
python version. So if you do 'python --version' and it's like 2.6, then you
would do a
sudo apt-get install python2.6-dev
On Tue, May 15, 2012 at 2:00 PM, Victor Zhang wrote:
> Hi! I'm also running into a similar problem. W
As someone who has used (and tried to modify) both marssx86 and gem5, I
would like to add one (potential) benefit to the marssx86 side of things:
the emulation mode (via QEMU) allows you to boot the system very quickly up
to a region of interest and take a checkpoint right before the simulation
lau
There definitely is backpressure on the CPU for regular
> memory accesses.
>
> Steve
>
>
> On Tue, Oct 23, 2012 at 12:49 PM, Paul Rosenfeld wrote:
>
>> As someone who has used (and tried to modify) both marssx86 and gem5, I
>> would like to add one (potential) bene
Another thing to note is that in the master branch of marss, you can expect
the slowdown for running more cores to be pretty much linear (not sure if
this is the case with gem5). QEMU emulates each core in sequence so as you
add cores, the simulation time goes up linearly. They do have some
experim
Hello all,
I was trying to update to a recent version of gem5 master but it appears that
the SystemC frontend no longer builds due to some changes in the DrainManager
and Checkpoint APIs. I'm not familiar with the API changes so it may take me
some time to figure out what is going on. Any chanc
Thanks for pointing out those patches, Andreas. I missed those -- I'll try to
apply those.
Doing a clean build of yesterday's master I get this:
g++ -I../../build/ARM -L../../build/ARM -I./systemc/include
-L./systemc/lib-linux64 -std=c++0x -g -c -o main.o main.cc
main.cc: In member function '
It should be in the ARM full system files:
http://www.gem5.org/dist/current/arm/aarch-system-2014-10.tar.xz
tar --list -f aarch-system-2014-10.tar | grep aarch32
binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
binaries/vmlinux.aarch32.ll_20131205.0-gem5
binaries/vexpress.aarch32.ll_20131205
Hello all,
I'm building the ARM m5 binary in the latest gem5 with arm-linux-gnueabihf-gcc
(Ubuntu 14.04 x86_64) and I'm getting a truncation warning from the assembler:
$ make -f Makefile.arm
arm-linux-gnueabihf-gcc -O2 -I /include/ -I /include/linux -march=armv7-a -o
m5op_arm.o -c m5op_arm.S
m
http://gem5.org/Publications is probably a good place to start.
-Paul
From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Preethi
Neelakantan
Sent: Saturday, January 23, 2016 7:31 PM
To: gem5-users@gem5.org
Subject: [gem5-users] need help in finding papers
Hello
I am going to b
While I haven't done this myself, I believe the process should be largely
analogous to how it works with Android. I think the hardest part is going to be
finding a Mali Linux userspace distribution that is compiled for a platform
similar enough to what gem5 simulates (see here:
http://malidevel
I took a look at the flags I used when running KitKat. It looks like I omitted
the --machine-type flag, had --os-type=android-kitkat and used the
vexpress.aarch32 dtb.
Are you seeing the various "warn: unimplemented instructions" scrolling by in
your gem5 output during boot?
From: gem5-users [
r 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
Thank you for any advice you can give.
>> on behalf of
Paul Rosenfeld (prosenfeld)
mailto:prosenf...@micron.com>>
Sent: Thursday, July 14, 2016 12:19 PM
To: gem5 users mailing list
Subject: Re: [gem5-users] Android KitKat stuck and not booting
I'm not sure why that would happen. I don't see a --mem-size flag on
If you saw the Android logo this is a good sign. Keep waiting -- Android is
very complicated and it's not surprising that it takes a while to simulate the
boot process.
To try to get some more information you can use m5term to connect to the
machine. You should see a shell prompt. If so, you c
Hello all,
I noticed a few problems on the download page ( http://gem5.org/Download ) but
I don't think I have permissions to edit that page.
This section heading still references the "mercurial repository" when
discussing the git repo. Also, I believe the clone address should be https (I
got
able to simply create an account.
Andreas
From: gem5-users
mailto:gem5-users-boun...@gem5.org>> on behalf of
"Paul Rosenfeld (prosenfeld)"
mailto:prosenf...@micron.com>>
Reply-To: gem5 users mailing list
mailto:gem5-users@gem5.org>>
Date: Monday, 6 March 2017 at 19:42
Hello all,
I was hoping to enable the context switch stats dumps on an aarch64 simulation
but I'm hitting an assertion failure and was wondering if anyone had any ideas
before I try to dig into this. The failure is here:
#2 0x015d89fa in ArmISA::vtophys (tc=0x81378e0, addr=2576980458
e1e033b917ba3R114
[4] https://github.com/KarateSnowMachine/gem5/pull/1/files
[5]
https://github.com/KarateSnowMachine/gem5/pull/1/files#diff-10f6b5e8e711c68fd5034bf3fab6a803R286
-Original Message-
From: Paul Rosenfeld (prosenfeld)
Sent: Wednesday, March 08, 2017 9:35 AM
To: gem5 users m
Hello all,
I have been following the instructions for setting up workload automation
(http://gem5.org/WA-gem5) and I've hit a bit of a snag. I've compiled the ARM
Linux kernel 4.3 (https://github.com/gem5/linux-arm-gem5) with the 9P options
enabled, set up diod, and applied the patch to add th
Hello all,
I'm encountering a somewhat strange issue with the latest gem5 master. In a
fresh build directory, I can build either gem5.opt or libgem5_opt.so, but not
one after the other. That is, when I run:
rm -rf build
scons -j32 --without-python --with-cxx-config build/ARM/libgem5_opt.so
E
I'm afraid I can't help you with this directly, but one idea might be to run
your commands through 'strace' and see how gem5 is trying to access /dev/kvm
and how the kernel is reacting to these accesses.
From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Qureshi
Yasir Mahmood
S
Probably what I would recommend is to use the instructions described in the
Workload Automation page (http://www.gem5.org/WA-gem5) to set up 9P filesystem
over VirtIO. Although it does not explicitly state how to do it, with a bit of
work you will be able to access the host file system from insi
It might just be that your graphviz installation wasn’t compiled with pdf
support. You should be able to check by running:
dot -v
From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Timon
Evenblij
Sent: Thursday, January 04, 2018 7:59 AM
To: gem5 users mailing list
Subject: [E
Hello all,
I was trying to set up Workload Automation and everything appears to be going
well on the kernel/boot side but when I cloned the latest WA repo from
https://github.com/ARM-software/workload-automation I didn't see any of the
commands that mounted the 9P filesystem over VirtIO that us
list ; Paul Rosenfeld (prosenfeld)
Subject: [EXT] Re: Workload Automation support in gem5?
I've received the following reply from WA people, though I don't fully
understand it, here it is:
> WA3 still supports gem5, the actual gem5 platform is implemented in devlib
> bu
You could take the approach previously implemented by ARM, which is to add a
few annotations to your kernel that allow you to find the task_info structures
in kernel memory and then ask gem5 to hook the kernel process switch function.
Each time the kernel context switches on a core, you get a ca
work.
Any suggestions?
On Fri, Jan 11, 2019 at 9:27 AM Paul Rosenfeld (prosenfeld)
mailto:prosenf...@micron.com>> wrote:
You could take the approach previously implemented by ARM, which is to add a
few annotations to your kernel that allow you to find the task_info structures
in kernel
Just out of curiosity -- from a simulation results standpoint, softFP will
have different performance characteristics than hardFP, correct?
On Wed, Jul 30, 2014 at 9:17 PM, jerry yin via gem5-users <
gem5-users@gem5.org> wrote:
> Hi Anthony,
>
> Thank you! Although I remember having tried both v
hat needs to be
> hand optimized.
>
>
> Anthony Gutierrez
> http://web.eecs.umich.edu/~atgutier
>
>
> On Thu, Jul 31, 2014 at 10:06 AM, Paul Rosenfeld via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Just out of curiosity -- from a simulation results
Andreas,
Could you give a summary of what kinds of changes would be necessary to fix
this issue and how difficult they would be? x86 is not my forte and I've
only messed around with the decode/execute part of gem5 once a while back.
However, we would be interested in having x86 SMP support with cl
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